KR101673241B1 - Method for fabricating tandem solar cell with thin film silicon and bulk crystalline silicon using silicon thin film tunnel junction layer by PECVD and solar cell thereof - Google Patents

Abstract

The present invention relates to a silicon thin film tunnel junction formed by a plasma chemical vapor deposition method capable of improving the efficiency of a solar cell by forming a tunnel junction layer having a nanocrystalline structure by using a chemical vapor deposition method between a bulk crystalline solar cell and a thin film solar cell Layer crystalline silicon and a solar cell using the same.
For example, a bulk crystalline solar cell forming a bulk crystalline solar cell, which is a bottom cell, A tunnel junction layer forming step of forming a tunnel junction layer made of a silicon thin film on the bulk crystalline solar cell; And forming a thin film solar cell, which is an upper cell, on the tunnel junction layer, wherein the tunnel junction layer electrically connects the crystalline solar cell and the thin film solar cell by a tunneling effect, Wherein the tunnel junction layer is formed by a plasma chemical vapor deposition method and a solar cell according to the method.

Description

TECHNICAL FIELD The present invention relates to a method of fabricating a laminated solar cell of a thin film silicon and a bulk crystalline silicon using a silicon thin film tunnel junction layer formed by a plasma CVD method and a solar cell using the thin film silicon and a bulk crystalline silicon film tunnel junction layer by PECVD and solar cell thereof < RTI ID = 0.0 >

The present invention relates to a method of manufacturing a laminated solar cell of a thin film silicon and a bulk crystalline silicon using a silicon thin film tunnel junction layer formed by a plasma chemical vapor deposition method, and a solar cell therefor.

Generally, the types of silicon solar cells are divided into a substrate type and a thin film type according to the type of material. The substrate-type silicon solar cell is divided into a single-crystalline silicon solar cell and a polycrystalline silicon solar cell according to a material used as a light absorption layer. Thin-film silicon solar cells are also classified into amorphous silicon (a-Si: H) solar cells and micro-crystalline silicon (c-Si: H) solar cells depending on materials used as the light absorption layer. Since a silicon wafer is used to obtain a crystalline silicon substrate, the production cost is high and it is required to undergo complicated steps in the process, so that productivity is low but the photoconversion efficiency is high. On the other hand, amorphous silicon solar cells have a disadvantage in that they are low in material cost and suitable for continuous mass production process, but have low photoconductivity. Therefore, in order to improve the efficiency of the solar cell by complementing these drawbacks, many companies, research institutes and universities are actively conducting researches.

The present invention provides a method for manufacturing a laminated solar cell of thin film silicon and bulk crystalline silicon using a silicon thin film tunnel junction layer formed by a plasma chemical vapor deposition method capable of improving the efficiency of a solar cell, and a solar cell therefor.

A method of manufacturing a solar cell according to the present invention includes: forming a bulk crystalline solar cell to form a bulk crystalline solar cell as a lower cell; A tunnel junction layer forming step of forming a tunnel junction layer made of a silicon thin film on the bulk crystalline solar cell; And forming a thin film solar cell, which is an upper cell, on the tunnel junction layer, wherein the tunnel junction layer electrically connects the crystalline solar cell and the thin film solar cell by a tunneling effect, And the tunnel junction layer is formed by a plasma chemical vapor deposition method.

In the tunnel junction layer forming step, an n-type tunnel junction layer made of an n-type silicon thin film is formed on the bulk crystalline solar cell, and a p-type tunnel junction layer made of a p-type silicon thin film is formed on the n- Can be formed.

The n-type tunnel junction layer SiH ₄ and H ₂ and is formed by a plasma chemical vapor deposition method using a PH ₃ gas and the SiH ₄ and H ₂ and the ratio of PH ₃ gas was 1: 200: may be 0.08 days.

The p-type tunnel junction layer SiH ₄ and H ₂ and B ₂ is formed by a plasma chemical vapor deposition method using a H ₆ gas, the SiH ₄ and H ₂ and B ₂ ratio of H ₆ gas was 1: 240: Number 0.06 il have.

The thickness of the n-type tunnel junction layer and the thickness of the p-type tunnel junction layer may be 1 nm to 10 nm, respectively.

The temperature of the tunnel junction layer forming step may be 160 캜 to 195 캜.

The tunnel junction layer may have a nanocrystalline structure.

Wherein the step of forming the bulk crystalline solar cell comprises: preparing a semiconductor substrate of a first conductive type; Forming an emitter layer on the front and rear surfaces of the semiconductor substrate; Removing a PSG formed on the semiconductor substrate; And a lower emitter layer removing step of removing the emitter layer formed on the rear surface of the semiconductor substrate.

The thin film solar cell forming step may include: a PIN semiconductor layer forming step of forming a PIN semiconductor layer in which a P-type silicon layer, an I-type silicon layer and an N-type silicon layer are sequentially stacked on the tunnel junction layer; A transparent electrode layer forming step of forming a transparent electrode layer on the PIN semiconductor layer; And forming a front electrode on the transparent electrode layer and forming a rear electrode on the rear surface of the semiconductor substrate.

An embodiment of the present invention includes a solar cell manufactured by the above-described method.

In one embodiment of the present invention, an n-type tunnel junction layer and a p-type tunnel junction layer are deposited between a bulk crystalline solar cell and a thin film solar cell by chemical vapor deposition to form a tunnel junction layer having a nanocrystalline structure, The present invention also provides a method for manufacturing a laminated type solar cell of thin film silicon and bulk crystalline silicon using a silicon thin film tunnel junction layer formed through a plasma chemical vapor deposition method capable of improving the efficiency of a solar cell.

1 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
2A to 2J are views for explaining a method of manufacturing a solar cell according to an embodiment of the present invention.
3A is a graph showing the degree of crystallization of the n-type tunnel junction layer by the Raman analysis method.
3B is a graph showing the degree of crystallization of the p-type tunnel junction layer by Raman analysis.
4 is a graph showing the voltage-current density characteristics of the tunnel junction layer.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, The present invention is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

In the following drawings, thickness and size of each layer are exaggerated for convenience and clarity of description, and the same reference numerals denote the same elements in the drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" include singular forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups.

Although the terms first, second, etc. are used herein to describe various elements, components, regions, layers and / or portions, these members, components, regions, layers and / It is obvious that no. These terms are only used to distinguish one member, component, region, layer or section from another region, layer or section. Thus, a first member, component, region, layer or section described below may refer to a second member, component, region, layer or section without departing from the teachings of the present invention.

1 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention. 2A to 2J are views for explaining a method of manufacturing a solar cell according to an embodiment of the present invention.

Referring to FIG. 1, a method for fabricating a solar cell according to an embodiment of the present invention includes forming a bulk crystalline silicon solar cell (S10), forming a tunnel junction layer (S20), and forming a thin film solar cell (S30).

Specifically, the step of forming a bulk crystalline solar cell (S10) used as a lower battery includes a semiconductor substrate preparing step (S11), an emitter layer forming step (S12), a PSG removing step (S13), and a lower emitter removing step . The thin film solar cell forming step S30 used as the upper cell includes a PIN semiconductor layer forming step S31, a transparent electrode layer forming step S32, and an electrode forming step S33. Here, the bulk-type crystalline solar cell, which is a lower cell, is a bulk crystalline silicon, and the thin-film solar cell, which is an upper cell, is also referred to as thin-film silicon. Hereinafter, the steps of FIG. 1 will be described with reference to FIGS. 2A to 2J.

2A, the semiconductor substrate preparation step S11 has a substantially flat front surface 111 (upper surface) and a substantially flat rear surface 112 (lower surface) opposite to the front surface 111, A semiconductor substrate 110 doped with a conductive impurity is prepared. For example, the semiconductor substrate 110 may be a P-type silicon semiconductor substrate. That is, the semiconductor substrate 110 may be a P-type silicon semiconductor substrate doped with an impurity such as boron (B) or gallium (Ga), which is a Group 13 element in the periodic table of the silicon semiconductor substrate.

Also, in the semiconductor substrate preparation step S11, as shown in FIG. 2B, a texturing process for forming the concave-convex structure 113 on the surface of the semiconductor substrate 110 may be performed. If the surface of the semiconductor substrate is formed with a concave-convex structure through the texturing process, the ratio of incident sunlight to the outside is reduced and the proportion of the solar cell absorbed by scattering of sunlight increases, There is an effect to be promoted. The texturing process may be performed using a wet process using a solution of NaOH, KOH, IPA, HNO ₃ , HF, or the like.

2C, the emitter layer 120 of the second conductivity type is formed on the front surface 111 and the rear surface 112 of the semiconductor substrate 110 in the emitter layer forming step S12. In the emitter layer formation step S12, thermal diffusion doping of phosphorus (P) is performed on the semiconductor substrate 110 to form the emitter layer 120 of the second conductivity type. For example, POCL ₃ , H ₃ PO ₄ , and the like may be doped to the semiconductor substrate 110 by thermal diffusion in the emitter layer forming step S 12. The emitter layer 120 includes an upper emitter layer 121 formed on a front surface 111 of the semiconductor substrate 110 and a lower emitter layer 122 formed on a rear surface 112 of the semiconductor substrate 110.

On the other hand, when a doping process is performed using a compound containing phosphorus (P), a phosphorus silicate glass (PSG) 123 is formed on the surface of the semiconductor substrate 110 together with the formation of the emitter layer 120 . The PSG 123 should be removed in the next step.

2D, in the PSG removal step S13, the PSG 123 formed on the surface of the semiconductor substrate 110 is removed. The PSG 123 can be removed by treating it with about 5 to 10% of diluted HF solution for about 15 seconds.

As shown in FIG. 2E, in the lower emitter layer removing step S14, the lower emitter layer 122 is etched and removed. In the lower emitter layer removing step S14, the lower emitter layer 122 formed on the rear surface of the semiconductor substrate 110 is etched and removed, thereby preventing a leakage current during the solar cell operation. After the lower emitter layer removing step (S14) may be a cleaning process is performed using _{SC1 (NH 4 O + H 2} O 2 + H 2 O).

A bulk crystalline type solar cell comprising a first conductive semiconductor substrate 110 and a second conductive emitter layer 121 formed on the front surface 111 of the semiconductor substrate 110 through the above- The battery 10 is completed.

Next, the tunnel junction layer 130 is formed on the upper part of the bulk crystalline solar cell 10, which is a lower battery.

As shown in FIG. 2F, in the tunnel junction layer forming step S20, a tunnel junction layer 130 is formed on the bulk crystalline solar cell 10, which is a lower battery. Specifically, in the tunnel junction layer formation step S20, a silicon thin film is deposited on the upper emitter layer 121 through plasma enhanced chemical vapor deposition (PECVD) to form a tunnel junction layer 130 . The tunnel junction layer 130 electrically connects the bulk crystalline solar cell 10, which is a lower cell, with the thin film solar cell 20, which will be described later, by a tunneling effect. The tunnel junction layer 130 may be approximately 2 nm to 20 nm, preferably 10 nm. When the thickness of the tunnel junction layer 130 is less than 2 nm, it is difficult to deposit the tunnel junction layer 130 on the emitter layer 121. If the thickness of the tunnel junction layer 130 is larger than 20 nm, the tunneling effect can not be expected. Therefore, an effective Ohmic contact is formed between the bulk crystalline solar cell 10, which is a lower battery, contact can not be formed.

The tunnel junction layer 130 includes an n-type tunnel junction layer 131 and a p-type tunnel junction layer 132. An n-type tunnel junction layer 131 is formed on the upper emitter layer 121 and a p-type tunnel junction layer 132 is formed on the n-type tunnel junction layer 131.

First, the n-type tunnel junction layer 131 is formed by a plasma chemical vapor deposition method using SiH ₄ , H _2, and PH ₃ gas. The conditions for forming the n-type tunnel junction layer 131 include a ratio of SiH ₄ to H ₂ and PH ₃ gas of 1: 200: 0.08, a temperature of about 195 ° C., a power of 13 W, The process pressure is 2.5 Torr to form an n-type tunnel junction layer 131 made of an n-type silicon thin film. The thickness of the n-type tunnel junction layer 131 may be approximately 1 nm to 10 nm, preferably 5 nm.

Next, the p-type tunnel junction layer 132 is formed by a plasma chemical vapor deposition method using SiH ₄ , H _2, and B ₂ H ₆ gas. The conditions for forming the p-type tunnel junction layer 132 include a ratio of SiH ₄ to H ₂ and B ₂ H ₆ gas of 1: 240: 0.06, a temperature of about 160 ° C, a power of 13 W And a process pressure of 3 Torr to form a p-type tunnel junction layer 132 made of a p-type silicon thin film. The thickness of the p-type tunnel junction layer 132 may be approximately 1 nm to 10 nm, preferably 5 nm.

That is, the temperature for performing the tunnel junction layer formation step (S20) may be about 160 ° C to 195 ° C. Here, if the temperature is lower than 160 ° C or higher than 195 ° C, it is not suitable to form the tunnel junction layer 130 having the above characteristics.

As shown in FIG. 2G, the PIN semiconductor layer 140 is formed on the tunnel junction layer 130 in the step of forming the PIN semiconductor layer (S31). Specifically, in the PIN semiconductor layer forming step S31, a P-type silicon layer 141, an I-type silicon layer 142 and an N-type silicon layer 143 are sequentially stacked on the tunnel junction layer 130 . The PIN semiconductor layer 140 may be formed by a plasma image deposition method. In the PIN semiconductor layer 140, the I-type silicon layer 142 is depleted by the P-type silicon layer 141 and the N-type silicon layer 143 to generate an electric field therein, The generated holes and electrons are drifted by the electric field and collected in the P-type silicon layer 141 and the N-type silicon layer 143, respectively.

As shown in FIG. 2h, the transparent electrode layer 150 is formed on the PIN semiconductor layer 140 in the transparent electrode layer forming step S32. In detail, the transparent electrode layer 150 may be formed on the N-type silicon layer 143 in the transparent electrode layer forming step S32. The transparent electrode layer 150 is an electrode through which solar light is incident and transmitted. Therefore, the transparent electrode layer 150 can be any material that prevents deterioration of light transmittance, has a low specific resistance, and has a good surface roughness. For example, the transparent electrode layer 150 may be formed of indium tin oxide (ITO), fluorine tin oxide (FTO), indium zinc oxide (IZO), or zinc oxide (ZnO). In addition, the transparent electrode layer 150 may be formed using a sputtering method.

2I and 2J, in the electrode forming step S33, the front electrode 160 is formed on the transparent electrode layer 150 and the rear surface of the semiconductor substrate 110 Electrode 170 is formed. The front electrode 160 may be formed of silver (Ag) and / or aluminum (Al), and the rear electrode 170 may be formed of aluminum (Al). In the electrode forming step S33, the front electrode 160 and the rear electrode 170 may be formed using a sputtering method or a screen printing method.

The solar cell 100 according to an embodiment of the present invention is completed by the above-described manufacturing method. The solar cell 100 includes a bulk crystalline solar cell 10 as a lower battery and a thin film solar cell 20 and a bulk crystalline solar cell 10 stacked on top of the bulk crystalline solar cell 10, And a tunnel junction layer 130 interposed between the solar cells 20.

3A is a graph showing the degree of crystallization of the n-type tunnel junction layer by the Raman analysis method. 3B is a graph showing the degree of crystallization of the p-type tunnel junction layer by Raman analysis.

As shown in FIG. 3A, Raman analysis was performed to obtain the crystallinity and the crystalline volume fraction of the n-type tunnel junction layer 131. The n-type tunnel junction layer 131 was 520 cm ^-1 . ≪ / RTI > Generally, in the Raman analysis, amorphous silicon exhibits a peak value at 480 cm ^-1 and crystalline silicon exhibits a peak value at 520 cm ^-1 . Also, as the crystalline phase increases, the peak value at 520 cm < ^-1 > That is, the n-type tunnel junction layer 131 of the present invention shows a peak at 520 cm ^-1 , and thus has a crystalline structure. Such a crystallization fraction of the thin film can be calculated using Raman analysis. After obtaining a crystallized fraction is 510㎝ ^-1, cumulative intensity (Integrated intensity) of 520㎝ ^{-1 -1} 480㎝ having crystalline properties with the amorphous characteristics in Raman analysis can be determined by the following equation.

That is, as the crystallization fraction increases, it can be interpreted as having a structural characteristic close to crystalline. The crystallization fraction Xc of the n-type tunnel junction layer 131 was calculated to be approximately 88.13%. Accordingly, it can be seen that the n-type tunnel junction layer 131 has a nanocrystalline structure.

3B, Raman analysis was performed to obtain the crystallinity and the crystalline volume fraction of the p-type tunnel junction layer 132, and the p-type tunnel junction layer 132 Lt; ^-1 > cm < ^{-1 &} gt ;. In addition, the crystallization fraction Xc of the p-type tunnel junction layer 132 was calculated to be approximately 86.21%. Therefore, it can be seen that the p-type tunnel junction layer 132 has a nanocrystalline structure.

4 is a graph showing the voltage-current density characteristics of the tunnel junction layer.

4, when the tunnel junction layer 130 is formed of the n-type tunnel junction layer 131 and the p-type tunnel junction layer 132 as in the present invention, the efficiency of the solar cell 100 is 10.33% Able to know. It can be seen that the tunnel junction layer 130 is higher in efficiency than the tunnel junction layer formed only of the p-type tunnel junction layer (E _ff = 9.48%) or the tunnel junction layer (E _ff = 9.82%) .

As described above, the solar cell 100 according to an embodiment of the present invention includes the n-type tunnel junction layer 131 and the p-type tunnel junction layer 131 by chemical vapor deposition between the bulk crystalline solar cell 10 and the thin film solar cell 20, The efficiency of the solar cell 100 can be improved by depositing the bonding layer 132 to form the tunnel junction layer 130 having the nanocrystalline structure.

Although the present invention has been described in connection with what is presently considered to be preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

10: Bulk type crystalline solar cell 20: Thin film solar cell
100: solar cell 110: semiconductor substrate
120: Emitter layer 121: Upper emitter layer
122: lower emitter layer 130: tunnel junction layer
131: n-type tunnel junction layer 132: p-type tunnel junction layer
140: PIN semiconductor layer 141: P-type silicon layer
142: I-type silicon layer 143: N-type silicon layer
150: transparent electrode layer 160: front electrode
170: rear electrode

Claims (10)

A bulk crystalline solar cell forming a bulk crystalline solar cell as a lower cell;
A tunnel junction layer forming step of forming a tunnel junction layer made of a silicon thin film on the bulk crystalline solar cell; And
And forming a thin film solar cell, which is an upper cell, on the tunnel junction layer,
Wherein the tunnel junction layer electrically connects the crystalline solar cell and the thin film solar cell by a tunneling effect, the tunnel junction layer is formed through a plasma chemical vapor deposition method,
In the tunnel junction layer forming step, an n-type tunnel junction layer made of an n-type silicon thin film is formed on the bulk crystalline solar cell, and a p-type tunnel junction layer made of a p-type silicon thin film is formed on the n- Lt; / RTI >
And 0.08: the n-type tunnel junction layer SiH ₄ and H ₂ and is formed by a plasma chemical vapor deposition method using a PH ₃ gas and the SiH ₄ and H _2, and PH ₃ gas ratio of 1: 200
The p-type tunnel junction layer SiH ₄ and H ₂ and B ₂ is formed by a plasma chemical vapor deposition method using a H ₆ gas, the SiH ₄ and H ₂ and B ₂ ratio of H ₆ gas was 1: 240: 0.06, and
Wherein the tunnel junction layer has a nanocrystalline structure. delete delete delete The method according to claim 1,
Wherein the thickness of the n-type tunnel junction layer and the thickness of the p-type tunnel junction layer are 1 nm to 10 nm, respectively. The method according to claim 1,
Wherein the temperature of the step of forming the tunnel junction layer is in the range of 160 캜 to 195 캜. delete The method according to claim 1,
The step of forming the bulk crystalline solar cell
A semiconductor substrate preparation step of preparing a semiconductor substrate of a first conductivity type;
Forming an emitter layer on the front and rear surfaces of the semiconductor substrate;
Removing a PSG formed on the semiconductor substrate; And
And a lower emitter layer removing step of removing the emitter layer formed on the rear surface of the semiconductor substrate. 9. The method of claim 8,
The thin film solar cell forming step
A PIN semiconductor layer forming step of forming a PIN semiconductor layer in which a P-type silicon layer, an I-type silicon layer and an N-type silicon layer are sequentially stacked on the tunnel junction layer;
A transparent electrode layer forming step of forming a transparent electrode layer on the PIN semiconductor layer; And
Forming a front electrode on the transparent electrode layer, and forming a rear electrode on the rear surface of the semiconductor substrate. A solar cell produced by the method according to any one of claims 1, 5 to 6, and 8 to 9.

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