KR20120098012A - Semiconductor package with through silicon via and mehtod for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor package with a through silicon via and a manufacturing method thereof are provided to prevent the reduction of a net-die by forming a bump alignment key in an area except the net-die on a wafer. CONSTITUTION: A through silicon via(26) and a bump alignment key(27) pass through a wafer. A bump is connected to the through silicon via. The bump alignment key is formed in the outside of the wafer and has a cross shape.

Description

Semiconductor package having through-silicon via and manufacturing method therefor {SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIA AND MEHTOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor package having through silicon vias and a method for manufacturing the same.

Among packaging technologies of semiconductor integrated circuits, three-dimensional lamination technology has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance thereof. The package using the three-dimensional stacking technology is a package in which a plurality of chips having the same storage capacity are stacked, and is generally called a stack package. The stack package has an advantage in that the data storage capacity can be increased very easily, but there is a disadvantage in that a wiring space for electrical connection inside the package is insufficient as the number and size of chips stacked are increased.

In order to solve this drawback of the stack package, a structure using a through silicon via (TSV) has been proposed. In recent years, a through electrode made of a conductive material is formed in a semiconductor chip to form the through electrode. The method of electrically connecting the semiconductor chips through the is used.

The through electrode enables bonding of fine pitch I / O pads, thereby increasing the number of I / O pads, and improving signal transmission speed between chips by forming a plurality of I / O pads. 3D design can further improve the performance of the semiconductor chip itself.

On the other hand, through-silicon vias (TSV) are formed through 'via first, via middle and via last processes' classified according to when the vias are formed.

1A and 1B illustrate a method of manufacturing a semiconductor package having a through silicon via (TSV) according to the prior art. The prior art is a method according to the Via middle process.

As shown in FIG. 1A, the first insulating layer 12 is formed on a device wafer 11 on which a transistor or the like is formed, and then penetrates the first insulating layer 12 and the device wafer 11 to a predetermined depth. Through-silicon via (TSV) 13 is formed.

Subsequently, the device wafer 11 is fab-outed and then a package front process is performed. The first bump 15 is formed on the metal pad 14 through the package front process. Multi-layered metal wirings 14A and 14B and a multi-layered second insulating layer 14D are formed on the first insulating layer 12. The multi-layered metal wires 14A and 14B are connected via the metal contact 14C.

Subsequently, the carrier wafer 17 is bonded to the front surface of the device wafer 11 using the tape 16, and then the back surface of the device wafer 11 is back ground. As a result, the through silicon via 13 is exposed.

Subsequently, after the third insulating layer 14 is coated on the back surface of the device wafer 11, an open process is performed to expose the through silicon vias 13. As a result, the open portion 19 is formed.

As shown in FIG. 1B, a second bump 20 is formed to be connected to the through silicon via 13 through the open part. A barrier metal and a seed layer 19 for bump plating are formed under the second bump 20.

After the second bump 20 is formed, the carrier wafer 17 is separated. Subsequently, the device wafer 11 is fixed to a mount tape, and wafer sawing is performed to separate the individual wafers. Then chip bonding is performed.

The prior art as described above, so that the bump is formed accurately on the through-silicon via 13 when the open portion 18A is formed after coating of the third insulating layer 18 for forming the bump that proceeds after the backgrinding. Although the alignment should be performed, the alignment process is now performed by aligning the key pattern of the metal layer formed in the device wafer 11 by transmitting the light source through the device wafer 11, thereby reducing the accuracy. do.

In order to compensate for the accuracy of the alignment, the size of the TSV hole is increased by the alignment inaccuracy.

However, since the through hole needs to be increased by the alignment inaccuracy, the die size in the wafer is increased, thereby reducing the net-die. In addition, as the through-hole size increases, the process time for forming the through-silicon via increases and the total amount of the filling material in the through-hole increases, so that problems such as through hole extrusion and warpage increase are complicated. Is occurring.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package and a method of manufacturing the same, which can improve the alignment accuracy for bump formation without increasing the die size and through hole size.

The semiconductor package of the present invention for achieving the above object is a wafer through which the through-silicon via and bump alignment key is passed; And bumps connected to the through silicon vias, wherein the bump alignment keys are formed in an outer region of the wafer or in a region other than the net die of the wafer.

In addition, the semiconductor package manufacturing method of the present invention comprises the steps of etching the device wafer to a predetermined depth to simultaneously form the through-hole and bump alignment key hole; Forming a through silicon via embedded in the through hole and a bump alignment key embedded in the bump alignment key hole; Thinning a back surface of the device wafer to expose the through silicon vias; Forming an insulating layer having an open portion exposing the through silicon vias; And forming a bump embedded in the open part and connected to the through silicon via.

According to the present invention, the accuracy of alignment is compensated for, and the size of the through-silicon via may be optimized according to the improved accuracy, rather than increasing the size of the existing through-hole by the alignment inaccuracy. This can reduce die size in the wafer, increase net die, and shorten the through silicon via formation process time. In addition, since the total amount of the filling material in the through-holes is reduced, it may contribute to improved yield and reliability by improving through-hole protrusion and warpage.

In addition, since the bump alignment key is formed in a region other than the net die in the wafer, it is possible to prevent a net die reduction.

In addition, concerns such as increased die size and net die reduction and the influence of transistors around the bump alignment key caused by bump alignment key formation in the die can be prevented.

1A and 1B illustrate a method of manufacturing a semiconductor package having through silicon vias according to the prior art.
2 illustrates a semiconductor package having through silicon vias according to an embodiment of the present invention.
3A to 3I illustrate a method of manufacturing a semiconductor package having through silicon vias according to an embodiment of the present invention.
4 is a photograph showing a shape in which a bump alignment key is added to an outer region of a wafer according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

The present invention forms a bump alignment key at the same time when forming through silicon via (TSV) so as to be directly aligned with the bump alignment key exposed after wafer backgrinding.

The bump align key is formed in a dummy die area outside the wafer or a non-net die area (the vignette die area) outside the wafer.

2 illustrates a semiconductor package having through silicon vias according to an embodiment of the present invention.

Referring to FIG. 2, through-silicon vias 26 penetrating through the device wafer 21A are formed. The device wafer 21A has a back side and a front side and has a thin thickness by backgrinding. The bump alignment key 27 penetrates through the apparatus wafer 21A. The bump alignment key 27 is simultaneously formed when the through silicon via 26 is formed. The metal pad 28 and the first bump 29 are formed on the front surface of the device wafer 21A. A second bump 36 is formed on the rear surface of the device wafer 21A to be connected to the through silicon via 26. The barrier metal and the seed layer 34 are formed between the second bump 36 and the through silicon via 26. The first insulating layer 22 is formed on the entire surface of the device wafer 21A, and the multi-layered metal wirings 28A and 28B and the multi-layered second insulating layer 28D are formed on the first insulating layer 22. The multi-layered metal wirings 28A and 28B are connected through the metal contacts 28C.

The bump alignment key 27 has, for example, a cross shape.

3A to 3I illustrate a method of manufacturing a semiconductor package having through silicon vias according to an embodiment of the present invention. Hereinafter, the example is a method according to a via middle process.

As shown in FIG. 3A, the first insulating layer 22 is formed on the entire surface of the wafer 21. A transistor (not shown) or the like may be formed on the wafer 21. Hereinafter, the wafer is abbreviated as device wafer 21. The device wafer 21 includes a silicon wafer.

Subsequently, the through wafer 24 is formed by etching the device wafer 21 at a predetermined depth. First, a mask 23 for forming a through hole is formed on the first insulating layer 22. The mask 23 can be formed using a photosensitive film. Next, the through hole 24 is formed by etching the first insulating layer 22 and the device wafer 21 by a predetermined depth using the mask 23 as an etch barrier. The present invention simultaneously forms bump alignment key holes 25 for bump alignment keys (or 'through-silicon via keys') when the through holes 24 are formed. The bump alignment keyhole 25 is formed in the outer region of the device wafer 21, in particular in the dummy die region or in a region other than the net die outside the wafer. The depths of the through hole 24 and the bump alignment key hole 25 may be the same.

As shown in FIG. 3B, after the mask 23 is stripped, the through hole 24 and the bump alignment key hole 25 are buried using the conductive layer. Here, the conductive layer includes a metal layer. The conductive layer embedded in the through hole 24 becomes through silicon via (TSV) 26. The conductive layer embedded in the bump alignment keyhole 25 becomes the bump alignment key 27. The through silicon via 26 and the bump alignment key 27 may be formed using copper (Cu). In order to fill the through silicon via 26 and the bump alignment key 27, the conductive layer may be planarized using chemical mechanical polishing (CMP) or the like. Although not shown, an insulating layer may be formed on the surface of the through hole 24 and the bump alignment key hole 25 to insulate the through silicon via 26 and the bump alignment key 27 from the device wafer 21. .

As shown in FIG. 3C, a package front process is performed on the device wafer 21 in which the through silicon via 26 and the bump alignment key 27 are formed. The metal pad 28 and the first bump 29 are formed through the package front process. Before the metal pad 28 is formed, multiple metal wires 28A and 28B may be formed. The metal pad 28 is formed using a metal layer. The multi-layered metal wires 28A and 28B may be connected through the metal contact 28C, and the uppermost metal wire 28B and the metal pad 28 of the metal wires may be connected to each other through the metal contact 28C. A second insulating layer 28D is formed between the metal wires 28A and 28B and the metal pad 28. The second insulating layer 28D is formed of a multilayer when the metal wirings 28A and 28B are multilayer. The second insulating layer 28D includes an inter layer dielectric (ILD) or an inter metal dielectirc (IMD). The formation method of the 1st bump 29 uses a well-known method. For example, after the photoresist pattern is formed to have an open portion on which the first bump 29 is to be formed, a copper-solder is electroplated on the open portion, and then the photoresist pattern is stripped. The first bump forming method may follow the subsequent second bump forming method.

As shown in FIG. 3D, the carrier wafer 31 is bonded to the front surface of the apparatus wafer 21. The device wafer 21 and the carrier wafer 31 are bonded using a tape 30. The tape 30 is also referred to as a tape for fabricating wafer (TF). The carrier wafer 31 is a wafer for facilitating the handling of the device wafer 21.

The carrier wafer 31 (also referred to as a carrier substrate) may be formed of glass, Si, glass ceramics, or the like. The carrier wafer 31 has a resistivity of 1 × ^{10 8} Ohm-cm or less. By reducing the resistivity of the carrier wafer 31, in subsequent processes, the carrier wafer 31 can be more reliably fixed to an electrostatic chuck (ESC). The diameter of the carrier wafer 31 is larger than the diameter of the device wafer 21.

When bonding the apparatus wafer 21 and the carrier wafer 31, the apparatus wafer 21 is turned upside down.

As shown in FIG. 3E, the backside of the device wafer 21 bonded to the carrier wafer 31 is backgrinded. This exposes the through silicon via 26 and the bump alignment key 27. By backgrinding, the device wafer is thinned as shown by reference numeral 21A.

As shown in FIG. 3F, the third insulating layer 32 is coated on the back surface of the apparatus wafer 21A subjected to backgrinding. The third insulating layer 32 is for insulating the back surface of the device wafer 21A. In addition, to provide an open portion in which the subsequent second bumps are to be formed.

Subsequently, an open process is performed to expose the through silicon vias 26. In the open process, the third insulating layer 32 is etched using the photoresist film as an etch barrier using a mask on which a mask is formed. As a result, an open portion 33 exposing the through silicon vias 26 is formed. In this case, direct overlay correction of the open unit 33 may be performed using the bump alignment key 27.

As shown in FIG. 3G, the barrier metal and the seed layer 34 are deposited on the entire surface including the open part 33, and then a bump photoresist pattern Bump PR 35 is formed. Subsequently, a second bump 36 is formed in the open portion of the bump photoresist pattern. The second bumps 36 may be formed by stacking Cu / Ni / Au.

As shown in FIG. 3H, after the bump photoresist pattern 35 is removed, the barrier metal and the seed layer 34 are etched.

As shown in FIG. 3I, the tape 30 and the carrier wafer 31 are removed. This is called debonding.

Although not shown, the device wafer 21A is subsequently fixed to a mount tape, and wafer sawing is performed to separate the individual wafers. Then chip bonding is performed.

FIG. 4 is a photograph showing a shape in which a bump alignment key is added to an outer region of a wafer according to an exemplary embodiment of the present invention, and is actually used in an exposure map and inline macro inspection equipment in photo equipment. Wafer image.

Referring to FIG. 4, a bump alignment key is added to a dummy die area outside the wafer. In particular, the circular display area of the outer dummy die area of the wafer is the area where the bump alignment key is formed.

The bump alignment key, for example, has a cross shape, as shown in the right picture.

According to the above, the present invention can improve the accuracy of the alignment by forming the bump alignment key so that the size of the through-silicon via can be optimized according to the improved accuracy without increasing the size of the through hole by the alignment inaccuracy. .

For example, in the past, the overlay management level maintains the through hole size of 9 µm or more with the opening part 5 µm ± 2 µm. The size can be reduced to the level of 6 μm.

As such, reducing the through-hole size can reduce the die size in the wafer, thereby increasing the Net-Die.

In addition, reducing the size of the through-holes may shorten the process time for forming through-silicon vias. That is, the etching time and the time for filling the conductive layer filled in the through hole are reduced, and as the total amount of the conductive layer filled in the through hole is reduced, subsequent through hole protrusion is improved and warpage is reduced. .

In addition, since the bump alignment key is formed in a region other than the net die in the wafer, it is possible to prevent the net die reduction. In addition, the increase in die size, net die reduction, and the influence of transistors around the bump alignment key caused by the formation of the bump alignment key in the die can be prevented in advance.

The present invention is applicable to all related devices that require alignment after backgrinding in a packaging process.

If the alignment key is formed in the dummy die area outside the wafer so as to be used in a subsequent package process when forming the through silicon via as in the present invention, it is possible to effectively control the alignment of the wafer-to-wafer stacking during packaging by stacking a plurality of wafers later. .

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

21 device wafer 22 first insulating layer
26: through silicon via 27: bump alignment key
28: metal pad 29: the first bump
31 carrier wafer 36 second bump

Claims (12)

A wafer through which the through silicon vias and the bump alignment keys pass;
A bump connected to the through silicon via
Semiconductor package comprising a.
The method of claim 1,
The bump alignment key is a semiconductor package formed in the outer region of the wafer.
The method of claim 1,
The bump alignment key is formed in a dummy die region other than the net die of the wafer.
The method of claim 1,
The bump alignment key has a cross shape.
The method of claim 1,
The bump alignment key and the through-silicon via are formed of a metal layer.
The method of claim 1,
The bump,
And a first bump formed on a front surface of the wafer and a second bump formed on a rear surface of the wafer.
Etching the device wafer to a predetermined depth to simultaneously form a through hole and a bump alignment key hole;
Forming a through silicon via embedded in the through hole and a bump alignment key embedded in the bump alignment key hole;
Thinning a back surface of the device wafer to expose the through silicon vias;
Forming an insulating layer having an open portion exposing the through silicon vias; And
Forming a bump embedded in the open part and connected to the through silicon via;
≪ / RTI >
The method of claim 7, wherein
Thinning the back side of the device wafer,
Bonding a carrier wafer to the front side of the device wafer; And
Backgrinding the backside of the device wafer
≪ / RTI >
The method of claim 7, wherein
The bump alignment key hole is formed in the outer region of the device wafer.
The method of claim 7, wherein
The bump alignment key hole is formed in a dummy die region other than the net die of the wafer.
The method of claim 7, wherein
The bump alignment key is a semiconductor package manufacturing method of forming a cross shape.
The method of claim 7, wherein
The bump alignment key and the through-silicon via are formed of a metal.

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