KR20120096627A - Ldpc decoder for mobile wimax - Google Patents

Abstract

PURPOSE: An LDPC(Low Density Parity Check) decoder for a mobile WI-MAX(Worldwide Interoperability for Microwave Access) is provided to reduce the number of clocks which decodes a single layer by eliminating an inserted stall. CONSTITUTION: An LDPC decoder(10) for a mobile Wi-Max includes a first memory(12) which stores a determination variable value and a second memory(11) which stores a check node value. The LDPC decoder includes a parity check matrix storage(131) which stores information about a basic parity check matrix supporting a code rate defined by IEEE(Institute of Electrical and Electronics Engineers) 802.16e standard. The LDPC decoder includes a cycle shift value generation unit(14) which generates a cycle shift value of a parity check matrix about a plurality of action modes according to a block length and a code rate. The LDPC decoder includes a substitution unit(15) which cyclically shifts data decoded according to the parity check matrix about a plurality of action modes. The LDPC decoder includes a decoding function unit(16) which performs decoding calculation.

Description

LDPC decoder for mobile WiMAX {LDPC DECODER FOR MOBILE WiMAX}

The present invention relates to a low density parity check (LDPC) decoder, and more particularly, to an LDPC decoder for mobile WiMAX capable of efficiently decoding an LDPC codeword according to IEEE 802.16e, which is a mobile WiMAX standard. .

In general, Worldwide Interoperability for Microwave Access (WiMAX) is an electronic communication technology that aims to provide data over long distances in a variety of ways, from point-to-point connections to fully portable access. It is based on the IEEE 802.16 standard, also called WirelessMAN. The name "WiMAX" was created in June 2001 by the WiMAX Forum to promote interoperability and compliance of standards. The forum describes WiMAX as "a standards-based technology that enables the delivery of last-mile wireless wide-area access as an alternative to cable and DSL." In particular, IEEE 802.16e, a revised version of IEEE 802.16, is called mobile WiMAX because it supports mobility.

According to the IEEE 802.16e standard of the mobile WiMAX, the LDPC code is designated as an option of the channel coding scheme, and the LDPC code of the IEEE 802.16e is defined by the parity check matrix H having an i × j size.

There is a need in the art for a technology capable of efficiently decoding the LDPC code specified in the IEEE 802.16e standard of the mobile WiMAX.

An object of the present invention is to provide an LDPC decoder for mobile WiMAX capable of efficiently decoding an LDPC code specified by IEEE 802.16e, which is a standard for mobile WiMAX.

As a means for solving the above technical problem, the present invention,

In the LDPC decoder for decoding LDPC coded data according to the IEEE 802.16e standard,

A first memory for storing a decision variable value;

A second memory for storing a test node value;

A parity check matrix storage unit for storing information about a basic parity check matrix supporting a code rate defined in the IEEE 802.16e standard;

A cyclic shift value generator for generating a cyclic shift value of the parity check matrix for a plurality of operation modes according to a block length and a code rate defined by the IEEE 802.16e standard using the basic parity check matrix;

A replacement unit for circularly moving the decoded data according to the parity check matrix for the plurality of operation modes;

A decoding function unit for performing a decoding operation using the decision variable value and the check node value according to the sub-matrix of each of the plurality of layers;

It may include an LDPC decoder for mobile WiMAX.

In one embodiment of the present invention, the second memory includes one bit indicating a sign of a minimum value / minimum value after the update of the effective sub-matrix except for the zero matrix of the layer, and one indicating whether the minimum / min minimum value after the update is performed. And a memory for storing two bits including a bit and a memory for storing a minimum value and a quasi minimum value of a sub-matrix included in the layer.

In one embodiment of the present invention, the parity check matrix storage unit may store the position information and the cyclic shift value of the sub-matrix except the zero matrix in the basic parity check matrix.

In one embodiment of the present invention, the first memory unit and the second memory unit may be a dual port memory in which a read operation and a write operation are simultaneously performed.

In this embodiment, each of the first memory unit and the second memory unit is sequentially performed with the read operation and the write operation delayed in units of layers, and in order to prevent duplication of access of the read operation and the write operation. Can be addressed by rearranging the order of

In this embodiment, corresponding data can be input to the replacement unit instead of the second memory unit for a variable in which a read operation and a write operation are duplicated.

In one embodiment of the present invention, the decoding function unit includes: a subtractor for subtracting and outputting the check node value and the decision variable value; A first number system converter that separates the output of the subtractor into a sign and a magnitude; An XOR logic operator that sequentially multiplies the separated codes by the first number system converter; A minimum value detector configured to sequentially receive the sizes separated by the first number system converter and detect minimum and quasi minimum values; A first-in, first-out memory unit that sequentially stores and outputs the output of the subtractor; A second number system converter that separates an output of the first-in, first-out memory unit into a code and a size; A comparator for comparing the minimum value with the magnitude separated in the second water system transducer; As a result of the comparison of the comparator, if the size separated from the second number system converter is equal to the minimum value, the quasi minimum value is updated and output to the size of a new test node value, and the size and the minimum value separated from the second number system converter are output. If different, mux to update the minimum value to the size of the new test node value; A third number system converter for converting the output of the mux to a magnitude and converting a value of a multiplication result of the XOR logic operation unit as a sign to a two's complement number system; And an addition operation unit configured to add the output of the third numerical system converter and the output of the first-in first-out memory unit to output a new decision variable value.

According to the present invention, the capacity of the test node memory can be significantly reduced.

In addition, according to the present invention, data hazards are frequently generated during memory writing / reading between layers, thereby eliminating stalls that are inserted. Accordingly, the number of clocks decoding one layer can be reduced, thereby improving operation speed. .

According to the present invention, since the base matrix is stored except for the zero matrix included in the parity check matrix, hardware can be minimized.

1 is a diagram illustrating examples of a parity check matrix according to a code rate of IEEE 802.16e.
FIG. 2A is a diagram illustrating an example of a parity check matrix PCM, and b is a variable node and a check node on a Tanner graph according to the parity check matrix of (a). A diagram illustrating a repetitive message transfer process between check nodes.
3 is a diagram illustrating a variable node operation that is equivalent to an iteration code in the decoding process of an LDPC code performed on a Tanner graph.
4 is a diagram illustrating a check node operation equivalent to a single parity check code in the decoding process of an LDPC code performed on a Tanner graph.
5 is a block diagram of an LDPC decoder for mobile WiMAX according to an embodiment of the present invention.
FIG. 6A is a diagram illustrating a memory storing method of test node update values in a conventional LDPC decoder, and (b) is a diagram illustrating a memory storing method of test node update values in an LDPC decoder of the present invention. .
FIG. 7 is a block diagram illustrating a circuit for generating a test node value using code information and minimum / minimum value information stored in the test node memory of the LDPC decoder according to the present invention.
8 is a diagram comparing the capacity of a conventional check node memory and a proposed check node memory for six code rates defined in the IEEE 802.16e standard.
9 is an inter-layer memory addressing timing diagram of an LDPC decoder, (a) shows an example of generating a data hazard, (b) shows a conventional technique using a stall to suppress the data hazard, (c) shows an example of applying the reordering technique according to the present invention.
FIG. 10 is a diagram illustrating a memory reordering and a method of reducing access of a decision variable memory of the LDPC decoder according to the present invention.
11 is a block diagram illustrating a structure of a decoding function unit (DFU) according to the present invention.
12 is a timing chart showing an example of operation timing of a decoding function unit (DFU) operation in the LDPC decoder of the present invention.
FIG. 13 is a circuit diagram showing a specific structure of a water system converter applied to the decoding functional unit shown in FIG.
FIG. 14 is a circuit diagram showing a specific structure of a water system converter applied to the decoding function unit shown in FIG.
FIG. 15 is a circuit diagram showing a specific structure of the minimum detector applied to the decoding functional unit shown in FIG.
FIG. 16A illustrates a conventional parity check matrix storage unit (parity check matrix storage unit (H-ROM)) storage scheme, and (b) illustrates a parity check matrix storage unit (parity check) according to the present invention. A matrix storage unit (H-ROM) storage scheme is shown.
17 is a block diagram illustrating a cyclic shift value generator of a parity check matrix applied to the LDPC decoder of the present invention.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, it should be noted that the shapes, sizes, etc. of the components shown in the drawings may be exaggerated for clarity.

Before describing the specific configuration and operation effects of the present invention, the general technical features of the Low Density Parity Check (LDPC) code and the LDPC decoding algorithm used in the IEEE 802.16e mobile WiMAX standard will be described.

The LDPC code is defined as a parity check matrix (PCM), which is a matrix most of which is filled with zeros and has only one part.

In IEEE 802.16e, a mobile WiMAX standard published in 2005, LDPC codes are designated as an option of channel coding. The LDPC code of IEEE 802.16e is defined by a parity check matrix H of size i × j. Where i represents the block length of the codeword and j represents the length of the parity check bit.

The parity check matrix H may be defined as in Equation 1 below.

[Formula 1]

는

크기의 치환행렬(permutation matrix) 또는 영 행렬(zero matrix)을 나타내며, 이를 부행렬(sub-matrix)이라고 한다. IEEE 802.16e의 패리티 검사 행렬 H는

의 이진 기저행렬(binary base matrix) 로부터 확장될 수 있으며,

이고

이며,

로 고정된 값이다. IEEE 802.16e는 19가지 블록길이와 각각의 블록길이에 대해 6가지 부호율을 지원하도록 규정되어 있어 총 114가지의 동작모드를 갖는다. In Formula 1,

The

A permutation matrix or zero matrix of size is referred to as a sub-matrix. Parity check matrix H of IEEE 802.16e is

Can be extended from the binary base matrix of

ego

Is,

Fixed value IEEE 802.16e is defined to support 19 block lengths and 6 code rates for each block length, and has a total of 114 operation modes.

범위의 값을 갖는다. 따라서 부행렬의 크기는

로 정의된다.Table 1 below shows the parameters of 114 LDPC codes defined in the IEEE 802.16e standard. Where f represents a block length index of the LDPC code,

It has a range of values. Therefore, the size of the submatrix

.

[Table 1]

크기의 단위행렬(identity matrix)을 지정된 값

만큼 오른쪽으로 순환이동(circular right shift)시킨 행렬이다. 블록길이에 따른 오른쪽 순환이동 값

는 하기 식 2와 같이 정의되며, 부호율 2/3A인 경우에만 하기 식 3으로 정의된다. 하기 식 2 및 식 3에서

(통상

로 표시됨)은 영 행렬을 나타낸다. z₀는 최대 부행렬 크기를 나타내며, 블록길이 2304 비트에 대해

의 값을 갖는다. The substitution matrix is

The identity matrix of the specified value

Is a matrix that is circularly right shifted by. Right circular shift value according to block length

Is defined as in Equation 2 below, and is defined in Equation 3 only when the code rate is 2 / 3A. In the following expressions 2 and 3

(Normal

Denotes a zero matrix. z ₀ represents the maximum submatrix size, and for block length 2304 bits

Has the value of.

[Formula 2]

[Equation 3]

은

크기의 단위행렬에 대한 오른쪽 순환이동 값을 나타낸다. 도 1에서

는 패리티 검사 행열의 각 열의 유효한 부행렬의 수를 나타내며,

은 레이어 당 유효 부행렬의 수,

는 PCM 전체의 유효 부행렬의 수를 나타낸다.
1 is a diagram illustrating examples of a parity check matrix according to a code rate of IEEE 802.16e. The parity check matrix (PCM) according to the code rate of IEEE 802.16e is shown in FIG.

silver

Represents a right-hand circular shift value for a unit matrix of size. In Figure 1

Represents the number of valid submatrices of each column of the parity check matrix,

Is the number of valid submatrices per layer,

Represents the number of valid submatrices of the entire PCM.

LDPC  Decryption Algorithm

In the present specification, to define an LDPC decoding algorithm, it is expressed as follows.

: 결정변수

Determinant

: 검사노드

: Inspection node

: 변수노드

Variable node

: 수신된 부호어에 대한 경판정 값

: Hard decision value for received codeword

: 검사노드에서 변수노드로 전달된 정보

: Information passed from check node to variable node

: 변수노드에서 검사노드로 전달된 정보

: Information passed from variable node to check node

: 변수노드

에 연결된 검사노드의 집합

Variable node

Set of check nodes connected to

: 검사노드

를 제외한 집합 변수노드

에 연결된 검사노드의 집합

: Inspection node

Set variable nodes except

Set of check nodes connected to

: 검사노드

에 연결된 변수노드의 집합

: Inspection node

Set of variable nodes connected to

: 변수노드

를 제외한 집합 검사노드

에 연결된 변수노드의 집합

Variable node

Set checking node except

Set of variable nodes connected to

FIG. 2A is a diagram illustrating an example of a parity check matrix PCM, and b is a variable node and a check node on a Tanner graph according to the parity check matrix of (a). A diagram illustrating a repetitive message transfer process between check nodes.

이면, 태너 그래프 상에서 변수노드 i는 검사노드 j와 연결된 것을 나타낸다. 예를 들어, 도 2는

인 LDPC 부호의 패리티 검사 행렬과 태너 그래프를 도시한 것이다.As shown in FIG. 2, the decoding of the LDPC code is performed through an iterative message transfer process between a variable node and a check node on a Tanner graph formed by a parity check matrix. Various decoding methods may exist according to the message transfer process between the nodes. The Tanner graph is a bipartite graph in which the rows and columns of the parity check matrix H of the LDPC code are mapped to the check node and the variable node of the Tanner graph, respectively. The connection between the variable node and the check node is determined by the position of 1 in the parity check matrix. Element of a matrix

, The variable node i on the Tanner graph indicates that it is connected to the check node j. For example, Figure 2

A parity check matrix and a Tanner graph of an LDPC code are shown.

In the decoding process of the LDPC code performed on the Tanner graph, the variable node may be regarded as an iterative code, and the test node may be regarded as a single parity check code.

는 수신된 부호어에 대한 경판정 값으로 변수노드에 입력된다. 또한,

는 해당 검사노드에서 변수노드로 전달된 정보인

를 제외한 변수노드에 전달된 나머지 모든 정보에 대한 함수이다. 왜냐하면,

는 해당 검사노드에서 변수노드로 전달한 정보이기 때문에 검사노드에서는 해당 정보를 이미 알고 있기 때문이다. 그리고 변수노드에서 복호한 추정 비트는 하기 식 4와 같이 표현 할 수 있다.3 is a diagram illustrating a variable node operation that is equivalent to an iteration code in the decoding process of an LDPC code performed on a Tanner graph. As shown in FIG. 3,

Is input to the variable node as a hard decision value for the received codeword. Also,

Is the information passed from the check node to the variable node.

All other information passed to the variable node except for. because,

This is because the check node already knows the information because it is the information passed from the check node to the variable node. The estimated bit decoded in the variable node can be expressed as Equation 4 below.

[Formula 4]

와 해당 변수노드에서 검사노드로 전달된 정보

그리고 검사노드에서 변수노드로 전달된 검사노드들의 모든 정보를 모두 취합(

)하여 복호 비트를 추정한다는 의미이다.Equation 4 is a hard decision value for the received codeword

And information passed from the variable node to the check node

And all the information of test nodes passed from test node to variable node are collected.

To estimate the decoding bit.

Channel coding is a technique for correcting errors by adding redundancy to information when delivering certain information. LDPC corrects an error by adding a parity bit as a block code. The parity check code determines whether the number of 1s in the specific information is odd or even and adds a parity bit to determine whether the information is true or false. If the transmission system uses even parity, the number of 1s present in the information string is counted and transmitted with the parity bit 1 appended to the odd number. The receiving side receives the information, grasps the number of 1s in the information string, compares it with the parity bits, and determines that there is no error in the received information strings when they are the same. If the transmission system uses odd parity, it counts the number of 1s in the information string and if it is even, transmits with the parity bit 1.

This parity check method cannot correct an error if two or more errors occur at the same time. This parity code is called a single parity check code. In the LDPC decoding process performed on the Tanner graph, the check node operation may be regarded as a single parity check code.

4 is a diagram illustrating a check node operation equivalent to a single parity check code in the decoding process of an LDPC code performed on a Tanner graph. Referring to FIG. 4, all the information except for the information transferred from the variable node to the check node is transferred from the check node to the variable node for the same reason as described above. The transfer from the variable node to the check node and the reverse from the check node to the variable node can be repeated and repeated.

The LDPC decoder for mobile WiMAX according to the present invention will be described in detail based on general technical features of the LDPC code and LDPC decoding algorithm used in the IEEE 802.16e mobile WiMAX standard.

5 is a block diagram of an LDPC decoder for mobile WiMAX according to an embodiment of the present invention.

As shown in FIG. 5, the LDPC decoder 10 for mobile WiMAX according to an embodiment of the present invention includes a first memory 12 for storing a decision variable value and a second memory for storing a test node value ( 11), a parity check matrix storage unit 131 for storing information about a basic parity check matrix that supports a code rate defined in the IEEE 802.16e standard, and the basic parity check matrix, using the parity check matrix. A cyclic shift value generation unit 14 for generating a cyclic shift value of the parity check matrix for the plurality of operation modes according to the block length and the code rate defined by the block length and the code rate, and decoded according to the parity check matrix for the plurality of operation modes. And a decoding function unit 16 which performs a decoding operation using the decision variable value and the check node value according to the sub-matrix of each of the plurality of layers. .

In addition, it may include a mux and demux (17 to 19) for selecting or dividing the signal or data output.

가 된다. 또한, QC-LDPC 방식으로 구성된 패리티 검사 행렬의 대부분은 영 (zero) 행렬로 이루어져 있다. 영 행렬은 검사노드와 변수노드 사이에 어떠한 연결도 형성하지 않기 때문에 필요한 연산이 존재하지 않는다. 따라서 LDPC 복호기는 영 행렬을 무시하고 연산을 수행할 수 있다. 본 발명에서 영 행렬을 효율적으로 무시하기 위해 부행렬 단위로 연산을 수행하는 블록-직렬 구조로 설계하여

개의 LLR(Log-Likelihood Ratio)이 동시에 연산되도록 한다. 각각의 DFU는 변수노드 연산과 결정변수 계산을 위한 가산기 2개, 검사노드 연산을 위한 최솟값/준최솟값 검출기 그리고 결정변수 계산을 위해 연산결과를 지연시키는 레지스터로 구성된다. 치환부(Permuter)는 패리티 검사 행렬상의 오른쪽 순환이동 값에 따라 검사노드와 변수노드 사이에 연결을 형성하는 블록이다.
The present invention supports 19 block lengths of the IEEE 802.16e standard and 6 code rates 1/2, 2/3 (A, B), 3/4 (A, B), and 5/6 for each block length. The present invention relates to a multimode LDPC decoder. In the IEEE 802.16e standard, the sub-matrix size of 114 parity check matrices depends on the block length.

. In addition, most of the parity check matrix constructed by the QC-LDPC method consists of a zero matrix. Since the zero matrix does not form any connection between the check node and the variable node, no operation is required. Therefore, the LDPC decoder can ignore the zero matrix and perform the operation. In the present invention, in order to efficiently ignore the zero matrix is designed in a block-serial structure that performs operations in sub-matrix unit

Log-Likelihood Ratio (LLR) is calculated at the same time. Each DFU consists of a variable node operation, two adders for the calculation of the decision variable, a minimum / quasi-minimum detector for the check node operation, and a register that delays the calculation results for the calculation of the decision variable. The permuter is a block that forms a connection between the check node and the variable node according to the right circular shift value on the parity check matrix.

)을 저장하는 결정변수(APP: A Posteriori Probability) 메모리(12)와 검사노드값(

)을 저장하는 검사노드(CN: Check Node) 메모리(11)가 사용된다. 이 두 메모리(11, 12)는 듀얼 포트 메모리로 구현될 수 있다.The memories 11 and 12 store the decision variable values (

) And a test node value (APP) for storing a determinant variable (APP: A Posteriori Probability).

A check node (CN) memory 11 that stores C) is used. The two memories 11 and 12 may be implemented as dual port memories.

The test node memory 11 may store information calculated in the variable node. In the present invention, a method of efficiently reducing the capacity of the test node memory 11 by using the features of the minimum sum algorithm is provided. In addition, the present invention provides a method for reducing access of the decision variable memory 12 through reordering of the parity check matrix H-matrix.

클록 사이클이 필요하지만 읽기와 쓰기가 중첩되므로

클록 사이클로 감소될 수 있다. 그러나 첫 번째 반복복호의 첫 번째 레이어 연산은 정보를 읽어오는 연산만 수행되고 마지막 반복복호의 마지막 레이어 연산은 정보를 쓰는 연산만 수행되기 때문에 읽기와 쓰기를 중첩시키지 못한다. 따라서

개의 레이어를 연산하기 위해서는

클록 사이클이 소요된다. 1개의 레이어 복호를 위해

클록 사이클이 소요되고,

개의 레이어로 이루어진 1회의 반복복호는 총

클록 사이클이 필요하다.
The decoding function unit (DFU) 16 reads the information corresponding to each node from the memory, performs the decoding operation, writes the data back into the memory, and overlaps the read operation and the write operation. The decoding function unit (DFU) 16 writes the decoded information into the memory when the decoding operation is completed, and reads information to be newly decoded from the memory. So in order for the original DFU to decode one layer,

Requires clock cycles, but because reads and writes overlap

Can be reduced in clock cycles. However, the first layer operation of the first iteration decodes only the information-reading operation, and the last layer operation of the last iteration decodes only the information-writing operation. therefore

To compute two layers

It takes a clock cycle. For one layer decoding

Clock cycles,

One iterative decoding of 4 layers

Clock cycles are required.

Inspection node  Memory Reduction Techniques

가 저장된다. 이 때,

의 크기

는 하기 식 5에 의해

의 최솟값으로 갱신되며, 최솟값이 발생한

번째

은 최솟값을 제외한 나머지

의 최솟값으로 갱신된다. 이는

가 다수의 최솟값과 하나의 준최솟값으로 갱신됨을 의미한다.In the check node memory of the LDPC decoder, the result of the calculation in the variable node.

Is stored. At this time,

Size

By the following formula 5

Is updated to the minimum of

th

Is except for the minimum

It is updated to the minimum value of. this is

Is updated with multiple minimums and one quasi minimum.

[Equation 5]

가 갱신되는 예를 든 것이다. 표 2의 (a)는

값중 1이 최솟값이고 2가 준최솟값이 된다. 따라서 1의 위치에는 준최솟값인 2로 갱신되고 나머지

값들은 최솟값인 1로 갱신된다. 표 2의 (b)는

값중 최솟값이 2이며 준최솟값도 2이기 때문에 모두 2로 갱신된다. Table 2 below

Is an example of updating. (A) of Table 2

One of the values is the minimum and 2 is the quasi minimum. Therefore, the position of 1 is updated to the quasi minimum value of 2 and the rest

The values are updated to the minimum value of 1. (B) of Table 2

Since the minimum value is 2 and the quasi minimum value is 2, they are all updated to 2.

[Table 2]

은

의 부호비트들의 곱셈으로 사용되어 양수와 음수를 나타낸다. 따라서

은 최솟값과 준최솟값 그리고 각각의 부호만으로 갱신될 수 있으며, 하기 식 6과 같은 4가지 경우로 정리될 수 있다.Also, in Equation 5

silver

Used to multiply the sign bits of to represent positive and negative numbers. therefore

Can be updated with only the minimum value, the quasi-minimum value, and each sign, and can be summarized into four cases as shown in Equation 6 below.

[Equation 6]

In the present invention, CN memory is divided into two regions, one of which is Check Node Magnitude (CNM) memory, which stores the minimum and quasi minimum values detected for each layer, and the other is a code / Sign / Magtype (SM) memory stores one bit and one sign of minimum / minimum value, and each node can store a value to be updated with a capacity of 2 bits.

Table 3 below is a method of expressing whether the minimum value / quasi-minimum value and the sign bit are 2 bits. If SM is 2 bits, 10 means a minimum value with a negative sign, and 01 means a quasi minimum value with a positive sign.

[Table 3]

-비트의

를 각 레이어의 유효 부행렬의 수

만큼 저장 하므로, 레이어 당

-비트의 메모리 용량이 필요하다.6 is a view comparing a memory storage method of a check node update value in a conventional LDPC decoder with a memory storage method of a check node update value in an LDPC decoder according to the present invention. In the conventional test node memory structure shown in FIG.

-Bit

The number of valid sub-matrix for each layer

As long as you save as per layer

Requires a bit of memory capacity.

의 부호비트인 Sign과

의 최솟값/준최솟값 여부를 표현하는 Mag_type을 2비트로 표현하여 각 레이어별로 0행렬을 제외한 부행렬 개수인

만큼 저장한다. 나머지 하나의 메모리는 CNM 메모리로서, 각 레이어별 부행렬의 개수에 상관없이

의 최솟값과 준최솟값 하나씩만 메모리에 저장한다. 따라서, 본 발명에서 제공하는 메모리 운용 감소 방식은 레이어당

-비트의 메모리 용량만 필요하여 검사노드 메모리를 크게 감소시킬 수 있다.
In contrast, according to the present invention, the test node memory is divided into two regions and stored as shown in FIG. One of these memories is called SM memory

Sign, which is the sign bit of

Mag_type representing whether the minimum or quasi-minimum value of is represented by 2 bits, and the number of sub-matrix except zero matrix for each layer

Save as much. The other memory is CNM memory, regardless of the number of sub-matrix for each layer.

Store only one minimum and one minimum value in memory. Therefore, the memory operation reduction method provided by the present invention is per layer.

Only a bit of memory capacity is required, which greatly reduces the test node memory.

값이 필요하므로, 부호 정보(Sign)와 최솟값/준최소값 여부 정보(Mag_type)로 구성된 신호를

로 변환하기 위한 부가적인 하드웨어가 필요하다. In order to perform the decoding operation of the test node, it is represented by a two's complement number system.

Since a value is required, a signal composed of sign information (Sign) and minimum / minor value information (Mag_type)

Additional hardware is needed to convert

값을 생성하는 회로를 도시한 블록도이다. FIG. 7 illustrates the use of sign information (Sign) and minimum / minimum value information (Mag_type) stored in the SM memory 11 in the check node memory 11 of the LDPC decoder according to the present invention.

A block diagram illustrating a circuit for generating a value.

의 부호비트로 사용되는 값이고, 최솟값/준최소값 여부 정보(Mag_type)는 MUX(211)의 선택신호로 입력되며, 이전 반복복호에서 CNM 메모리(112)에 저장된 최솟값과 준최솟값인

중 한가지를 선택한다. 최솟값/준최소값 여부 정보(Mag_type)가 0이면

은 최솟값이고, 1이면

은 준최솟값이 된다. The circuit shown in FIG. 7 may be included in a decoding function unit (DFU) to be described later. Sign information is converted

Is a value used as a sign bit, and the minimum / min minimum value information (Mag_type) is input as a selection signal of the MUX 211, and the minimum and quasi minimum values stored in the CNM memory 112 in the previous iterative decoding.

Choose one. If minimum / min minimum information (Mag_type) is 0

Is the minimum, and 1

Becomes the quasi minimum.

를 생성시켜 준다.

값 생성 회로는 동시에 갱신되어야 하는 검사노드의 개수(

)만큼 필요하며, 노드를 작은 그룹으로 분할하여 갱신하는 반병렬 구조에서는 메모리 면적에 비해 작은 면적의 하드웨어로 구현될 수 있다. The minimum and quasi-minimum values selected by the MUX 211 are input to the two's complement converter 212 together with the sign information Sign. Together, the two's complement converter 212 receives the sign information (Sign) and the minimum / minor value information (Mag_type) and converts it to the two's complement number system.

Will create

The value generation circuit is the number of check nodes that must be updated at the same time (

In the anti-parallel structure in which nodes are divided into small groups and updated, the hardware can be implemented in a smaller area than the memory area.

비트 폭(

)이 8 비트라면, 종래 방식은

비트의 검사노드 메모리가 필요하다. 이에 반해, 본 발명에 따르면, SM 메모리 용량

비트와 CNM 메모리 용량

비트를 합산한 총 34,560 비트의 검사노드 메모리만 사용될 수 있다. 따라서 29,952 비트가 감소되어 검사노드 메모리의 용량을 46% 감소시킬 수 있다.
For example, a decoder using a PCM with a block length of 2304 and a code rate of 1/2

Bit width (

) Is 8 bits, the conventional way

A bit of checknode memory is required. In contrast, according to the present invention, the SM memory capacity

Bit and CNM memory capacity

Only a total of 34,560 bit test node memories can be used. Therefore, 29,952 bits can be reduced, which can reduce the capacity of the test node memory by 46%.

FIG. 8 compares the capacity of a conventional check node memory and a proposed check node memory for six code rates defined in the IEEE 802.16e standard. Referring to FIG. 8, it can be seen that the capacity of the proposed method is considerably reduced as the code rate is larger. According to the present invention, as the approximate bit width increases, the capacity of the check node memory can be significantly reduced compared to the conventional method.

Parity check matrix Reordering and  Determinant Memory access  Reduction method

The block-serial LDPC decoder stores the decoding operation intermediate results by the decoding function unit (DFU) in the memory and repeatedly reads them. In the present invention, a dual port memory is used to simultaneously perform such memory read / write operations. Memory addressing is important for the decoder's memory read / write operations. Memory addressing is related to the parity check matrix (PCM), which is particularly important at which layer the decoding block is located.

9 is an inter-layer memory addressing timing diagram of an LDPC decoder, (a) shows an example of generating a data hazard, (b) shows a conventional technique using a stall to suppress the data hazard, (c) shows an example of applying the reordering technique according to the present invention.

의 3번 블록과 레이어

의 0번 블록을 읽을 때, 데이터 해저드(data hazard)가 할 수 있다. 복호 기능 유닛(DFU)는 레이어 i의 부행렬을 순차적으로 읽어 복호연산을 거친 후 다시 레이어 i의 부행렬을 읽은 순서대로 메모리에 저장한다. 이 때, 레이어

의 0번 블록을 읽는 동시에 레이어 i의 0번 블록 연산 결과를 메모리에 저장하게 된다. 이 과정에서 레이어 i의 복호된 정보를 메모리에 저장하기 전에 레이어

에서 정보를 읽어 오기 때문에 레이어 i에서 복호된 정보를 반영하지 못하게 되어 데이터 해저드가 발생하게 된다. As shown in Fig. 9A, the layer

Block 3 and Layers

When reading block 0, the data hazard can do it. The decoding function unit (DFU) sequentially reads the sub-matrix of the layer i, performs a decoding operation, and stores the sub-matrix of the layer i in the memory in the order of reading. At this time, the layer

At the same time reading block 0 of block 0, the operation of block 0 of layer i is stored in memory. In the process, before storing the decoded information of layer i in memory,

Since the information is read from, it cannot reflect the decoded information in layer i, resulting in a data hazard.

에서 복호된 정보를 메모리에 저장한 후 메모리에서 레이어

의 정보를 읽어오도록 하는 방법이 적용되었다. 이러한 스톨을 적용하는 방식은, 연접한 레이어 간에 변수노드가 중복되는 경우가 많은 경우, 블록-직렬 방식의 레이어드(layered) 복호에서는 레이어 간의 메모리 쓰기/읽기 과정에서 데이터 해저드가 자주 발생하게 되어 삽입되는 스톨의 수가 증가하여 하나의 레이어를 복호하는 클록 수가 증가하여 동작속도가 느려지는 문제가 발생한다. 본 발명은 이러한 스톨을 적용함으로써 발생하는 문제점을 해소하기 위해, 도 9의 (c)와 같이 패리티 검사 행렬(PCM)의 부행렬 위치를 재정렬(Reordering)하여 스톨을 삽입하지 않고 데이터의 해저드를 방지함으로써 최적의 메모리 어드레싱이 이루어지도록 할 수 있다.In order to prevent such data hazards, a layer is conventionally inserted by inserting a stall as shown in FIG.

Stores the decoded information in memory and stores the layer in memory

The method of reading the information of the was applied. In this case, when the variable nodes are frequently duplicated between contiguous layers, data hazards are frequently inserted during memory writing / reading between layers in block-serial layered decoding. As the number of stalls increases, the number of clocks that decode one layer increases, resulting in a problem that the operation speed becomes slow. In order to solve the problem caused by applying the stall, the present invention reorders the sub-matrix positions of the parity check matrix (PCM) as shown in FIG. 9 (c) to prevent hazards of data without inserting a stall. In this way, optimal memory addressing can be achieved.

,

의 패리티 검사 행렬(PCM)은 도 10의 (a)에 도시된 바와 같이 연접한 두 레이어의 변수노드가 중복되는 경우가 많아 스톨을 삽입하지 않고서 재정열(reordering) 만으로 데이터 해저드를 제거하는데 어려움이 발생할 수 있다. 이에, 본 발명에서는 도 10의 (b) 및 (c)에 도시한 바와 같은 방식을 제공한다. 도 10의 (a)에 도시된 것과 같은 패리티 검사 행열을 재정열하여 도 10의 (b)에 도시한 것과 같이 읽기/쓰기 동작이 동시에 일어나게 하고, 메모리의 동일 주소에 억세스(access) 할 경우 도 10의 (c)와 같이 메모리를 거치지 않고, 치환부(permuter)(15)로 데이터를 입력하는 기법을 사용할 수 있다.Code rate defined in the 802.16e standard

,

As shown in FIG. 10A, the parity check matrix PCM of the parity check matrix (PCM) has difficulty in removing the data hazard only by reordering without inserting a stall because the variable nodes of two contiguous layers overlap each other. May occur. Thus, the present invention provides a scheme as shown in (b) and (c) of FIG. When the parity check matrix as shown in FIG. 10 (a) is rearranged so that a read / write operation occurs simultaneously as shown in FIG. 10 (b), and the same address of the memory is accessed. As shown in (c) of FIG. 10, a technique of inputting data into the permuter 15 without passing through the memory may be used.

는 패리티 검사 행렬(PCM)의 유효 블록의 수이다. 부호화율

,

의 경우에, 종래 방식(336회)에 비해 메모리 억세스 횟수가 약 52%(172회) 감소하였으며, 와이맥스 표준(IEEE 802.16e)의 6가지 부호화율 전체에 대해 모두 고려하였을 경우 기존방식(2×(76+80+81+75+88+80)=960)에 비해 본 발명에 따른 방식(2×(76+80+81+75)+92+72=788)이 메모리 억세스 횟수가 약 18% 감소하였음을 알 수 있다. Table 4 below compares the number of memory accesses between the conventional method and the method of the present invention. In Table 4

Is the number of valid blocks of the parity check matrix (PCM). Coding rate

,

In the case of, the number of memory accesses is reduced by about 52% (172 times) compared to the conventional method (336 times), and when all the six coding rates of the WiMAX standard (IEEE 802.16e) are considered, the conventional method (2 × Compared to (76 + 80 + 81 + 75 + 88 + 80) = 960, the method according to the present invention (2 × (76 + 80 + 81 + 75) + 92 + 72 = 788) has about 18% of the number of memory accesses. It can be seen that the decrease.

[Table 4]

,

)
(802.16e WiMAX, Block-length: 2304, Code-rate:

,

)

Decoding function unit Decoding Function Unit : DFU ) rescue

The decoding function unit (DFU) collects Log-Likelihood Ratios (LLRs) of codewords except for itself to correct an error of an input codeword including an error and predicts the LLR closest to the original codeword. In the present invention, a decoding function unit (DFU) having a layered structure based on a minimum sum algorithm is applied.

11 is a block diagram showing the structure of a decoding functional unit according to the present invention. As shown in FIG. 11, the decoding function unit (DFU) includes a check node value (CNV) block, a minimum detector, a sign bit accumulator, and a FIFO (First-In First-First) for generating minimum and sub minimum values. Out) It consists of memory, adder, subtractor, comparator and number system (two's complement / sign-size) converter. Inside the decoding function unit (DFU), the LLRs are approximated with constant bits and computed separately from the sign and size.

와 결정변수

는 뺄셈연산을 통해 변수노드값

를 계산한다. 계산된

는 수체계 변환기(TC_SM1)를 통해 부호와 크기로 분리되어 부호는 순차적으로 입력되어 곱셈한다. 또한 분리된 변수노드 크기

는 최솟값 검출기(Min_det)를 통해 순차적으로 입력되는 분리된

들과 비교하여 최솟값과 준최솟값을 검출하여 레지스터에 저장한다. 한편, 순차적으로 계산된

는 선입선출 메모리부(FIFO)에 누적되어

만큼 지연된 후 수체계 변환기(TC_SM2)를 통해 부호와 크기로 분리된다. 분리된

는 비교기를 통해 검출된 최솟값 min0과 비교되어 두 값이 같으면 준최솟값 min1을 새로운 검사노드 크기

로 갱신하고, 다르면 최솟값 min0이

로 갱신된다. 왜냐하면, 상기 식 5에 따르면

번째

를 결정할 때에는 i번째

를 제외한 나머지 변수노드 크기의 집합

중 가장 작은

을 선택하기 때문에 검사노드 i를 구성하는 변수노드의 집합

중 가장 작은

가 발생한 위치에는 준최솟값이 갱신되고 변수 노드 i를 제외한 검사노드 i를 구성하는 나머지 변수노드의 집합

에는 최솟값으로 갱신되기 때문이다. 또한 부호의 누적 곱셈도 동일한 원리로 모든 부호를 누적 곱셈한 다음 i번째

의 부호를 한 번 더 누적 곱셈하여 갱신한다. 부호의 누적 곱셈은 XOR 연산으로 이루어진다. 결정된

의 크기와 부호는 2의 보수 수체계 변환을 통해 새로운 검사노드값

로 갱신된다. 갱신된 검사노드값

과 FIFO에 의해 지연된

는 덧셈연산을 통해 새로운 결정변수값

로 갱신된다. 한편 누적곱셈을 통해 얻어진 검사노드값의 부호 1비트와 비교기를 통해 얻은 mag_type 1비트는 2비트로 변환되어 SM 메모리, 최솟값 검출기를 통해 얻어진 최솟값과 준최솟값은 CNM 메모리에 저장된다. Converted Check Node Value

And determinants

Subtracts variable node values with subtraction

. Calculated

Is divided into a sign and a size by the number system converter TC_SM1, and the signs are sequentially input and multiplied. Also separate variable node size

Is separated sequentially input through the minimum detector Min_det.

The minimum and quasi-minimum values are detected and stored in registers. Meanwhile, sequentially calculated

Accumulates in the first-in, first-out (FIFO)

After the delay, it is separated into code and size through the number system converter TC_SM2. Separated

Is compared with the minimum value min0 detected by the comparator.

If it is different, the minimum value min0 is

Is updated to Because, according to Equation 5

th

I is determined when

Set of variable node sizes except for

Smallest of

Set of variable nodes constituting test node i

Smallest of

Where the quasi-minimum value is updated and the remaining set of variable nodes constituting check node i except variable node i

This is because it is updated to the minimum value. In addition, the cumulative multiplication of the signs is performed on the same principle as the cumulative multiplication of all signs.

The sign of is updated by cumulative multiplication once more. Cumulative multiplication of the sign consists of an XOR operation. determined

The magnitude and sign of are the new test node values through the conversion of two's complement number system.

Is updated to Updated Check Node Value

And delayed by FIFO

Is the new decision variable value through the addition operation.

Is updated to Meanwhile, one sign of the check node value obtained through cumulative multiplication and one bit of mag_type obtained through the comparator are converted into two bits, and the minimum and quasi minimum values obtained through the SM memory and the minimum value detector are stored in the CNM memory.

와

를 읽어오는 과정이며, 쓰기동작은 연산된

와

를 메모리에 쓰는 과정이다. 읽기동작과 쓰기동작은 최초 1회를 제외하고는 항상 중첩되어 일어난다. i번째 레이어의 쓰기동작은 (i-1)번째 레이어의 읽기 동작과 동시에 일어난다. (i-1)번째 레이어의 읽기동작은 새로운 최솟값/준최솟값을 검출하고 부호 누적곱셈 또한 새롭게 시작하기 때문에 i번째 레이어의 검출 결과를 메모리에 쓰기 위해서는 값을 보전할 필요가 있다. 프로세스 과정은 읽기동작 동안 결정된 부호 누적곱셈과 최솟값/준최솟값 검출의 결과를 결과값 레지스터로 저장하는 과정이다.
12 is a timing chart showing an example of operation timing of a decoding function unit (DFU) operation in the LDPC decoder of the present invention. The operation of the decoding function unit (DFU) consists of a read operation, a write operation, and a process. Read operation from memory

Wow

It is a process of reading and writing operation is calculated

Wow

Is the process of writing to memory. Read and write operations always overlap except for the first time. The write operation of the i-th layer occurs simultaneously with the read operation of the (i-1) th layer. Since the read operation of the (i-1) th layer detects a new minimum / quasi-minimum value and also starts a new sign cumulative multiplication, it is necessary to preserve the value in order to write the detection result of the i-th layer to memory. The process involves storing the result of the sign cumulative multiplication and the minimum / quasi-minimum detection determined during the read operation into the result register.

FIG. 13 is a circuit diagram showing a specific structure of a water system converter applied to the decoding functional unit shown in FIG. In particular, the number system converter illustrated in FIG. 13 is a block that separates the value a of the two's complement number system into a sign bit and a size, and may be designed using Equation 7 below.

[Equation 7]

The number system converter TC_SM shown in FIG. 13 determines whether the number of input two's complement number systems is positive or negative, and if it is positive, the sign is 0 and the magnitude outputs the input two's complement as it is. If the input number is negative, the sign becomes 1, and the complement of the input 2 is inverted as shown in Equation 7 and 1 is added to calculate the magnitude value. Table 5 below shows the operation of the water system converter (TC_SM converter) shown in FIG.

[Table 5]

FIG. 14 is a circuit diagram showing a specific structure of a water system converter applied to the decoding function unit shown in FIG. In particular, the converter SM_TC shown in FIG. 14 is a block that receives a code and a size and converts it into a two's complement number system, which can be designed using Equation 8.

[Equation 8]

The number system converter (SM_TC converter) shown in FIG. 14 determines whether the input code is positive or negative. If the sign is positive, the MSB of the two's complement number system becomes 0 and the size is the same as the input 7-bit size. Will print. If the input code is negative, the MSB of the two's complement number system is 1, and the input size is inverted as shown in Equation 8, and converted by adding 1. Table 6 below shows the operation of the water system converter SM_TC converter shown in FIG.

TABLE 6

FIG. 15 is a circuit diagram showing a specific structure of the minimum detector applied to the decoding functional unit shown in FIG.

As shown in FIG. 15, the minimum detector is a block that detects the smallest minimum value and the second smallest minimum value by comparing unsigned values sequentially input. The minimum detector may comprise two comparators, registers min0 and min1 storing the detected minimum / quasi-minimum values and a MUX controlling the detector. The two comparators generate the signals en_m0 and en_m1 by comparing the values input to the detector with the values of the registers storing the minimum and quasi-minimum values, respectively. The signals en_m0 and en_m1 are signals for activating the input of the registers storing the minimum and quasi-minimum values, respectively. The designed minimum detector controls the MUX to determine whether the newly updated value is minimum or quasi-minimum. Table 7 below summarizes the operation of the minimum detector.

[Table 7]

If the input value x is larger than the minimum and quasi-minimum values, en_m0 and en_m1 are 0 and 0, respectively, and the values of the registers m0 and m1 do not change. If x is greater than the minimum and less than the quasi minimum, the en_m1 signal becomes 1, activating the min1 register and updating the min1 register via MUX. If x is less than both the minimum and quasi-minimum values, both the en_m0 and en_m1 signals are 1, the value of the min0 register is updated to min1 via MUX, and x is updated to min0. In other words, when a new minimum value is input, the existing minimum value becomes the quasi-minimum value and the new x becomes the minimum value.

를 생성시켜 주는 블록이다. 이 CNV 블록은 MUX와 2의 보수 수체계 변환기로 이루어져 있다. MUX는 SM 메모리로부터 최솟값 유무를 판단하는 Mag_type 1비트를 받아 0이면 CNM 메모리에서 최솟값을, 1이면 준최솟값을 선택하게 된다. 2의 보수 수체계 변환기는 MUX에서 검사노드 크기

를 SM 메모리를 통해 검사노드값

의 부호를 받아 검사노드값

으로 변환한다.
On the other hand, the CNV (Check Node Value) block for generating the minimum and quasi-minimum value of FIG. 11 is a check node value as described with reference to FIG.

This block creates. This CNV block consists of a MUX and a two's complement number converter. The MUX receives 1 Mag_type bit to determine the minimum value from the SM memory, and if 0, the minimum value is selected from the CNM memory, and if the value is 1, the quasi-minimum value is selected. 2, complement number system converter checks node size in MUX

Node value through SM memory

Check node value

Convert to

Parity check matrix storage (parity check matrix storage (H-) ROM ))

)이 12, 8, 6, 4로 구성되며, 레이어 당 24개의 부행렬을 가지고 있다. 부행렬 하나의 크기는 블록길이에 따라

(단,

)가 된다. 패리티 검사 행렬(PCM)을 구성하는 부행렬들은 다수가 영(0) 행렬로 이루어져 있다. 예를 들어,

인 경우는 212개의 영행렬이 포함되어 있고,

인 경우는 16개의 영 행렬이 포함되어 있다. 하드웨어 구현시 영행렬은 복호결과에 아무런 영향을 미치지 않기 때문에 영행렬을 제외시킨다면 동작속도를 빠르게 할 수 있으며 패리티 검사 행렬 저장부(H-ROM)의 용량을 줄일 수 있다. 따라서 본 발명에서는 부호율에 따른 6개의 기본 패리티 검사 행렬(PCM)의 정보를 저장하는 대신에, 영 행렬을 제외한 부행렬들의 위치 정보와 순환이동 값만을 패리티 검사 행렬 저장부(패리티 검사 행렬 저장부(H-ROM))에 저장한다. The parity check matrix storage unit (parity check matrix storage unit (H-ROM)) is a memory that stores a parity check matrix (PCM) value used for LDPC decoding. In the IEEE 802.16e standard, a basic parity check matrix (PCM) supporting six code rates (R = 1/2, 2/3 (A, B), 3/4 (A, B), 5/6) is described above. As defined in FIG. 1. In order to support all 19 block lengths, an effective cyclic shift value for each block length should be calculated and used using a basic parity check matrix (PCM) according to a code rate and Equations 2 and 3 above. The parity check matrix (PCM), defined in the IEEE 802.16e standard, depends on the number of layers

) Consists of 12, 8, 6, and 4, with 24 submatrices per layer. The size of one submatrix depends on the block length

(only,

) The sub-matrixes of the parity check matrix (PCM) are composed of a zero matrix. E.g,

Is 212 zero matrices,

In the case of, 16 zero matrices are included. In the hardware implementation, since the zero matrix has no effect on the decoding result, excluding the zero matrix can speed up the operation and reduce the capacity of the parity check matrix storage unit (H-ROM). Therefore, in the present invention, instead of storing the information of the six basic parity check matrix (PCM) according to the code rate, the parity check matrix storage unit (parity check matrix storage unit) only the position information and the cyclic shift value of the sub-matrix except the zero matrix (H-ROM)).

FIG. 16A illustrates a conventional parity check matrix storage unit (parity check matrix storage unit (H-ROM)) storage scheme, and (b) illustrates a parity check matrix storage unit (parity check) according to the present invention. A matrix storage unit (H-ROM) storage scheme is shown.

을 할당하였다. 부호율이 1/2인 경우 모든 블록길이는 각 레이어마다 영행렬을 제외한 부행렬의 개수는 6?7개이므로 부행렬의 개수를 7개로 할당하였으며, 총

개의 부행렬을 순환이동 값과 부행렬 위치로 식별하도록 한다.
As shown in FIG. 16, in the present invention, the parity check matrix is adapted to a layer having the most sub-matrix except for the zero matrix.

Was assigned. If the code rate is 1/2, the number of sub-matrixes is assigned to 7 because all block lengths are 6-7, except for zero, for each layer.

Identifies the two sub-matrix by the circular shift value and the sub-matrix position.

Circular movement value  Generation unit ( SVG : Shifting Value Generator )

The cyclic shift value generation unit (SVG) uses the basic matrix for six code rates defined in the IEEE 802.16e standard to apply valid cyclic shift values of the basic matrix to the 114 operating modes. Is a block that generates a cyclic shift value of a parity check matrix (PCM) that supports each operation mode. 17 is a block diagram illustrating a cyclic shift value generator applied to the LDPC decoder of the present invention.

결과를 12비트로 양자화하여 룩업테이블(LUT)로 저장한 후 패리티 검사 행렬 저장부(패리티 검사 행렬 저장부(H-ROM))에 저장된 부호율에 따른 기본행렬의 순환이동 값을 사용하여 곱셈 연산을 수행한다.

값은 소수점 이하 12비트로 양자화 한 값이다. 12비트로 양자화 된 값은

의 값과 약간의 오차가 발생하게 되며, 이를 보상하기 위한 회로가 필요하다. Tmul 블록은

값을 소수점 이하 12비트로 양자화 한 값과 기본 행렬의 값을 곱하여 19비트의 결과 값 중 상위 7비트 값에 소수점 이하 6비트의 값이 ‘111111’인 경우 정수부에 1을 보상하는 회로이다. 상기 식 3은 부호율이 2/3A인 경우에만 사용된다. 2/3A의 기본행렬의 유효한 순환이동의 값은 48 미만이므로,

가 48 이상인 경우에는 기본 행렬을 그대로 사용하고, 44이하인 경우

를 사용해 나머지 연산을 한다.

가 가장 작은 경우는 24이기 때문에 48 미만의 기본 행렬의 순환이동 값을

로 한 번 뺀 값이 실제 나머지 연산의 결과와 동일하다. 따라서 본 발명에서는 도 17에 도시된 바와 같이

가 48이상인 경우는 패리티 검사 행렬 저장부(패리티 검사 행렬 저장부(H-ROM))의 데이터를 R_2_3A_en 신호를 사용하여 바이패스(bypass) 시키고, 그 외의 경우는 Sub 블록 내의 비교기에서

보다 값이 클 경우만 기본행렬의 순환이동 값에서

를 감산한다.
In Equation 2, when the division operation is implemented in hardware, the result value cannot be obtained every clock. Therefore, in the present invention,

Quantize the result into 12 bits and store it as a lookup table (LUT), and then perform multiplication operation using the cyclic shift value of the base matrix according to the code rate stored in the parity check matrix storage unit (parity check matrix storage unit (H-ROM)). To perform.

The value is quantized to 12 bits after the decimal point. The value quantized to 12 bits is

There is a slight error with the value of, and a circuit is needed to compensate for this. Tmul block

It is a circuit that compensates 1 in the integer part when multiplying the value by 12 bits below the decimal point and the value of the base matrix by multiplying the value of the base matrix by the upper 7 bits among the result values of 19 bits. Equation 3 is used only when the code rate is 2 / 3A. Since the effective circular shift value of the 2 / 3A base matrix is less than 48,

Is greater than or equal to 48, the default matrix is used and less than or equal to 44

To do the rest.

Is the smallest value of 24, so the circular shift of the underlying matrix less than 48

The value subtracted once is the same as the result of the remaining operation. Therefore, in the present invention, as shown in FIG.

Is greater than or equal to 48, the data of the parity check matrix storage (parity check matrix storage (H-ROM)) is bypassed using the R_2_3A_en signal.

Only when the value is greater than

Subtract

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the following claims and their equivalents.

11: Test node memory (first memory) 12: APP memory (first memory)
13: control unit 131: parity check matrix storage unit
14: cyclic shift value generation unit 15: substitution unit
16: decoding function unit

Claims (7)

In the LDPC decoder for decoding LDPC coded data according to the IEEE 802.16e standard,
A first memory for storing a decision variable value;
A second memory for storing a test node value;
A parity check matrix storage unit for storing information about a basic parity check matrix supporting a code rate defined in the IEEE 802.16e standard;
A cyclic shift value generator for generating a cyclic shift value of the parity check matrix for a plurality of operation modes according to a block length and a code rate defined by the IEEE 802.16e standard using the basic parity check matrix;
A replacement unit for circularly moving the decoded data according to the parity check matrix for the plurality of operation modes; And
Decoding function unit for performing a decoding operation using the decision variable value and the check node value according to the sub-matrix of each of the plurality of layers
LDPC decoder for mobile WiMAX comprising a.
The method of claim 1, wherein the second memory,
A memory for storing two bits including one bit indicating a sign of a minimum value / minimum value after the update of the effective sub-matrix except the zero matrix of the layer and one bit indicating whether the minimum value / sub-minimum value after the update is performed; An LDPC decoder for mobile WiMAX, comprising a memory for storing the minimum and quasi minimum values of sub-matrix included in the layer.
The method of claim 1, wherein the parity check matrix storage unit,
And the position information and the cyclic shift value of the sub-matrix except for the zero matrix in the basic parity check matrix.
The memory device of claim 1, wherein the first memory unit and the second memory unit include:
The LDPC decoder for mobile WiMAX, characterized in that the dual port memory that read and write operations are performed at the same time.
The memory device of claim 4, wherein the first memory unit and the second memory unit include:
The read and write operations are sequentially delayed in units of layers, and are sequentially addressed by reordering the sub-matrix in layers in order to prevent duplication of access of the read and write operations. .
The method of claim 4, wherein
The LDPC decoder for mobile WiMAX, characterized in that the data corresponding to the read operation and the write operation are input to the replacement unit instead of the second memory unit.
The method of claim 1, wherein the decoding function unit,
A subtractor for subtracting and outputting the check node value and the decision variable value;
A first number system converter that separates the output of the subtractor into a sign and a magnitude;
An XOR logic operator that sequentially multiplies the separated codes by the first number system converter;
A minimum value detector configured to sequentially receive the sizes separated by the first number system converter and detect minimum and quasi minimum values;
A first-in, first-out memory unit that sequentially stores and outputs the output of the subtractor;
A second number system converter that separates an output of the first-in, first-out memory unit into a code and a size;
A comparator for comparing the minimum value with the magnitude separated in the second water system transducer;
As a result of the comparison of the comparator, if the size separated from the second number system converter is equal to the minimum value, the quasi minimum value is updated and output to the size of a new test node value, and the size and the minimum value separated from the second number system converter are output. If different, mux to update the minimum value to the size of the new test node value;
A third number system converter for converting the output of the mux to a magnitude and converting a value of a multiplication result of the XOR logic operation unit as a sign to a two's complement number system; And
And an addition operation unit configured to add the output of the third number system converter and the output of the first-in first-out memory unit to output a new decision variable value.

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