KR20120096606A - X-ray detector panel and method for manufacturing the panel - Google Patents

X-ray detector panel and method for manufacturing the panel Download PDF

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KR20120096606A
KR20120096606A KR1020110015780A KR20110015780A KR20120096606A KR 20120096606 A KR20120096606 A KR 20120096606A KR 1020110015780 A KR1020110015780 A KR 1020110015780A KR 20110015780 A KR20110015780 A KR 20110015780A KR 20120096606 A KR20120096606 A KR 20120096606A
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electrode
layer
contact hole
data
gate
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KR1020110015780A
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Korean (ko)
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추대호
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(주)세현
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/085—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors the device being sensitive to very short wavelength, e.g. X-ray, Gamma-rays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/115—Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

An X-ray detector panel capable of improving a fill factor may include a base substrate, a gate wiring formed on the base substrate, a gate insulating layer covering the gate wiring, a thin film transistor connected to the gate wiring, a first protective layer covering the thin film transistor, An optical sensor unit formed in the first protective layer, a second protective layer covering the optical sensor unit, a data wiring formed in the second protective layer and a bias wiring spaced apart from the data wiring. In this case, the optical sensor unit is formed to overlap a part of the thin film transistor in a unit region formed by the gate wiring and the data wiring. As such, as the optical sensor part is formed to overlap with a portion of the thin film transistor, the filter may be further extended in the unit region to further improve the filter.

Description

X-ray detector panel and its manufacturing method {X-RAY DETECTOR PANEL AND METHOD FOR MANUFACTURING THE PANEL}

The present invention relates to an x-ray detector panel and a method for manufacturing the same, and more particularly, to an x-ray detector panel and a method for manufacturing the same that can detect the X-rays and to photograph the inside of the object.

In general, X-rays have a short wavelength and can easily penetrate an object. The amount of X-rays transmitted is determined by the degree of compactness inside the object. That is, the internal state of the object may be indirectly observed through the transmission amount of the X-ray that has passed through the object.

The X-ray detector panel is a device for detecting the amount of transmission of the X-rays transmitted through the object. The X-ray detector panel detects the amount of transmission of the X-ray, and displays the internal state of the object to the outside through a display device. The X-ray detector may generally be used as a medical inspection device, a non-destructive inspection device, and the like.

The X-ray detector panel generally includes a PIN diode that directly or indirectly senses the intensity of an X-ray applied from the outside, a thin film transistor electrically connected to the P-side electrode of the PIN diode, a gate wiring and data electrically connected to the thin film transistor. Wiring, and a bias wiring for applying a bias voltage to the N-side electrode of the PIN diode.

However, as the PIN diode is planarly spaced apart from the data wiring and the gate wiring so as not to overlap the thin film transistor, and the bias wiring is formed on the PIN diode to cover a portion of the PIN diode. The area of the PIN diode capable of sensing x-rays is reduced. That is, a fill factor, which is a ratio of an area capable of sensing X-rays in a unit pixel area, is deteriorated.

Accordingly, an object of the present invention is to solve such a problem, and an object of the present invention is to provide an X-ray detector panel capable of improving a fill factor by increasing an area capable of sensing X-rays.

The X-ray detector panel according to the exemplary embodiment of the present invention includes a base substrate, a gate wiring, a gate insulating layer, a thin film transistor, a first protective layer, an optical sensor unit, a second protective layer, a data wiring, and a bias wiring.

The gate wiring is formed on the base substrate in a first direction, and the gate insulating layer is formed on the base substrate to cover the gate wiring. The thin film transistor may include a gate electrode branched from the gate wiring, an active pattern formed on the gate insulating layer to overlap the gate electrode, a source electrode formed on the active pattern and extending to one side, and formed on the gate insulating layer; And a drain electrode formed on the active pattern to be spaced apart from the source electrode and extending to the other side and formed on the gate insulating layer. The first passivation layer is formed on the gate insulating layer to cover the thin film transistor, and has a drain contact hole exposing a portion of the drain electrode and a first data contact hole exposing a portion of the source electrode. The optical sensor unit is formed on the first protective layer and electrically connected to the drain electrode through the drain contact hole, a PIN diode formed on the lower electrode, and a transparent conductive material formed on the PIN diode. It comprises a top electrode made up. The second passivation layer is formed on the first passivation layer to cover the photosensor, and has a bias contact hole exposing a portion of the upper electrode and a second data contact hole exposing the first data contact hole. . The data line is formed in a second direction crossing the first direction on the second passivation layer, and is electrically connected to the source electrode through the second data contact hole and the first data contact hole. The bias line is formed in the second direction on the second protective layer to be spaced apart from the data line, and is electrically connected to the upper electrode through the bias contact hole. The optical sensor unit is formed to overlap a portion of the thin film transistor in a unit region formed by the gate line and the data line.

The optical sensor unit may be formed so as not to overlap a channel unit formed between the source electrode and the drain electrode of the active pattern. In this case, the bias wire may be formed to cover the channel portion. The lower electrode, the PIN diode, and the upper electrode may be stacked to have the same shape.

The X-ray detector panel may further include a third passivation layer formed on the second passivation layer to cover the data line and the bias line. In this case, all of the first, second and third protective layers may be inorganic insulating layers.

The data line may include a data main line and a data connection part. The data main wiring is formed in the second direction, and the data connection part is branched from the data main wiring so as to overlap with a portion of the source electrode, and the source is connected to the source through the first and second data contact holes. Is electrically connected to the electrode.

In the method of manufacturing an X-ray detector panel according to an embodiment of the present invention, first, a gate wiring extending in a first direction and a gate electrode branched from the gate wiring are formed on a base substrate, and the gate wiring and the gate electrode are formed. A gate insulating layer is formed on the base substrate to cover. Subsequently, an active pattern is formed on the gate insulating layer to overlap the gate electrode, and then a source electrode formed on the active pattern and extending to one side on the gate insulating layer and spaced apart from the source electrode. A drain electrode formed on the active pattern and extending to the other side is formed. Subsequently, a drain contact hole covering the source electrode, the drain electrode, and the active pattern and exposing a portion of the drain electrode and a first data contact hole exposing a portion of the source electrode are formed on the gate insulating layer. The first protective layer having is formed. Thereafter, an upper electrode including a lower electrode disposed on the first protective layer and electrically connected to the drain electrode through the drain contact hole, a PIN diode disposed on the lower electrode, and a transparent conductive material disposed on the PIN diode. An optical sensor portion having an electrode is formed. Subsequently, a second passivation layer is formed on the first passivation layer, the second passivation layer covering the upper electrode and having a bias contact hole exposing a portion of the upper electrode and a second data contact hole exposing the first data contact hole. do. Then, on the second passivation layer, a data line extending in a second direction crossing the first direction and electrically connected to the source electrode through the first and second data contact holes, and spaced apart from the data line. And a bias line extending in the second direction and electrically connected to the upper electrode through the bias contact hole. In this case, the optical sensor unit is formed in the unit region formed by the gate wiring and the data wiring so as not to overlap the channel portion formed between the source electrode and the drain electrode of the active pattern.

The optical sensor unit may be formed by first forming a lower metal layer on the first protective layer, a PIN semiconductor layer on the lower metal layer, and an upper conductive layer formed of a transparent metal material on the PIN semiconductor layer. The upper layer, the PIN diode, and the lower electrode may be formed by patterning the conductive layer, the PIN semiconductor layer, and the lower metal layer at a time through one mask.

As described above, according to the X-ray detector panel and a method of manufacturing the same, the optical sensor part is formed to be extended to the maximum so as not to overlap with the channel part formed between the source electrode and the drain electrode of the active pattern in the unit area formed by the gate wiring and the data wiring. Accordingly, the effector of the photosensor part can be further improved.

1 is a plan view illustrating an X-ray detector panel according to an exemplary embodiment of the present invention.
2 is a cross-sectional view taken along the line I-I 'of FIG.
3 is a cross-sectional view taken along the line II-II 'of FIG. 2.
4 is a cross-sectional view illustrating a manufacturing process up to a first passivation layer during the manufacturing process of the X-ray detector panel of FIG. 1.
5 is a cross-sectional view for describing a step of forming a lower metal layer after the manufacturing process of FIG. 4.
FIG. 6 is a cross-sectional view illustrating a process of forming a PIN semiconductor layer and an upper conductive layer after the manufacturing process of FIG. 5.
FIG. 7 is a cross-sectional view illustrating a step of forming an optical sensor unit after the manufacturing process of FIG. 6.
8 is a cross-sectional view illustrating a step of forming a second protective layer, a data line, and a bias line after the manufacturing process of FIG. 7.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text.

It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, actions, components, parts or combinations thereof.

In the drawings, the thickness of each device or film (layer) and regions has been exaggerated for clarity of the invention, and each device may have a variety of additional devices not described herein. When (layer) is mentioned as being located on another film (layer) or substrate, an additional film (layer) may be formed directly on or between the other film (layer) or substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

1 is a plan view illustrating an X-ray detector panel according to an exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1, and FIG. 3 is a line II-II ′ of FIG. 2. It is a cross section which cut along.

1, 2, and 3, the X-ray detector panel according to the present exemplary embodiment includes a base substrate 100, a gate wiring GL, a gate insulating layer 110, a thin film transistor TFT, and a first protective layer. 120, an optical sensor unit, a second passivation layer 160, a data line DL, a bias line BL, a third passivation layer 180, and an organic insulating layer 190.

The base substrate 100 has a plate shape and may be made of a transparent material, for example, glass, quartz, synthetic resin, or the like. The gate line GL is formed on the base substrate 100 in a first direction D1. The gate insulating layer 110 is formed on the base substrate 100 to cover the gate line GL.

The thin film transistor TFT includes a gate electrode 10, an active pattern 20, a source electrode 30, and a drain electrode 40. The gate electrode 10 is formed on the base substrate 100, covered by the gate insulating layer 110, and branched from the gate wiring GL. The active pattern 20 is formed on the gate insulating layer 110 to overlap the gate electrode 10, and includes a channel pattern in which a channel can be formed and an ohmic contact pattern formed on the channel pattern. For example, the channel pattern is an amorphous silicon pattern having a thickness of about 2200 GPa, and the ohmic contact pattern is an ion doped amorphous silicon pattern having a thickness of about 500 GPa. The source electrode 30 is formed on the active pattern 20 and extends to one side to be formed on the gate insulating layer 110. The drain electrode 40 is formed on the active pattern 20 so as to be spaced apart from the source electrode 30, and extends to the other side, and is formed on the gate insulating layer 110. On the other hand, the ohmic contact pattern is formed between the channel pattern and the source electrode 30, and between the channel pattern and the drain electrode 40, respectively.

In the present exemplary embodiment, a portion of the channel pattern of the active pattern 20 corresponding to between the source electrode 30 and the drain electrode 40 has a gate signal through the gate line GL and the gate electrode 10. ), Where a channel is actually formed between the source electrode 30 and the drain electrode 40 to generate a flow of charge, which is later referred to as a channel portion CH. That is, the channel portion CH is a minimum region that should not be influenced from the outside in the operation of the thin film transistor TFT.

The first passivation layer 120 is formed on the gate insulating layer 110 to cover the thin film transistor TFT, and exposes a portion of the drain electrode 40 to the first passivation layer 120. A first data contact hole 124 is formed to expose the drain contact hole 122 and a portion of the source electrode 30. The first protective layer 120 may be an inorganic insulating layer, and may be, for example, a silicon nitride (SiNx) layer having a thickness of about 1000 GPa.

The photo sensor unit SR is formed on the first passivation layer 120 and is electrically connected to the drain electrode 40 through the drain contact hole 122 and the lower electrode LP. PIN diode (DI) is formed on the () to convert the light applied from the outside into electricity, and the upper electrode (HP) formed on the PIN diode (DI) and made of a transparent conductive material. In this case, the PIN diode DI includes a P-type semiconductor part formed on the lower electrode LP, an I-type semiconductor part formed on the P-type semiconductor part, and an N-type semiconductor part formed on the I-type semiconductor part. .

The lower electrode LP, the PIN diode DI, and the upper electrode HP may be stacked to have the same shape as shown in the drawing. Alternatively, the lower electrode LP, the PIN diode DI, and the upper electrode HP may be stacked to have a step shape.

The second passivation layer 160 is formed on the first passivation layer 120 to cover the optical sensor part SR, and a part of the upper electrode HP is formed on the second passivation layer 160. A bias contact hole 162 for exposing and a second data contact hole 164 for exposing the first data contact hole 124 are formed. The second protective layer 160 may be an inorganic insulating layer, and may include, for example, a double layer of a silicon nitride (SiONx) layer having a thickness of about 14500 GPa and a silicon oxide (SiO 2 ) layer having a thickness of about 500 GPa.

The data line DL is formed in the second direction D2 crossing the first direction D1 on the second passivation layer 160 to form the second data contact hole 164 and the first. The data contact hole 124 is electrically connected to the source electrode 30. Specifically, for example, the data line DL may include a data main wiring DL-a formed in the second direction D2 on the second protective layer 160, and the data main wiring DL-a. It may include a data connection (DL-b) branched from). The data connection part DL-b overlaps a portion of the source electrode 30 and is electrically connected to the source electrode 30 through the first data contact hole 124 and the second data contact hole 164. Is connected.

The bias line BL is spaced apart from the data line DL on the second passivation layer 160 in the second direction D2, and is formed through the bias contact hole 162. Electrical connection with HP). The bias line BL may extend in the second direction D2 to cover a portion of the thin film transistor TFT.

The third passivation layer 180 is formed on the second passivation layer to cover the data line DL and the bias line BL. The third protective layer 180 may be an inorganic insulating layer, and may be formed of, for example, a silicon nitride (SiNx) layer having a thickness of about 4000 μm. The organic insulating layer 190 may be formed on the third passivation layer 180 and planarize an upper surface thereof. In this case, it is preferable that both the third protective layer 180 and the organic insulating layer 190 are formed, but in some cases, only one may be formed.

In the present exemplary embodiment, the optical sensor part SR is extended to overlap a portion of the thin film transistor TFT in a unit region formed by the gate line GL and the data line DL. Specifically, for example, the lower electrode LP of the optical sensor part SR may be extended to the channel part CH so as not to overlap with the channel part CH. On the other hand, since the bias line BL is formed in the second direction D2 to cover a portion of the thin film transistor TFT, the lower electrode LP does not overlap the bias line BL. It may be formed to extend to the channel portion (CH) in the direction opposite to the first direction (D1) to the maximum expansion in the range. In this case, the bias line BL may be formed to cover the channel portion CH, and to minimize a portion that coincides or overlaps the lower electrode LP in the first direction D1.

Hereinafter, a method of manufacturing the X-ray detector panel described with reference to FIGS. 1, 2, and 3 will be described.

4 is a cross-sectional view illustrating a manufacturing process up to a first passivation layer during the manufacturing process of the X-ray detector panel of FIG. 1.

Referring to FIG. 4, first, a gate metal layer is formed on the base substrate 100, and the gate metal layer is patterned to form the gate line GL and the gate electrode 10. In this case, the gate metal layer may include, for example, a double layer made of aluminum neodymium compound (AlNd) and chromium (Cr) or a triple layer made of aluminum neodymium compound (AlNd), chromium (Cr) and chromium nitride (CrNx). Can be. In this case, the aluminum neodymium compound (AlNd) may be formed to a thickness of about 2500 kPa, the chromium (Cr) to a thickness of about 500 kPa, and the chromium nitride (CrNx) may be formed to a thickness of about 100 kPa.

Subsequently, the gate insulating layer 110 is formed on the base substrate 100 to cover the gate line GL and the gate electrode 10. In this case, the gate insulating layer 110 may be an inorganic insulating layer, and may be formed of, for example, a silicon nitride (SiNx) layer having a thickness of about 4500 GPa.

Subsequently, an active layer is formed on the gate insulating layer 110, and the active layer is patterned to form the active pattern 20. In this case, the active layer may include a channel layer and an ohmic contact layer. For example, the channel layer may be an amorphous silicon layer having a thickness of about 2200 μs, and the ohmic contact layer may be an ion doped amorphous silicon layer having a thickness of about 500 μs. Accordingly, the active pattern 20 includes the channel pattern formed by patterning the channel layer and the ohmic contact pattern formed by patterning the ohmic contact layer.

Subsequently, after forming a source drain metal layer on the gate insulating layer 110 to cover the active pattern 20, the source drain metal layer is patterned to form the source electrode 30 and the drain electrode 40. do. In this case, the source drain metal layer may be formed of, for example, a chromium (Cr) layer having a thickness of about 1500 kV or a double layer of a chromium (Cr) layer having a thickness of about 1500 kPa and a chromium nitride (CrNx) layer having a thickness of about 100 kPa to 200 kPa. . Meanwhile, when patterning the source drain metal layer, a portion of the active pattern 20 may also be etched. As a result, the ohmic contact pattern of the active pattern 20 may be formed only under each of the source electrode 30 and the drain electrode 40.

Subsequently, after patterning the source drain metal layer, the first passivation layer 120 is formed on the gate insulating layer 110 to cover the source electrode 30 and the drain electrode 40. Here, the first protective layer 120 may be an inorganic insulating layer, for example, a silicon nitride (SiNx) layer having a thickness of about 1000 GPa. Thereafter, a portion of the first passivation layer 120 is etched to expose the drain contact hole 122 exposing a portion of the drain electrode 40 and the first data exposing a portion of the source electrode 30. The contact hole 124 is formed. The first data contact hole 124 may not be formed together with the drain contact hole 122, but may be formed when the second data contact hole 164 of the second protective layer 160 is formed. have.

5 is a cross-sectional view for describing a step of forming a lower metal layer after the manufacturing process of FIG. 4.

Referring to FIG. 5, after etching a portion of the first passivation layer 120, a lower metal layer 130 is formed on the first passivation layer 120. In this case, the lower metal layer 130 may be made of substantially the same material as the source drain metal layer, and may be, for example, a chromium (Cr) layer having a thickness of about 1500 kPa, or about 100 kPa with a chromium (Cr) layer having a thickness of about 1500 kPa. It may be composed of a bilayer of a 200 nm thick chromium nitride (CrNx) layer.

FIG. 6 is a cross-sectional view illustrating a process of forming a PIN semiconductor layer and an upper conductive layer after the manufacturing process of FIG. 5.

Referring to FIG. 6, after forming the lower metal layer 130, a PIN semiconductor layer 140 is formed on the lower metal layer 130. In this case, the PIN semiconductor layer 140 includes a P-type semiconductor layer, an I-type semiconductor layer and an N-type semiconductor layer, wherein the P-type semiconductor layer has a thickness of about 100 GPa and the intrinsic semiconductor layer has a thickness of about 10000 GPa. The N-type semiconductor layer may be formed to a thickness of about 500 GPa.

Subsequently, an upper conductive layer 150 made of a transparent conductive material is formed on the PIN semiconductor layer 140. In this case, the upper conductive layer 150 may be formed of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like, and may be formed to a thickness of about 400 μs.

FIG. 7 is a cross-sectional view illustrating a step of forming an optical sensor unit after the manufacturing process of FIG. 6.

Referring to FIG. 7, after the upper conductive layer 150 is formed, a photoresist layer is formed on the upper conductive layer 150, and a portion of the photoresist layer is exposed by a mask through a mask to remove the photoresist. Form a pattern. Herein, the photoresist layer may use either a positive photoresist layer or a negative photoresist layer.

Subsequently, after the photoresist pattern is formed, the upper conductive layer 150, the PIN semiconductor layer 140, and the lower metal layer 130 are successively patterned at one time by using the photoresist pattern as a mask. . For example, a portion of the upper conductive layer 150, the PIN semiconductor layer 140, and the lower metal layer 130 are simultaneously etched by applying an inductively coupled plasma (ICP). As a result, the upper electrode HP, the PIN diode DI, and the lower electrode LP stacked in the same shape are formed. Thereafter, the photoresist pattern is removed through an etchant.

Meanwhile, the upper conductive layer 150, the PIN semiconductor layer 140, and the lower metal layer 130 may be patterned using different masks. As a result, the lower electrode LP and the PIN diode DI may be patterned. ) And the upper electrode HP may be stacked and formed to have a step shape.

In the present exemplary embodiment, the lower electrode LP of the optical sensor part SR may not overlap the channel part CH in a unit area formed by the gate line GL and the data line DL. The lower metal layer 130 may be patterned to extend to the channel portion CH.

8 is a cross-sectional view illustrating a step of forming a second protective layer, a data line, and a bias line after the manufacturing process of FIG. 7.

Referring to FIG. 8, after forming the optical sensor part SR, the second protective layer 160 is formed on the first protective layer 120 to cover the upper electrode HP. In this case, the second protective layer 160 may be an inorganic insulating layer, and may be formed of, for example, a double layer of a silicon nitride (SiONx) layer having a thickness of about 14500 GPa and a silicon oxide (SiO 2 ) layer having a thickness of about 500 GPa. Thereafter, a portion of the second passivation layer 160 is etched to expose the bias contact hole 162 exposing a portion of the upper electrode HP and the second data exposing the first data contact hole 124. The contact hole 164 is formed. Here, after forming the second data contact hole 164 in the second passivation layer 160, the first data contact hole 124 may be formed in the first passivation layer 120 continuously. .

Subsequently, after etching a portion of the second passivation layer 160, a data metal layer is formed on the second passivation layer 160, and the data metal layer is patterned to form the data wiring DL and the bias wiring ( BL). The data metal layer may include, for example, a double layer of molybdenum (Mo) and aluminum (Al) or a triple layer of molybdenum (Mo), aluminum (Al), and molybdenum (Mo), and the molybdenum (Mo) The thickness of about 500 kPa and the aluminum (Al) may be formed to a thickness of about 2500 kPa.

In the present exemplary embodiment, the bias line BL is patterned to have a shape extending in the second direction D2 to cover the channel portion CH, and the lower electrode LP in the first direction D1. ) May be formed to minimize or overlap with the overlapping portion.

2 and 3, after patterning the data metal layer, the third protective layer 180 is formed to cover the data line DL and the bias line BL. In this case, the third protective layer 180 may be an inorganic insulating layer, and may be formed of, for example, a silicon nitride (SiNx) layer having a thickness of about 4000 μs. Subsequently, the organic insulating layer 190 is formed on the third passivation layer 180.

As described above, according to the present exemplary embodiment, the source sensor 30 of the active pattern 20 is in the unit region formed by the gate line GL and the data line DL. As the maximum extension is formed so as not to overlap the channel portion CH formed between the drain electrode 40, the filter of the optical sensor unit SR may be further improved.

In the detailed description of the present invention described above with reference to the preferred embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary skill in the art will be described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

100: base substrate GL: gate wiring
110: gate insulating layer TFT: thin film transistor
10 gate electrode 20 active pattern
30 source electrode 40 drain electrode
120: first insulating layer 122: drain contact hole
124: first data contact hole 130: lower metal layer
LP: lower electrode 140: PIN diode
DI: PIN diode 150: upper conductive layer
HP: upper electrode 160: second protective layer
162: bias contact hole 164: second data contact hole
DL: data wiring BL: bias wiring
180: third protective layer 190: organic insulating layer
CH: Channel part

Claims (9)

A base substrate;
A gate wiring formed on the base substrate in a first direction;
A gate insulating layer formed on the base substrate to cover the gate wiring;
A gate electrode branched from the gate wiring, an active pattern formed on the gate insulating layer to overlap the gate electrode, a source electrode formed on the active pattern and extending to one side, and formed on the gate insulating layer, and the source electrode A thin film transistor formed on the active pattern to be spaced apart from the active pattern and extending to the other side to include a drain electrode formed on the gate insulating layer;
A first protection layer formed on the gate insulating layer to cover the thin film transistor, the first protective layer having a drain contact hole exposing a portion of the drain electrode and a first data contact hole exposing a portion of the source electrode;
A lower electrode formed on the first protective layer and electrically connected to the drain electrode through the drain contact hole, a PIN diode formed on the lower electrode, and an upper electrode formed of the transparent conductive material on the PIN diode; Optical sensor unit comprising;
A second passivation layer formed on the first passivation layer to cover the photosensor, and having a bias contact hole exposing a portion of the upper electrode and a second data contact hole exposing the first data contact hole;
A data line formed on the second passivation layer in a second direction crossing the first direction and electrically connected to the source electrode through the second data contact hole and the first data contact hole; And
A bias line formed on the second passivation layer, the bias line being spaced apart from the data line and electrically connected to the upper electrode through the bias contact hole;
The optical sensor unit is formed to overlap a portion of the thin film transistor in the unit region formed by the gate wiring and the data wiring. The method of claim 1, wherein the optical sensor unit
The X-ray detector panel of the active pattern is formed so as not to overlap the channel portion formed between the source electrode and the drain electrode. The method of claim 2, wherein the bias wiring is
And an X-ray detector panel formed to cover the channel portion. The method of claim 2, wherein the lower electrode, the PIN diode and the upper electrode
The X-ray detector panel, characterized in that stacked to have the same shape with each other. The X-ray detector panel of claim 1, further comprising a third passivation layer formed on the second passivation layer to cover the data line and the bias line. The X-ray detector panel of claim 5, wherein the first, second, and third protective layers are all inorganic insulating layers. The method of claim 1, wherein the data line is
A data main wiring formed in the second direction; And
An X-ray detector panel including a data connection part which is branched from the data main wiring and overlaps with a part of the source electrode, and is electrically connected to the source electrode through the first data contact hole and the second data contact hole. . Forming a gate wiring extending in a first direction on the base substrate and a gate electrode branched from the gate wiring;
Forming a gate insulating layer on the base substrate to cover the gate wiring and the gate electrode;
Forming an active pattern on the gate insulating layer to overlap the gate electrode;
Forming a source electrode formed on the active pattern and extending to one side on the gate insulating layer, and a drain electrode formed on the active pattern and spaced apart from the source electrode to extend to the other side;
A drain contact hole covering the source electrode, the drain electrode and the active pattern and exposing a portion of the drain electrode and a first data contact hole exposing a portion of the source electrode on the gate insulating layer; 1 forming a protective layer;
An upper electrode disposed on the first passivation layer, the lower electrode electrically connected to the drain electrode through the drain contact hole, a PIN diode disposed on the lower electrode, and a transparent conductive material disposed on the PIN diode; Forming an optical sensor unit;
Forming a second passivation layer on the first passivation layer, the second passivation layer covering the upper electrode and having a bias contact hole exposing a portion of the upper electrode and a second data contact hole exposing the first data contact hole; ; And
A data line extending in a second direction crossing the first direction and electrically connected to the source electrode through the first and second data contact holes and spaced apart from the data line on the second protective layer; Forming a bias line extending in a second direction and electrically connected to the upper electrode through the bias contact hole;
And the optical sensor part is formed so as not to overlap a channel part formed between the source electrode and the drain electrode of the active pattern in a unit region formed by the gate wiring and the data wiring. The method of claim 8, wherein the forming of the optical sensor unit
Forming an upper conductive layer formed of a lower metal layer on the first passivation layer, a PIN semiconductor layer on the lower metal layer, and a transparent metal material on the PIN semiconductor layer; And
And patterning the upper conductive layer, the PIN semiconductor layer, and the lower metal layer at one time through one mask to form the upper electrode, the PIN diode, and the lower electrode. Manufacturing method.
KR1020110015780A 2011-02-23 2011-02-23 X-ray detector panel and method for manufacturing the panel KR20120096606A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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