KR20120095080A - Non-polar or semi-polar group iii-nitride based light emitting diode and fabrication method thereof - Google Patents

Abstract

PURPOSE: A non-polar or semi-polar III group nitride based light emitting diode and a manufacturing method thereof are provided to improve light extraction efficiency by forming a roughness in a cavity. CONSTITUTION: A substrate includes a growth surface of a non-polar or semi-polar epitaxial layer. A first III group nitride layer(102) is grown on a substrate. A second III group nitride layer(104) is grown on the first III group nitride layer with a lateral growth method and includes one or more cavities(105) inside. A light emitting diode structure is grown on the second III group nitride layer. One region of the cavity shows N-polarity.

Description

Non-polar or semi-polar Group II-nitride based light emitting diode and method for manufacturing same {Non-polar or Semi-polar Group III-Nitride Based Light Emitting Diode and Fabrication Method Thereof}

The present invention relates to non-polar or semi-polar Group III nitride based light emitting diodes (LEDs). More specifically, the present invention relates to nonpolar or semipolar III-nitride based LEDs having improved quantum efficiency and nonpolar or semipolar III-nitride based LEDs having increased light extraction efficiency due to roughness.

BACKGROUND ART As a semiconductor light emitting device, LEDs applied to backlight light sources, display light sources, general light sources and full color displays, etc. are widely used by using the characteristics of compound semiconductors. Typical materials of such LEDs are group III-V nitride semiconductors such as GaN (Gallium Nitride), AlN (Aluminum Nitride), InN (Indium Nitride), and the like, and the materials are directly transition-type large energy band gaps. It has a characteristic that is suitable for the optoelectronic device, such as having a gap () to obtain light in the near-wavelength region according to the composition of the nitride, the light emitting device using the same is applied in various fields such as flat panel display device, optical communication.

Such devices are typically grown in a thin film form on a substrate by growth methods such as molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), and hydride vapor phase epitaxy (HVPE).

However, semiconductors based on group III nitrides represented by GaN typically fabricate device structures on (0001) planes using c-plane substrates (eg, sapphire substrates). Spontaneous polarization is formed in the growth direction (0001). In particular, an LED having a typical InGaN / GaN quantum well structure generates internal strain due to lattice mismatch in the quantum well structure when the structure is grown on the (0001) plane, and thus, due to piezoelectric fields. Since the quantum-confined Stark effect (QCSE) is caused, there is a limit to increasing the internal quantum efficiency.

Specifically, group III nitrides, particularly GaN and alloys thereof (eg, alloys with InN and / or AlN), are most stable in hexagonal Wrtzite structures, which The crystal structure is represented by two or three equal basal plane axes in which the crystals are rotated 120 ° relative to each other and are all perpendicular to the c-axis.

Any plane lying perpendicular to the c-axis by the group III element and nitrogen atom position in the urchite crystal structure will contain only one type of atom. Proceeding to the c-axis, each face may contain only one type of atom (group III element or nitrogen). At this time, in order to maintain charge neutrality, for example, the GaN crystal has an N-face containing only nitrogen atoms and a Ga-face containing only Ga atoms at each end. Located in As a result, group III nitride crystals are polar along the c-axis. Such spontaneous polarization depends on the structure and composition of the crystal as a bulk property. Due to the above characteristics, most GaN-based devices grow in a direction parallel to the polar c-axis. In addition, when forming the heterojunction structure, stress due to a large lattice constant difference between Group III nitrides and a property having the same c-axis orientation is generated, which also causes a piezoelectric polarization phenomenon.

As such, the conventional c-plane quantum well structure in group III nitride-based optoelectronic and electronic devices is characterized in that the electrostatic field caused by piezoelectric and spontaneous polarization changes the energy band structure of the quantum well structure, Since the distribution of electrons and holes by the electric field is distorted, the spatial separation of electrons and holes by such an electric field is called a quantum constrained stark effect, which lowers the internal quantum efficiency and causes a red shift of the emission spectrum.

To alleviate the above-mentioned problems. For example, methods for growing non-polar or semi-polar group III nitrides have been proposed. The nonpolar or semipolar planes thus obtained contain the same number of group III atoms and nitrogen atoms and thus exhibit charge neutrality, with the result that the entire crystal is not polarized in the growth direction. However, nonpolar Group III nitride crystals growing on heterogeneous substrates exhibit high defect densities resulting in a problem of reducing quantum efficiency. Therefore, in recent years, in order to realize homoepitaxi characteristics, research on a technique for forming an LED structure on a group III nitride substrate has been conducted.

On the other hand, the external quantum efficiency, the light efficiency, is determined by the product of the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency is determined by the quality of the nitride semiconductor and the current injection efficiency. However, even when manufacturing an LED having the same internal quantum efficiency, the ability to emit light to the outside may vary depending on the light extraction efficiency. That is, when light generated from the active layer inside the LED structure is emitted to the outside, a critical angle at which light can be emitted due to a difference in refractive index between gallium nitride (refractive index = 2.4) and air (refractive index = 1) The angle is reduced to cause light loss due to total internal reflection, and the light incident outside the critical angle is totally reflected until absorbed inside the device, causing the device to generate heat.

In addition, one of the problems in improving the light extraction efficiency of the LED is that the light generated from the active layer inside the chip is totally reflected by the difference in the refractive index of the peripheral layer is absorbed and extinguished while the light is reflected repeatedly. For example, total reflection occurs at the boundary with the sapphire substrate, and total reflection occurs even when light is emitted from the nitride semiconductor layer (specifically, the GaN layer) to the outside.

As such, since nitride has a relatively higher refractive index than these external materials, the critical angles for the internally generated light to escape to the outside are about 23 ° (GaN / air), and about 45 ° (GaN / sapphire).

As a result, a phenomenon in which the light extraction efficiency of the LED is lowered is caused and the light efficiency of the LED is reduced. To alleviate this problem, flip chip structure, surface texturing, patterned sapphire substrate (PSS), photonic crystal technology, and anti-reflection layer) Structure-related technologies are being developed. Among them, in the case of the surface asperity forming technique, it is applied to the n-GaN layer of the vertical chip.

It is true that the above-mentioned techniques contribute to increasing the light extraction efficiency by total internal reflection, but there is still an improvement. In particular, in the case of the surface unevenness forming technique, there is a limit in improving the light extraction efficiency because the area of the surface forming the unevenness is limited.

Accordingly, there is a need for a group III nitride based LED and a method of manufacturing the same, which exhibit improved light efficiency by increasing both internal quantum efficiency and light extraction efficiency.

Accordingly, an embodiment of the present invention is to provide a group III nitride-based LED and a method for manufacturing the same to reduce the light efficiency degradation caused by the polarity and defects of the epitaxy layer.

Embodiment of the present invention is to provide a III-nitride-based LED and a method for manufacturing the same by improving the light efficiency by increasing both the internal quantum efficiency and light extraction efficiency.

According to an aspect of the invention,

A substrate having a growth surface of a nonpolar or semipolar epitaxy layer;

A first group III nitride layer grown on the substrate;

A second III-nitride layer grown on the first III-nitride layer by a lateral growth method and having one or two or more cavities therein; And

A light emitting diode structure grown on the second group III nitride layer;

Including,

A nonpolar or semipolar group III nitride based light emitting diode is provided in which at least one region of the cavity inner surface is N-polar.

According to a second aspect of the invention,

An anisotropically etched silicon (Si) substrate to provide a growth surface of a nonpolar or semipolar epitaxy layer;

b) a Group III nitride layer grown on the etched silicon substrate and having one or more cavities formed therein; And

c) a light emitting diode structure grown on the group III nitride layer;

Including,

A growth surface of the nonpolar or semipolar epitaxy layer has a (111) facet, and a nonpolar or semipolar group III nitride based light emitting diode is provided in which at least one region of the cavity inner surface is N-polar. .

According to a preferred embodiment of the present invention, roughness may be additionally formed on the inner surface of the cavity.

According to a third aspect of the invention,

a) growing a group III nitride layer on a substrate having a growth surface of a nonpolar or semipolar epitaxy layer;

b) growing a group III nitride layer having at least one cavity therein grown on the first group III nitride layer by lateral growth, wherein at least one region of the inner surface of the cavity exhibits N-polarity; ; And

c) growing a light emitting diode structure on the second Group III nitride layer;

Provided is a method of manufacturing a nonpolar or semipolar III-nitride based light emitting diode comprising a.

According to a fourth aspect of the invention,

a) performing anisotropic etching to provide a growth surface of a nonpolar or semipolar epitaxy layer on a silicon (Si) substrate;

b) growing a group III nitride layer while forming one or more cavities on the etched silicon substrate, wherein at least one region of the inner surface of the cavity exhibits N-polarity; And

c) growing a light emitting diode structure on the group III nitride layer grown in step b);

/ RTI >

The growth surface of the nonpolar or semipolar epitaxy layer is provided with a method for producing a nonpolar or semipolar III-nitride based light emitting diode having a (111) facet.

According to a preferred embodiment of the present invention, the method may further include d) forming roughness on the inner surface of the cavity by performing chemical etching.

Nonpolar or semipolar III-nitride light emitting diodes manufactured according to embodiments of the present invention can improve the internal quantum efficiency by mitigating problems caused by polar nitride growth and reducing defects. An illuminance over is formed in the cavity to increase the light extraction efficiency, thereby providing a light emitting diode of improved performance.

1 (a) is a diagram showing nonpolar planes (a-plane and m-plane) of the crystal structure of GaN;
Fig. 1 (b) is a diagram showing a semi-polar plane in the crystal structure of GaN;
2 is a cross-sectional view showing a state in which a group III nitride layer (mold) is formed on a substrate in one embodiment according to the present invention;
3 is a cross-sectional view showing a process of forming a mask pattern (stripe pattern) on the first group III nitride layer in one embodiment according to the present invention;
FIG. 4 is a cross-sectional view showing, in one embodiment according to the present invention, a second III-nitride layer regrown by side growth (or overgrowth) on a first III-nitride layer;
5 is a cross-sectional view showing a cross section in which a light emitting diode structure is formed on a second group III nitride layer in one embodiment according to the present invention;
6 is a cross-sectional view showing a state in which roughness is formed on the inner surface of the cavity of the Group III-nitride layer according to another embodiment of the present invention;
7 is a cross-sectional view schematically showing a state in which a nonpolar or semipolar group III nitride layer having a cavity formed on a silicon substrate is formed on a silicon substrate, and a light emitting diode structure is formed on the silicon substrate as a template; ;
8 is a SEM photograph showing a cross section of a second GaN layer grown in Example 1 of the present invention;
9A and 9B are graphs showing the XRD measurement results for the LED wafer having the LED structure formed in Example 1 of the present invention; And
FIG. 10 is a SEM photograph showing a state in which roughness is formed on an inner surface of a cavity after an etching process for the sample prepared in Example 1 according to Example 2 of the present invention.

The present invention can all be achieved by the following description. The following description is to be understood as describing preferred embodiments of the invention, but the invention is not necessarily limited thereto.

In addition, the accompanying drawings may be somewhat exaggerated relative to the thickness (or height) of the actual layer or the ratio with other layers to facilitate understanding, the meaning of which will be appropriately understood by the specific purpose of the related description to be described later Can be.

In this specification, the expressions "on" and "on" are used to refer to the concept of relative location, where other components or layers are directly present in the layers mentioned, as well as other layers in between. It can be understood that (intermediate layer) or components may be interposed or present. Similarly, the expressions "below", "below", "below" and "between" may also be understood as a relative concept of position.

In the present specification, "Group III nitride" may refer to a semiconductor compound formed of a group III element on the periodic table and nitrogen. As an example of such a group III element, aluminum (Al), gallium (Ga), indium (In), or the like can be exemplified, and these can be included alone or in combination of two or more. Therefore, it can be understood as a concept including GaN, AlN, InN, AlGaN, AlInN, GaInN, AlInGaN and the like. Generalizing this, the group III nitride can be represented by the following general formula (1).

[Formula 1]

Al _x In _y Ga _1-xy N

Where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ x + y ≦ 1.

As used herein, the term “Group III nitride based LED” refers not only to the case where each layer constituting the LED is composed of a Group III nitride material, but also on a Group III nitride layer, for example, III-V or II-VI. It can be understood to include all cases of forming or growing the LED structure of the material.

As used herein, the term "side growth" or "side overgrowth" is a concept that includes lateral epitaxy overgrowth (LEO, ELO or ELOG), PENDEO epitaxy, and the like, and is easier to lateral growth than vertical growth. By doing so, it is possible to suppress propagation of defects or dislocations in a direction perpendicular to the layer surface. Such processes are commonly known in the art for the purpose of reducing defects or dislocations during c-plane GaN growth by MOCVD or the like.

The term " nonpolar " means to have crystallographic directions (e.g., a-plane and m-plane) perpendicular to the c-axis. The nonpolar plane of the group III nitride crystal structure is shown in FIG. as in a).

The term "semipolar" means having a crystal orientation between 0 and 90 ° with respect to (0001) or (000-1). The "semipolar plane" then extends across the hexagonal unit cell diagonally and forms an angle other than 90 ° with the c-axis. In particular, compared to the polar layer, the influence of polarity is reduced because the polar vector is inclined with respect to the growth direction.

Semipolar planes commonly found in group III nitrides are (11-22), (1-101), (10-11), (10-13), (10-12), (20-21). ), (10-14) and the like, but the present invention is not limited to the above specific values. Such a semipolar plane may be represented as shown in FIG. 1 (b). For example, in the case of semipolar GaN in the (11-22) direction, the semipolar plane is inclined about 58 ° with the (0002) plane.

In the present specification, each of the "first conductivity type semiconductor" and the "second conductivity type semiconductor" may mean "n-type" or "p-type", and typically has opposite conductivity characteristics. At this time, a semiconductor such as unintentionally doped GaN may be used as the first conductivity type semiconductor. For example, when the first conductivity type semiconductor is located at a lower side (ie, in the case of a lower conductivity type semiconductor region), the second conductivity type may be a p-type (or n-type) semiconductor. The semiconductor (ie, top conductive semiconductor region) may be an n-type (or p-type) semiconductor.

2 is a view showing a state in which a group III nitride layer (mold) is formed on a substrate in one embodiment according to the present invention.

In this embodiment, the group III-nitride layer may mean a nonpolar or semipolar layer, preferably a semipolar layer. In this case, the group III nitride layer exhibits nonpolar or semipolar characteristics, not polarity, and serves as a template for the subsequently grown group III nitride layer.

According to the figure, first, an epitaxial layer 102 of group III-nitride is grown on the substrate 101. At this time, any substrate suitable for growth of the nonpolar or semipolar III-nitride layer as the substrate 101 may be used without particular limitation. Such substrates can broadly include symmetry-equivalent planes such as a-plane, r-plane or m-plane. .

Further, an r-plane substrate is prepared for the production of a nonpolar group III nitride layer, and an m-plane substrate (for example, (1-100) orientation for the production of a semipolar group III nitride layer. With silver).

In this regard, as the material of the substrate, sapphire, silicon carbide (SiC), lithium aluminate, spinel, and the like may be exemplified, and in some cases, a group III nitride or alloy material thereof (for example, gallium nitride) (GaN), aluminum nitride (AlN) or the like) may be used.

According to an exemplary embodiment of the invention, it may be desirable to use an m-plane sapphire substrate to implement semipolarity as the substrate. Prior to forming a nitride layer on such substrate 101, optionally, removal of residual oxygen in the reaction zone, annealing or heat treatment of the reaction zone using hydrogen and / or nitrogen (high temperature, eg, to a growth temperature) Step) can be performed. In addition, for example, in the case of a sapphire substrate, it may also include the step of nitriding the surface of the substrate using anhydrous ammonia or the like.

In an alternative embodiment of the present invention, an intermediate layer or a buffer layer (not shown) may be formed on the substrate 101 before the first group III nitride layer 102 is grown. Such interlayers can be selectively introduced to obtain better physical properties of the group III nitride layer 102, the exemplary materials being not only group III-V compounds such as AlN, AlGaN, but also nonpolar, in particular semipolar, group III nitride layers It may be another material suitable for promoting the growth of. In this way, when the group III nitride layer is grown on the intermediate layer, the interfacial energy is reduced compared to when directly growing on the heterogeneous substrate, so that high density nucleation is possible, and further, lateral growth is promoted. Due to this, there is an advantage of promoting planar growth, and the lattice mismatch can be alleviated to some extent. At this time, deposition or epitaxial growth techniques known in the art, such as MOCVD, HVPE, etc. may be utilized.

The dimension of the intermediate layer thus selectively introduced is not particularly limited but may be in the range of at least about 10 to 50 nm. In addition, the process conditions can be adjusted to, for example, about 550 to 750 ° C. at atmospheric pressure for the formation of the intermediate layer, which should be understood as an exemplary meaning and the present invention is not limited to the above numerical range.

In the above embodiments, nonpolar or semipolar III-nitride layers can be formed on the substrate (or intermediate layer on the substrate) using conventional layer growth techniques such as MOCVD, HVPE, MBE, etc. It may be desirable to use MOCVD to ensure a better quality template.

In certain embodiments of the present invention, the first group III nitride layer 102 may be formed to a thickness, specifically about 1 to 10 μm, more specifically about 2 to 5 μm. As such, in order to form the first group III nitride layer 102, a growth reaction may be performed for about 60 to 300 minutes under a temperature of about 800 to 1100 ° C. and a pressure of about 200 to 500 torr. The specific growth conditions are described for illustrative purposes, and may be changed according to the size of the substrate and the like, but the present invention is not necessarily limited thereto.

In addition, in the present embodiment, it may be preferable that the first group III nitride layer 102 has a semi-polar direction characteristic, and specifically, substrate characteristics and growth conditions may be adjusted to have a (11-22) direction. .

3 and 4 illustrate a specific pattern of a cavity 105 below the interior of the Group III nitride layer 104 regrown on the Group III nitride layer 102 by lateral growth or overgrowth. It is a figure which shows the process of forming a kind of tunnel by being formed continuously along the mask of (a stripe pattern in drawing).

In the illustrated embodiment, the lateral growth method can be carried out, for example, under ammonothermal growth conditions, and the ELOG method can be used as an example of the various lateral growth methods mentioned above. At this time, a conventional growth method, for example, MOCVD, HVPE, etc. may be used, it may be preferable to use MOCVD to facilitate the formation of a cavity as described below. The reason for this is that it may be easy to implement a cavity, particularly a triangular cavity, by showing a tendency to grow into an inverted leg shape in the lateral growth process, as described below.

The ELOG method is a modification of the selective crystal growth technique, and is used to prevent vertical propagation of dislocations occurring in the initial growth stage by partially patterning the insulating layer of the thin film on the already grown group III nitride layer. Hereinafter, the example will focus on the ELOG method.

Referring to the drawings, first, a patterned mask layer 103 'is formed on the first semipolar group III nitride layer 102 in the form of a stripe. In this case, the mask of the stripe pattern may typically be a dielectric material, and typically include SiO ₂ , SiN _x (eg, Si ₃ N ₄ ), and the like.

In order to form the mask pattern, the insulating layer 103 is first formed by, for example, plasma enhanced chemical vapor deposition (PECVD). Then, one set on the group III nitride layer 102 using conventional photolithography method (in the above method, for etching, a conventional manner such as, for example, ICP-RIE, etc. may be adopted). The parallel stripe pattern 103 'remains. In this case, an area between the masks of the stripe pattern may be referred to as a "window area".

For example, the width of the mask may be set in a range of about 2 to 50 μm (specifically, about 2 to 10 μm), and the width of the window is about 2 to 20 μm (more specifically, about 2 to 10 μm). have.

Further, the mask may be suitable if it is in the range of about 500-2000 mm 3 thickness. In addition, according to the present embodiment, the mask may be formed by setting in all the directions that can be placed on the plane, preferably in the (1-100) direction. The reason for considering the orientation of the mask pattern is because it affects the characteristics such as the facet formation of the over-grown group III nitride layer.

Typically, group III nitrides, especially GaN, are characterized by a much faster growth rate in the c-plane direction than other planes. As described above, when the growth rate in the c-plane direction is reduced by using a mask (for example, SiO ₂ material) pattern to grow at a uniform rate, the quality of the overall growth layer is improved as well as flat and smooth. A surface can be obtained. In particular, when the mask pattern is formed in the (1-100) direction, a smoother surface can be formed. However, when the mask is patterned in the (-1-123) direction, the uneven surface of the micro unit may be formed. Therefore, although the present embodiment is not necessarily limited to the mask pattern in a specific direction, it may be more preferable to set the mask pattern in the (1-100) direction.

Then, a group III nitride regrowth process is performed, which begins in the window region, where the microstructure of the underlying group III nitride layer 102 is reproduced, while the growth is over the mask region. It won't happen. Over time, crystals growing in the window region gradually grow (overgrowth) over the mask. As such, the growth layer of group III nitride extends vertically and laterally, wherein the regions grown laterally are referred to as " wing regions ". In the wing region, high quality crystals can be obtained in which defects are significantly reduced by lateral growth.

In addition, the rate of extension between vertical and side (horizontal) depends on growth conditions, such that a nitride overgrown layer extending from the window to the side (e.g., the right direction) over time will have a side ( For example, it may meet and merge with the nitride overgrowth layer extending in the left direction. As a result, a cavity 105 is formed below the joining boundary, which is formed continuously along the mask pattern to form a kind of tunnel structure. The cavity 105 may exhibit various shapes such as a triangle, a square, a rectangle, a circle, and the like, depending on process conditions, but may have a triangular shape as shown.

Although the above embodiment illustrates a case in which the cavities are continuously connected and formed as a tunnel, this is provided as a preferable purpose, and may be included in the scope of the present invention even if intentionally or unintentionally closed in some sections.

In the present embodiment, semi-polar III-nitride may be suitable for forming a kind of tunnel by continuously connecting the cavity in the II-III nitride layer, but the present invention is not limited thereto. Non-polar group III nitrides are also possible if one cavity is available.

The thickness of the group III-nitride layer 104 may be, for example, in the range of about 3 to 10 μm, and the size (diameter or height) of the cavity is about 2 to 50 μm, more specifically about 2 to May be in the range of 10 μm. These numerical ranges are exemplary and can be adjusted according to changes in process conditions.

For example, the triangular cavity size may be formed differently according to the size of the pattern mask. For example, when the mask width of the pattern is about 7 μm, the diameter of the triangular cavity is about 6 μm wide. Will have. If the width of the mask increases, the diameter of the triangular cavity also increases in proportion to this, and the growth time will also increase as the width of the mask increases.

The second group III nitride layer 104 according to the illustrated embodiment may be formed (grown) by various parameter combinations, for example, the growth temperature is about 700 to 1,100 ° C. (more specifically about 800 to 1,000). ° C), and the pressure may range from about 200 to 400 mTorr. For example, when the mask pattern is in the (1-100) direction, the mask pattern may be performed at about 800 to 1100 ° C. for about 240 to 600 minutes. In this case, the flow rate of the Ga source (eg, trimethylgallium, triethylgallium, etc.) supplied may range from about 10 to 30 sccm.

 The second III-nitride layer 104 grows in an inverted trapezoidal shape from the window and gradually forms a triangular-shaped cavity 105.

The lateral growth layer obtained as described above can be characterized by x-ray diffraction (XRD) analysis, and in the case of nonpolar and semipolar layers, it is usually anisotropic according to the angle (direction angle). In this regard, for the semipolar group III nitrides obtainable by lateral growth in this embodiment, for example, the range of about 300 to 500 arc sec (the FWHM value in arcsec (degree × 3600)) It may be desirable to indicate.

FIG. 5 is a cross-sectional view showing a cross section in which a light emitting diode (LED) structure is formed on the second group III nitride layer 104 in the embodiment of the present invention.

According to the figure, the LED structure is configured in the order of the first conductive semiconductor layer 111, the active layer 112 and the second conductive semiconductor layer 113 from below. In addition, an electrode 114 is formed on the second conductive semiconductor layer 113, and an electrode 115 is formed on an exposed surface of the first conductive semiconductor layer 111. If the first conductive semiconductor layer 111 is an n-type semiconductor material, the electrode 115 may be an n-type electrode, and the second conductive semiconductor layer 113 may be a p-type semiconductor material. In this case, the electrode 114 may be a p-type electrode. The layer configuration shown above is provided for illustrative purposes and various LED structures known in the art can be employed without particular limitation.

Meanwhile, materials of the first and second conductivity-type semiconductor layers 111 and 113 and the active layer 112 formed on the group III-nitride layer 104 are not particularly limited, and various known materials for manufacturing LEDs are known in the art. Semiconductor materials (III-V, II-VI, etc.) such as GaN, InN, AlN, InP, InS, GaAs, CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, Al _x Ga _1-x N, In _x Ga _1-x N, In _x Ga _1-x As, Zn _x Cd _1-x S, and the like may be used, and these may be used alone or in combination (in the above, 0 <x <1). In addition, the type of the first conductivity type semiconductor and the second conductivity type semiconductor may be different. However, it may be desirable to use group III nitride to effectively implement homoepitaxy properties.

In addition, the active layer 112 may be made of at least two materials selected from, for example, GaN, AlN, InN, InGaN, AlGaN, InAlGaN, or the like. Among them, a material having a small energy band gap may be used as a quantum well, and a material having a large energy band gap may be configured as a quantum barrier, and both single and multi quantum well structures may be used.

Dimensions of each layer constituting the above-described LED structure are also not particularly limited, but may be configured to have the dimensions shown in Table 1 below.

First conductive semiconductor layer Active layer (well: barrier) Second conductivity type semiconductor layer thickness About 0.6-10 μm, preferably about 2-5 μm -Well layer
About 1-5 nm, preferably about 2.5-3 nm

-Barrier layer
About 5-25 nm, preferably about 7-15 nm About 50-500 nm,
Preferably about 150-300 nm

In addition, in the case of the electrodes 114 and 115 for electrical application, for example, platinum (Pt), palladium (Pd), aluminum (Al), gold (Au), nickel / gold (Ni / Au) alone Or in combination. For this electrode pattern formation, conventional methods such as photoresist patterning-etching, which are known in the art, may be performed.

FIG. 6 is a view showing a cross section of an LED device having roughness formed on an inner surface of a cavity of a Group II III nitride layer by chemical etching in a preferred embodiment of the present invention.

As shown, roughness is formed in the inner surface of the cavity, particularly in the form of a tunnel, by chemical etching. The reason why the chemical etching is possible in the above embodiment may be explained as follows, but the present invention is not limited thereto.

Representative Group III nitride GaN crystals have two different faces, a Ga-face and an N-face. At this time, the Ga-plane is terminated at the end by a gallium atom, while the N-plane is terminated by the nitrogen atom at the end. Ga-plane is chemically stable, whereas N-plane is chemically unstable and highly reactive.

Usually, in the case of a polar nitride layer ((0001) surface) grown on a c-plane substrate, since the end of the surface is Ga-plane, it is chemically very stable and chemical etching is difficult. However, in the case of the etched object, especially the group III-nitride layer 104, an N-polar surface will be present in the cavity inner surface (eg, at least one region of the cavity inner surface). Specifically, the -c plane and the (n- or r-) plane exist on both sides of the triangular cavity, respectively, while the bottom surface of the cavity is formed of SiO ₂ , for example. In the illustrated embodiment, there may be a -c plane that exhibits N-polarity and two (n- or r-) planes that partially represent N-polarity on two sides of the tunnel except the bottom plane in the tunnel. have.

In general, when chemical etching is possible with respect to the N-polar plane, not only the surface showing the N-polarity is etched, but one GaN particle is etched because the binding energy of Ga and N is larger in one GaN particle. . Therefore, when the N-polarity is exposed, chemical etching may occur on the exposed surface, that is, the inner surface of the cavity. Roughness may be formed regularly or irregularly by chemical etching.

In order to implement the chemical etching, various wet etching methods may be used, and as long as roughness 106 may be formed on the inner surface of the cavity 105, it is not necessarily limited to a specific method. Typically, an aqueous solution of an acid (for example a strong acid such as H ₃ PO ₄ ) or an aqueous solution of a base (for example an alkali salt such as NaOH, KOH or a mixture thereof) can be used.

In this embodiment, the chemical etching will preferably be carried out under conditions that form roughness 106 in the interior of the cavity 105 without affecting each layer constituting the LED. For example, when using an aqueous base solution, more specifically an aqueous KOH solution, the molar ratio of KOH to water may range from about 1 to 10, more specifically about 1 to 5, using examples of such aqueous base solutions. For example, temperature conditions in the range from room temperature to about 500 ° C., specifically from room temperature to 200 ° C., can be set.

In addition, the etching time may range from about 1 second to 10 minutes, specifically about 1 to 5 minutes. The etching conditions are provided for illustrative purposes, and the present invention is not necessarily limited to the above conditions, and may be changed depending on the crystal characteristics in the object to be etched, the diameter size of the cavity according to the pattern mask size, and the like. However, under excessively harsh etching conditions, the inner surface of the cavity 105 and / or other layers constituting the LED element may be damaged to deteriorate light emission characteristics. As such, the chemical etching conditions are not set uniformly, and optimal conditions can be derived by considering the degree of improvement in light extraction efficiency.

Meanwhile, according to another embodiment of the present invention, a nonpolar or semipolar group III nitride light emitting diode using a silicon (Si) substrate and a method of manufacturing the same are provided.

FIG. 7 is a cross-sectional view schematically illustrating a state in which a nonpolar or semipolar III-nitride layer in which a cavity is formed on a silicon substrate is formed and an LED structure is formed on the III-nitride layer; FIG. .

In the above-described embodiment, for example, (111) facets are formed on the upper surface of the silicon substrate 201. In this case, the silicon substrate may be, for example, a (311) or (001) silicon substrate. As shown, a patterning step, specifically, a patterning process through an anisotropic etching, may be performed to form the (111) facet. As such, the (111) facets formed on the silicon substrate may selectively grow (form) group III nitride (ie, selective growth). That is, the group III nitride layer 204 may be grown (formed) by forming, for example, a triangular shaped cavity 205 by (111) facets formed on a silicon substrate.

In this embodiment, the group III nitride layer 204 grown while the cavity 205 is formed is semipolar (eg, (1-101) or (11-22)) or nonpolar (eg, ( 11-20)). Accordingly, the group III nitride layer 204 acts as a kind of mold, and constitutes a LED structure formed thereon, for example, a first conductive semiconductor layer 211, an active layer 212, and a second conductive type. The semiconductor layer 213 may similarly exhibit semipolar or nonpolar characteristics.

Meanwhile, according to the present embodiment, the (111) facet may be formed using a pattern mask layer (for example, a SiO ₂ mask).

According to an exemplary embodiment, first, a SiO ₂ mask (eg, about 70 nm thick, about 1 μm or less mask width, about 1 to 3 μm pattern spacing) on a (311) silicon substrate is subjected to photolithography techniques and the like. To form a pattern (e.g., stripe pattern) on a silicon substrate, etch at about 30 to 50 [deg.] C with an etchant (e.g., KOH solution), and then, for example, HF (e.g., diluted HF), buffered oxide etchant (HF + NH ₄ F mixture; BOE) and the like can be used to remove the mask layer. The (111) facets are formed on the silicon substrate by the etching process.

Thereafter, a III-nitride layer 204 having a predetermined thickness is formed on the silicon substrate through (re) growth such as MOCVD. In the growth process, the intermediate layer or the buffer layer (not shown) described above may be selectively formed.

The growth of the above-mentioned group III nitride may be performed at, for example, about 900 to 1,100 ° C. Subsequently, the formation (growth) of the LED structure consisting of the first conductivity type semiconductor layer 211, the active layer 212, and the second conductivity type semiconductor layer 213 in order, and in further embodiments the inner surface of the cavity 205. Principles and detailed processes of chemical etching for forming roughness in are the same as described above, and thus will be omitted.

Group III nitride based LEDs manufactured according to the above embodiments may have the following advantages.

First, by implementing an epitaxy layer having apolar or semipolarity, it is possible to alleviate a phenomenon such as a spontaneous polarization, such as a light efficiency deterioration factor conventionally seen in a polar growth layer.

In addition, by forming the LED structure on the side growth layer, the defect density, etc. is significantly reduced, it is possible to ensure a higher quality crystal quality, and as a result it is possible to increase the internal quantum efficiency.

In addition, when roughness is formed on the inner surface of the cavity formed in the side growth layer, roughness can be formed over a larger area than the surface roughness technique known in the art (cavity area formed inside the LED element is relatively larger). As a result, the escape paths of the generated light are relatively more diverse. Therefore, in addition to the effect of increasing the internal quantum efficiency, it is possible to further improve the light extraction efficiency can improve the overall light efficiency. In this regard, by forming roughness on the inner surface of the cavity, for example, an effect of improving light extraction efficiency of about 5 to 50%, specifically about 10 to 30% can be obtained.

The present invention can be more clearly understood by the following examples, which are only intended to illustrate the present invention and are not intended to limit the scope of the invention.

Example 1

1st GaN Layer growth

A planar semipolar GaN layer was formed on an m-sapphire substrate (Crystal-On Company: M-plane 2 "sapphire wafer, thickness 430 μm) using the MOCVD equipment (Veeco) under the conditions of Table 2 below. At this time, trimethylgallium and ammonia were used as the gallium source and the nitrogen source, respectively.

Temperature (℃) Time (min) Pg (Torr) Nitriding 1080 0.75 500 Low Temperature Growth (Middle Layer) 700 4 200 Recrystallization 1060 5 200 High temperature growth 880 180 300

Analysis by HR-XRD confirmed that a semipolar GaN layer having a thickness of about 2 μm and a direction of (11-22) was formed.

Growth of the Second GaN Layer

ELOG was performed on the first GaN layer using a mask of stripe pattern arranged at regular intervals. At this time, as a mask, a SiO ₂ layer was first deposited to a thickness of 100 nm by PECVD, and then the width (mask area) and stripe spacing (window area) of the stripe were measured by ICP-RIE etching using standard photolithography. It adjusted to 7 micrometers and 4 micrometers. At this time, the mask pattern was formed in the (1-100) direction.

The GaN layer was then regrown at 880 ° C. and 300 mTorr using MOCVD (ELOG). At this time, the side growth layer had a thickness of about 4 μm.

Process conditions for lateral growth layer formation are shown in Table 3 below.

Growth conditions Mask pattern direction (1-100) Growth time (minutes) 360 Flow rate of gallium source (sccm) 20

An SEM photograph of the cross-section of the laterally grown second GaN layer is shown in FIG. 8.

The GaN layer regrown from the window region gradually extended laterally overgrown over the mask region over time, and as the lateral growth continued, the lateral growth layers extending from the left and right over the wing region merged with each other. As shown, it can be seen that the triangular cavities are continuously connected along the mask pattern to form a tunnel.

On the other hand, using a XRD analysis device (PANalytical, product name: High-resolution X-Ray diffraction), FWHM (full width at half maximum; unit: arcsec) value according to the azimuthal angle for the side-grown sample The change of was measured. As a result, the FWHM values of the samples were 733, 468, 517, and 840 arcsec, respectively. From this, it can be seen that the semipolar characteristics are relatively excellent and the anisotropy is low.

Formation (growth) of LED structure

A sample having a cavity tunnel prepared as described above was placed in a MOCVD (manufacturer: Vecco, product name: D180mini) chamber, and an n-type GaN layer having a thickness of 3 μm was grown at 880 ° C.

In the MOCVD chamber, a multi-quantum well layer (active layer) consisting of five pairs of about 2 nm thick InGaN wells and about 7 nm thick GaN barriers on the growth layer of n-type GaN (780 ° C.) and 830 ° C., respectively. LED wafers were prepared by forming a p-type GaN layer of 150 nm thickness on the multi-quantum well layer sequentially at 980 ° C. (total thickness: 50 nm) and sequentially. The XRD measurement results for the LED wafer thus manufactured are shown in FIGS. 9A and 9B.

FIG. 9A is a measurement result when rotated by 90 ° in a phi scan, and FIG. 9B shows characteristics obtained by measuring while rotating in a phi scan. According to the figure, it was confirmed that the LED constituent layers in the manufactured LED wafer had a (11-22) direction.

Example 2

KOH aqueous solution (molar ratio of KOH / H ₂ O = 1: 10) was added to a height high enough to contain the prepared sample, which was placed on a hot plate. The sample was added while maintaining the temperature after raising the KOH aqueous solution to 300 ° C. The SEM image showed the change (10 seconds) of the second GaN layer due to etching, and the results are shown in FIG. 10.

As confirmed in the figure, it can be seen that roughness is formed on the inner surface of the cavity as the etching proceeds.

Example 3

A 70 nm thick SiO ₂ mask layer was sputter deposited on the (311) substrate, and a stripe pattern was formed using a photolithography method (mask width of 1 μm, pattern spacing of 2 μm). The silicon substrate was then etched at 40 ° C. with KOH solution (25%). As a result, (111) facets formed on the silicon substrate surface, which were removed using diluted HF solution.

Thereafter, the LED structure was formed under the same conditions as in Example 1 to manufacture an LED wafer. As a result of XRD measurement on the manufactured LED wafer, it was confirmed that it had semipolar characteristics.

Simple modifications and variations of the present invention can be readily used by those skilled in the art, and all such variations or modifications can be considered to be included within the scope of the present invention.

101: substrate
102: Group III-nitride layer
103: insulator layer for mask
103 ': mask pattern layer
104: Group II III nitride layer
105, 205: cavity
106: roughness
111, 211: first conductive semiconductor layer
112, 212: active layer
113, 213: second conductive semiconductor layer
114, 115, 214, 215: electrode
201: Silicon substrate with (111) facet formed
204: Group III nitride layer

Claims (15)

A substrate having a growth surface of a nonpolar or semipolar epitaxy layer;
A first group III nitride layer grown on the substrate;
A second III-nitride layer grown on the first III-nitride layer by a lateral growth method and having one or two or more cavities therein; And
A light emitting diode structure grown on the second group III nitride layer;
Including,
A nonpolar or semipolar group III nitride based light emitting diode in which at least one region of the inner surface of the cavity exhibits N-polarity. An anisotropically etched silicon (Si) substrate to provide a growth surface of a nonpolar or semipolar epitaxy layer;
b) a Group III nitride layer grown on the etched silicon substrate and having one or more cavities formed therein; And
c) a light emitting diode structure grown on the group III nitride layer;
Including,
And a growth surface of the nonpolar or semipolar epitaxy layer has a (111) facet, and at least one region of the cavity inner surface is N-polar. The nonpolar or semipolar group III nitride based light emitting diode of claim 1, wherein the substrate providing the growth surface of the nonpolar or semipolar epitaxy layer is an m-plane sapphire substrate. The nonpolar or semipolar III-nitride based light emitting diode according to claim 1, wherein the first III-nitride layer is a semipolar layer in the (11-22) direction. The nonpolar or semipolar III-nitride based light emitting diode according to claim 1 or 2, wherein roughness is formed on an inner surface of the cavity. a) growing a group III nitride layer on a substrate having a growth surface of a nonpolar or semipolar epitaxy layer;
b) growing a group III nitride layer having at least one cavity therein grown on the first group III nitride layer by lateral growth, wherein at least one region of the inner surface of the cavity exhibits N-polarity; ; And
c) growing a light emitting diode structure on the second Group III nitride layer;
Non-polar or semi-polar group III nitride-based light emitting diode comprising a. a) performing anisotropic etching to provide a growth surface of a nonpolar or semipolar epitaxy layer on a silicon (Si) substrate;
b) growing a group III nitride layer while forming one or more cavities on the etched silicon substrate, wherein at least one region of the inner surface of the cavity exhibits N-polarity; And
c) growing a light emitting diode structure on the group III nitride layer grown in step b);
Including;
And a growth surface of the nonpolar or semipolar epitaxy layer has a (111) facet. The method of claim 6, wherein the lateral growth method is an epitaxial lateral overgrowth (ELOG) method. The method of claim 7, wherein step b)
(i) forming a patterned mask layer on the first Group III nitride layer; And
(ii) laterally growing a group III nitride layer on the first group III nitride layer on which the patterned mask layer is formed;
Method for producing a non-polar or semi-polar group III nitride based light emitting diode comprising a. 10. The method of claim 9, wherein the mask layer is patterned in the (1-100) direction. 10. The method of claim 9,
The mask layer is a method of manufacturing a non-polar or semi-polar group III nitride based light emitting diode, characterized in that the SiO ₂ or SiN _x material. 10. The method of claim 9,
The mask layer is formed in a stripe pattern,
The width and the stripe spacing of the stripe is a method for producing a nonpolar or semipolar group III nitride based light emitting diode, characterized in that the range of 2 to 50 ㎛ and 2 to 20 ㎛ respectively. 8. The method of claim 6 or 7, further comprising d) forming a roughness on the inner surface of the cavity by performing chemical etching. The method of claim 13, wherein the chemical etching is performed in an aqueous KOH solution. 15. The method of claim 14, wherein the KOH molar ratio of the aqueous KOH solution to water ranges from 1 to 10.

Images