KR20120088440A - The Circuit for generating Output Enable Signal - Google Patents

The Circuit for generating Output Enable Signal Download PDF

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Publication number
KR20120088440A
KR20120088440A KR1020110009797A KR20110009797A KR20120088440A KR 20120088440 A KR20120088440 A KR 20120088440A KR 1020110009797 A KR1020110009797 A KR 1020110009797A KR 20110009797 A KR20110009797 A KR 20110009797A KR 20120088440 A KR20120088440 A KR 20120088440A
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KR
South Korea
Prior art keywords
pulse
signal
read pulse
read
output enable
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KR1020110009797A
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Korean (ko)
Inventor
강재석
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020110009797A priority Critical patent/KR20120088440A/en
Publication of KR20120088440A publication Critical patent/KR20120088440A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Abstract

The output enable signal generation circuit of the present invention includes a read pulse generator for generating a read pulse in response to a read command and a clock signal, a variable delay unit for outputting the read pulse as a delayed read pulse by varying the delay of the read pulse according to a variable delay signal. And a sensing output unit configured to sense a delayed read pulse according to the signal and to generate an output enable signal according to the sensed result.

Description

Output Enable Signal Generation Circuit {The Circuit for generating Output Enable Signal}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device using an output enable signal.

In a semiconductor memory device such as a DRAM, an output enable signal (OE) is used to output data according to a read command. When the output enable signal OE is activated, the semiconductor memory device starts to output the latched data in response to the read command.

The output enable signal OE is generated in response to the read command RD, the clock signal CLK, and the DLL clock signal CLKDLL. Therefore, the activation time of the read command RD, the clock signal CLK, and the DLL clock signal CLKDLL becomes an important factor for stably activating the output enable signal OE.

When the DLL operation is performed, the DLL clock signal CLKDLL may be synchronized with the clock signal CLK according to the delay lock operation. However, when the DLL operation is stopped, the DLL clock signal CLKDLL has a delay value of a predetermined time compared to the clock signal CLK, unlike when the DLL operation is performed. The delay value of this predetermined time varies with PVT changes (Process, Voltage, Temperature Change). Therefore, when the PVT change is large, the timing margins of the read command RD, the clock signal CLK, and the DLL clock signal CLKDLL are reduced. When the DLL operation is stopped, if the delay time of the DLL clock signal CLKDLL relative to the clock signal CLK is changed by more than half of the clock signal CLK relative to the design value, the output enable signal OE is activated at the wrong time. Cas Latency Fail may occur.

Variation of the delay time of the DLL clock CLKDLL according to the PVT change may cause more problems than the low frequency region for the output enable signal OE when operating in the high frequency region.

SUMMARY OF THE INVENTION The present invention has a technical problem to provide an output enable signal generation circuit insensitive to PVT variation.

An output enable signal generation circuit according to an embodiment of the present invention includes a read pulse generation unit generating a read pulse in response to a read command and a clock signal, and varying the read pulse according to a variable delay signal to output the delay pulse. And a sensing output unit configured to sense the delayed read pulse according to a variable delay unit and a pulse signal, and generate an output enable signal according to the detected result.

In addition, the output enable signal generation circuit according to another embodiment of the present invention includes a read pulse generator for generating a read pulse in response to a read command and a clock signal, and variable delay the read pulse in accordance with a variable delay signal as a delay read pulse. A variable delay unit for outputting a first sensing output unit for detecting the delayed read pulse according to a first pulse and generating a first output enable signal according to the detected result, the first output enable signal and a second pulse And a second sensing output for generating a second output enable signal in response.

The present invention creates the effect of preventing the generation of an error of the output enable signal that can occur in accordance with the PVT change.

1 is a schematic block diagram of an output enable signal generation circuit according to an embodiment of the present invention;
2 is a schematic block diagram of an output enable signal generation circuit according to another embodiment of the present invention, FIG. 3 is a signal waveform diagram of the output enable signal generation circuit shown in FIG.
4 is a schematic diagram of an exemplary embodiment of the variable delay unit 200 illustrated in FIGS. 1 and 2.

1 is a schematic block diagram of an output enable signal generation circuit according to an embodiment of the present invention.

The output enable signal generation circuit may include a read pulse generator 100, a variable delay unit 200, and a sensing output unit 300.

The read pulse generator 100 generates a read pulse RDp in response to the read command RD and the clock signal CLK. The read pulse generator 100 may be configured to detect activation of the read command RD in response to the clock signal CLK and generate the read pulse RDp having a predetermined pulse width. The read pulse generator 100 may be configured to include a general pulse generation circuit.

The variable delay unit 200 variably delays the read pulse RDp according to the variable delay signal Del <0: 3> and outputs the delayed pulse RDpd. The variable delay signal Del <0: 3> may be used as a signal of a plurality of bits to vary the delay time of the variable delay operation. 1 is illustrated as a 4 bit signal. The variable delay signal Del <0: 3> may be used as a test mode signal. The variable delay unit 200 may include a plurality of delay circuits having different delay values according to the variable delay signals Del <0: 3>.

The sensing output unit 300 detects the delayed read pulse RDpd according to a pulse signal pul and generates an output enable signal OE according to the detected result. The pulse signal pul is a signal activated in response to the DLL clock signal CLKDLL. The sensing output unit 300 may include a general sensing circuit and an amplifier circuit.

Since the sensing output unit 300 detects the delayed read pulse RDpd according to the pulse signal pul, the output enable according to the timing of the pulse signal pul and the delayed read pulse RDpd. Whether the signal OE is generated may vary. The output enable signal generation circuit according to an embodiment of the present invention generates the delayed read pulse RDpd by performing the variable delay operation of the variable delay unit 200, and thus the delayed read pulse RDpd and the pulse. The timing margin of the signal pul can be improved.

As mentioned above, the delay time of the DLL clock signal CLKDLL may vary according to the PVT change. Accordingly, since the timing of activation of the pulse signal pul is also affected, the output enable signal generation circuit according to an embodiment of the present invention can prevent an error of the output enable signal OE due to a PVT change. have.

2 is a schematic block diagram of an output enable signal generation circuit according to another embodiment of the present invention.

The output enable signal generation circuit shown in FIG. 2 is suitable for use in a semiconductor memory device using a plurality of DLL clocks, such as a semiconductor memory device such as a DDR system. The semiconductor memory device using the DDR method uses a first DLL clock FCLKDLL and a second DLL clock RCLKDLL having an inverted phase of the first DLL clock FCLKDLL as a DLL clock.

The output enable signal generation circuit illustrated in FIG. 2 may include a read pulse generator 100, a variable delay unit 200, a first sensing output unit 310, and a second sensing output unit 320. Can be.

The read pulse generator 100 generates a read pulse RDp in response to the read command RD and the clock signal CLK. The read pulse generator 100 illustrated in FIG. 2 may be configured and operate in the same manner as the read pulse generator 100 illustrated in FIG. 1.

The variable delay unit 200 variably delays the read pulse RDp according to the variable delay signal Del <0: 3> and outputs the delayed pulse RDpd. The variable delay signal Del <0: 3> may be used as a signal of a plurality of bits to vary the delay time of the variable delay operation. 1 is illustrated as a 4 bit signal. The variable delay signal Del <0: 3> may be used as a test mode signal. The variable delay unit 200 illustrated in FIG. 2 may be configured and operate in the same manner as the variable delay unit 200 illustrated in FIG. 2.

The output enable signal generation circuit illustrated in FIG. 2 is not limited, but includes the first sensing output unit 310 and the second sensing output unit 320 corresponding to two pulse signals.

The first sensing output unit 310 detects the delayed read pulse RDpd according to the first pulse signal pul1, and generates the first output enable signal OE1 according to the detected result.

The second sensing output unit 320 generates a second output enable signal OE2 in response to the first output enable signal OE1 and the second pulse pul2.

The first pulse signal pul1 is a signal activated in response to the first DLL clock FCLKDLL, and the second pulse signal pul2 is a signal activated in response to the first DLL clock RCLKDLL. The first and second sensing output units 310 and 320 may include a general sensing circuit and an amplifying circuit.

The output enable signal generation circuit shown in FIG. 2 generates the delayed read pulse RDpd by performing the variable delay operation by the variable delay unit 200, like the output enable signal generation circuit shown in FIG. 1. Therefore, timing margins of the delayed read pulse RDpd and the first pulse signal pul1 may be improved.

The variable delay time of the variable delay unit 200 may be set in consideration of timing margins of the delay read pulse RDpd and the first pulse signal pul1. As shown in FIG. 2, the variable delay unit 200, the first sensing output unit 310, and the second sensing output unit 320 are connected to each other in series. Since the second pulse signal pul2 received by the second sensing output unit 320 is influenced by the same as the first pulse signal pul1 with respect to the PVT change, the first sensing output unit 310 is The normal operation of generating the first output enable signal OE1 may be regarded as the second sensing output unit 320 also operating normally to generate the second output enable signal OE2.

Also as mentioned above, the first pulse signal pul1 is activated in response to the first DLL clock FCLKDLL, and the second pulse signal pul2 is activated in response to the second DLL clock RCLKDLL. It can be configured using a signal. As illustrated in FIG. 2, the output enable signal generation circuit may further include a first pulse generator 410 and a second pulse generator 420.

The first pulse generator 410 generates the first pulse pul1 in response to the first DLL clock FCLKDLL.

The second pulse generator 420 generates the second pulse pul2 in response to the second DLL clock RCLKDLL. The first pulse generator 410 and the second pulse generator 420 may be configured to include a general pulse generation circuit.

3 is a signal waveform diagram of the output enable signal generation circuit shown in FIG. 2.

As shown in FIG. 3, when the clock signal CLK is activated, the read pulse generator 100 detects activation of the read command RD and detects the read pulse RDp having a predetermined pulse width. Create

The variable delay unit 200 variably delays the read pulse RDp according to the variable delay signal Del <0: 3> to generate the delayed read pulse RDpd. 3, the delay read pulse RDpd may be variably delayed.

Referring to FIG. 3, it is shown that the first pulse signal pul1 is not intended to be limited but is activated twice. It is shown as (a) and (b) for convenience of description.

The designer's intention assumes that the delayed read pulse RDpd is activated between the activation points of (a) and (b) (see the delayed read pulse RDpd solid line waveform in Fig. 3). If the delayed read pulse RDpd is activated before the step (a) as shown by the dotted line in FIG. 3 according to the PVT change, the first output enable signal OE1 is activated in response to the step (a). Accordingly, the first and second output enable signals OE1 and OE2 are activated one cycle before the intention as shown by the dotted line in FIG. 3. This error is called CAS Latency Fail.

As shown in FIG. 3, the first output enable as the variable delay unit 200 generates the delay read pulse RDpd in a solid line according to the variable delay signal Del <0: 3>. Signal OE1 may be activated in response to the activation time of (b). In addition, the second output enable signal OE2 may be activated in response to a second activation time of the second pulse signal pul2 (see FIG. 3D).

As described above, the output enable signal generation circuit according to another embodiment of the present invention performs a variable delay operation to the variable delay unit 200 to perform timing margins of the delayed read pulse RDpd and the first pulse signal pul1. Can be improved.

4 is a schematic diagram of an exemplary embodiment of the variable delay unit 200 illustrated in FIGS. 1 and 2.

As mentioned above, the variable delay unit 200 variably delays the read pulse RDp according to the variable delay signal Del <0: 3> to generate the delayed read pulse RDpd.

The variable delay unit 200 illustrated in FIG. 4 is configured when all bits of the variable delay signal Del <0: 3> are deactivated to 0 and one bit of the variable delay signal Del <0: 3>. And configured to generate the delay read pulse RDpd with five different delay times in some cases where only 1 and the remaining bits are zero.

Here, in order to more efficiently make the timing margin for the output enable signal according to the embodiment of the present invention, the delay read pulse RDpd may be based on the third longest delay time value among the five different delay times. It is desirable to have time and configure it to have one of the remaining delay times as the PVT changes. The variable delay unit 200 shown in FIG. 4 is configured to implement this feature.

The variable delay unit 200 illustrated in FIG. 4 may include first to fifth delay circuits 210 to 250 and a basic signal generator 260.

The variable delay unit 200 illustrated in FIG. 4 may determine which of four bits of the variable delay signal Del <0: 3> is activated or four bits of the variable delay signal Del <0: 3>. The read pulse RDp is outputted as the delayed read pulse RDpd through some of the first to fifth delay circuits 210 to 250 according to whether the bits are all zeros. have. Since this configuration is a configuration that can be easily implemented by those skilled in the art, a detailed description thereof will be omitted.

In addition, although the variable delay unit 200 shown in FIG. 4 is configured to variably delay the read pulse RDp with five different delay times, this is illustrated as an embodiment. It is noted that the variable delay operation of the variable delay unit 200 having five different delay times does not limit the scope of the present invention.

For example, the variable delay unit 200 may be configured to variably delay the read pulse RDp with three different delay times. In this case, it is preferable that the delay read pulse RDpd has a second longest delay time value among the three different delay times as a basic delay time, and has one of the remaining delay times according to the PVT change.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: read pulse generator 200: variable delay unit
210: first delay circuit 220: second delay circuit
230: third delay circuit 240: fourth delay circuit
250: fifth delay circuit 260: basic signal generator
300: sensing output unit 310: first sensing output unit
320: second sensing output unit 410: first pulse generating unit
420: second pulse generator

Claims (11)

A read pulse generator generating a read pulse in response to a read command and a clock signal;
A variable delay unit for delaying the read pulse according to a variable delay signal and outputting the read pulse as a delay read pulse; And
And a sensing output unit for sensing the delayed read pulse according to a pulse signal and generating an output enable signal according to the detected result. The method of claim 1,
And an average value of delay time of the variable delay unit is a half period of the clock signal. The method of claim 2,
The variable delay unit variably delays the read pulse with three different delay times,
And a second longest delay time of said three delay times is a half period of said clock signal. The method of claim 1,
And the read pulse generator detects activation of the read command in response to the clock signal and generates the read pulse having a predetermined pulse width. A read pulse generator generating a read pulse in response to a read command and a clock signal;
A variable delay unit for delaying the read pulse according to a variable delay signal and outputting the read pulse as a delay read pulse;
A first sensing output unit configured to sense the delayed read pulse according to a first pulse and generate a first output enable signal according to the sensed result
And a second sensing output unit configured to generate a second output enable signal in response to the first output enable signal and the second pulse. The method of claim 5, wherein
And an average value of delay time of the variable delay unit is a half period of the clock signal. The method according to claim 6,
The variable delay unit variably delays the read pulse with three different delay times,
And a second longest delay time of said three delay times is a half period of said clock signal. The method of claim 5, wherein
And the read pulse generator detects activation of the read command in response to the clock signal and generates the read pulse having a predetermined pulse width. The method of claim 5, wherein
And the first sensing output unit senses activation of the delayed read pulse signal in response to the first pulse signal, and generates the first output enable signal having a predetermined pulse width. The method of claim 5, wherein
And the second sensing output unit detects activation of the first output enable signal in response to the second pulse signal, and generates the second output enable signal having a predetermined pulse width. The method of claim 5, wherein
A first pulse generator configured to generate the first pulse in response to a first DLL clock; And
And a second pulse generator configured to generate the second pulse in response to a second DLL clock.
KR1020110009797A 2011-01-31 2011-01-31 The Circuit for generating Output Enable Signal KR20120088440A (en)

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