KR20120085027A - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Semiconductor light emitting device and manufacturing method thereof Download PDF

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KR20120085027A
KR20120085027A KR1020110006410A KR20110006410A KR20120085027A KR 20120085027 A KR20120085027 A KR 20120085027A KR 1020110006410 A KR1020110006410 A KR 1020110006410A KR 20110006410 A KR20110006410 A KR 20110006410A KR 20120085027 A KR20120085027 A KR 20120085027A
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layer
light emitting
emitting device
metal
semiconductor light
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KR1020110006410A
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Korean (ko)
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고형덕
박용조
조주영
박성주
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삼성전자주식회사
광주과학기술원
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Publication of KR20120085027A publication Critical patent/KR20120085027A/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0083—Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biophysics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Led Devices (AREA)

Abstract

The present invention relates to a semiconductor light emitting device and a method of manufacturing the same.
A light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, and formed in at least one of the first and second conductive semiconductor layers, the light emitted from the active layer, and a surface thereof. It provides a semiconductor light emitting device comprising a plasmon generating layer consisting of a metal nano-pattern to cause plasmon resonance in.

Description

Semiconductor Light Emitting Device and Manufacturing Method

The present invention relates to a semiconductor light emitting device and a method of manufacturing the same.

In general, semiconductor light emitting devices are widely used in green or blue light emitting diodes (LEDs) or laser diodes (LDs) provided as light sources in full-color displays, image scanners, various signal systems, and optical communication devices. Has been. Such a semiconductor light emitting device can be provided as a light emitting device having an active layer emitting a variety of light, including blue and green using the recombination principle of electrons and holes.

After the development of such semiconductor light emitting devices, many technological developments have been made, and the range of their use has been expanded, and many studies have been conducted on general light sources and electric light sources. In particular, the conventional semiconductor light emitting device is mainly used as a component that is applied to low current / low power mobile products, and as the application range is gradually expanded to the high current / high power field recently, by increasing the internal quantum efficiency and external quantum efficiency Research for improving the light output of the light emitting device has been actively conducted.

One object of the present invention is to provide a semiconductor light emitting device in which the surface plasmon mutual coupling efficiency is maximized to improve internal quantum efficiency.

Another object of the present invention is to provide a semiconductor light emitting device in which an optical path changing effect is increased due to a difference in refractive index between a semiconductor layer and a plasmon generating layer, thereby improving external light extraction efficiency.

Another object of the present invention is to provide a method of manufacturing a semiconductor light emitting device that can solve the problem that the characteristics and ratio of the surface plasmon cross-linking changes according to the size or density change of the metal nanoparticles.

According to an aspect of the present invention,

A light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And a plasmon generating layer formed in at least one of the first and second conductivity type semiconductor layers, the plasmon generating layer having a metal nano pattern to cause plasmon resonance on the light emitted from the active layer and its surface. to provide.

In one embodiment of the present invention, the metal nano pattern may be made of one or more metals selected from the group consisting of Ag, Au, Pt, Al, Cu, Ni and Ti.

In one embodiment of the present invention, the plasmon generating layer may have a distance of less than 100nm from the active layer.

In one embodiment of the present invention, the metal nano-pattern may be formed by arranging a plurality of metals having a plurality of bar shapes spaced apart at regular intervals.

In one embodiment of the present invention, the metal nano-pattern may be formed by arranging a plurality of metals having a polygonal column shape to form a row and a row.

In this case, an interval between the metal nano patterns may be 1 nm to 10 μm.

In one embodiment of the present invention, the plasmon generating layer may be formed on the surface of the active layer.

In one embodiment of the present invention, the plasmon generating layer may be symmetrically formed in the first and second conductivity-type semiconductor layers with respect to the active layer.

Another aspect of the invention,

Sequentially forming a first conductivity type semiconductor layer and an active layer on the substrate, forming a metal layer on the active layer, patterning the metal layer to form a metal nanopattern, and covering the metal nanopattern It provides a semiconductor light emitting device manufacturing method comprising the step of forming a second conductive semiconductor layer.

In an embodiment, the method may further include forming a second conductive semiconductor layer on the active layer, and the metal layer may be formed on the second conductive semiconductor layer.

In one embodiment of the present invention, the patterning may be made by selectively etching the metal layer by at least one of photo-lithography, holography- lithography and nano-imprint lithography.

In the semiconductor light emitting device according to the embodiment of the present invention, the internal quantum efficiency is improved by maximizing the surface plasmon mutual coupling efficiency,

In addition, the optical path changing effect is increased due to the difference in refractive index between the semiconductor layer and the plasmon generating layer, thereby improving external light extraction efficiency.

In addition, the method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention includes a plasmon generating layer formed in the form of a metal nanopattern, whereby characteristics and ratios of surface plasmon cross-linking may vary according to the size or density of the metal nanoparticles. You can solve the problem of change.

1 is a perspective view showing a semiconductor light emitting device according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view taken along line AA ′ of FIG. 1.
3 is a schematic plan view of FIG. 1 viewed from the top.
4 is a schematic plan view of a semiconductor light emitting device according to another embodiment of the present invention as viewed from above.
5 is a perspective view schematically showing a semiconductor light emitting device according to still another embodiment of the present invention.
6 is a cross-sectional view schematically showing a semiconductor light emitting device according to still another embodiment of the present invention.
7 to 10 are diagrams showing a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

1 is a perspective view illustrating a semiconductor light emitting device according to an exemplary embodiment of the present invention, FIG. 2 is a schematic cross-sectional view taken along line AA ′ of FIG. 1, and FIG. 3 is a schematic plan view of FIG. 1 viewed from above. to be. 1 to 3, the semiconductor light emitting device 100 according to the present embodiment includes a first conductive semiconductor layer 21, an active layer 22, and a second conductive semiconductor layer (on a substrate 10). A light emitting structure 20 including 23 is formed, and inside the at least one of the first and second conductivity-type semiconductor layers 21 and 23, light emitted from the active layer 22 and plasmon resonance on the surface thereof. The plasmon generating layer 30 is formed of a metal nano-pattern to form a. In addition, the first conductive type formed on the first conductive type semiconductor layer 21 exposed by etching part of the second conductive type semiconductor layer 23, the active layer 22, and the first conductive type semiconductor layer 21. The electrode 21a and the second conductivity type electrode 23a formed on the upper surface of the second conductivity type semiconductor layer 23 may be included.

In the present embodiment, the first and second conductivity-type semiconductor layers 21 and 23 may be n-type and p-type semiconductor layers, respectively, and may be formed of a nitride semiconductor. Therefore, the present invention is not limited thereto, but in the present embodiment, the first and second conductivity types may be understood to mean n-type and p-type, respectively. The first and second conductivity-type semiconductor layers 21 and 23 are Al x In y Ga (1-xy) N composition formulas, where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ x + y ≦ 1. ), For example, GaN, AlGaN, InGaN, and the like may correspond to this. The active layer 22 formed between the first and second conductive semiconductor layers 21 and 23 emits light having a predetermined energy by recombination of electrons and holes, and the quantum well layer and the quantum barrier layer alternate with each other. It may be made of a multi-quantum well (MQW) structure stacked. In the case of a multi-quantum well structure, for example, an InGaN / GaN structure may be used. Meanwhile, the first and second conductivity type semiconductor layers 21 and 23 and the active layer 22 may be formed using a semiconductor layer growth process such as MOCVD, MBE, HVPE, and the like known in the art.

The substrate 10 is for growing a semiconductor single crystal, in particular, a nitride single crystal, and may use a substrate made of a material such as sapphire, SiC, MgAl 2 O 4 , MgO, LiAlO 2 , LiGaO 2 , GaN, or the like. In this case, the sapphire is a Hexa-Rhombo R3c symmetric crystal, and the lattice constants in the c-axis and a-axis directions are 13.001 4. and 4.758 C, respectively, C (0001) plane, A (1120) plane, R 1102 surface and the like. In this case, the C plane is mainly used as a nitride growth substrate because the C surface is relatively easy to grow and stable at high temperatures. Although not shown, a buffer layer may be interposed therebetween to mitigate lattice mismatch between the light emitting structure 20 made of a semiconductor layer and the substrate 10. This buffer layer may be a low temperature nucleus growth layer including AlN or GaN.

The plasmon generating layer 30 is formed in at least one of the first and second conductivity-type semiconductor layers 21 and 23, and is formed of a metal nano pattern so that light emitted from the active layer 22 may be formed in the metal nano pattern. By causing plasmon resonance at the surface, the internal quantum efficiency of the light emitting device can be improved. In one embodiment of the present invention, the metal nano pattern is formed in the first and second conductivity-type semiconductor layer (21, 23), the first and second conductivity-type semiconductor layer (21, 23) As well as the case where it is disposed to be completely enclosed, as will be described later (see Figure 6), a part of the metal nano-pattern inside the light emitting structure 20 in contact with the first or second conductivity-type semiconductor layer (21, 23), The remaining part includes a form formed to be adjacent to the active layer 22. The metal nanopattern constituting the plasmon generating layer 30 is a material suitable for utilizing the surface plasmon phenomenon, and may easily be used for the emission of electrons by an external stimulus and metals having a negative dielectric constant. Specifically, Ag , Au, Pt, Al, Cu, Ni and Ti may be made of one or more metals or alloys thereof selected from the group consisting of.

As shown in FIG. 3, the metal nanopattern forming the plasmon generating layer 30 may be formed of a metal nanopattern having a bar shape, having a width of 10 nm to 10 μm, and a width of 10 nm to 10 μm. It may be spaced apart to have a spacing of μm, causing plasmon resonance at the light emitted from the active layer 22 and its surface. In addition, the plasmon generating layer 30 may be formed to have a distance that can cause surface plasmon by the light emitted from the active layer 22, that is, a distance of 100 nm or less from the active layer 22.

Surface plasmons are collective charge density oscillations of electrons occurring on the metal thin film surface, and the surface plasmon waves generated are surface electromagnetic waves propagating along the interface between the metal and the dielectric. On the other hand, as a photo-electron effect that occurs in metals such as gold (Au) and silver (Ag), when light of a specific wavelength is irradiated onto the metal, a resonance phenomenon occurs in which most of the light energy is transferred to free electrons. As a result, the phenomenon that occurs when surface electromagnetic waves occur is called Surface Plasmon Resonance. The conditions for the surface plasmon resonance to occur is the wavelength of the incident light, the refractive index of the material in contact with the metal, and the like, in particular, the distance between the active layer and the metal nanopattern is very important. That is, the surface plasmon resonance may occur when the distance between the active layer and the metal nanopattern is less than or equal to a predetermined distance. In this embodiment, the distance between the active layer 22 and the plasmon generating layer 30 having the metal nanopattern corresponds to this. Specifically, the thickness is preferably 100 nm or less.

According to the present embodiment, the plasmon generating layer 30 is formed in the form of a metal nanopattern formed to have a constant cycle, not in the form of metal nanoparticles, and thus, according to the size or density change of the metal nanoparticles, It is possible to solve the problem of different characteristics and ratios, and improve the internal quantum efficiency by maximizing the surface plasmon mutual coupling efficiency by adjusting the shape, thickness, width and pitch of the metal nanopattern. In addition, the metal nano-pattern is formed to be embedded in the first and second semiconductor layers 21 and 23, so that the first and second conductivity-type semiconductor layers 21 and 23 and the plasmon generating layer are formed. Due to the difference in refractive index between the 30, the optical path changing effect is increased, and the external light extraction efficiency can be improved.

Meanwhile, the first and second conductive electrodes 21a and 23a formed on the first and second conductive semiconductor layers 21 and 23 are provided as an electrical connection region with a lead frame or an external electrode. It may be made of a metal material having electrical conductivity. In the present exemplary embodiment, the first and second conductivity type electrodes 21a and 23a are illustrated to be formed adjacent to corners of the first and second conductivity type semiconductor layers 21 and 23, but are not limited thereto. The shape, size and position may be appropriately determined in consideration of the current dispersion efficiency inside the semiconductor layer.

4 is a schematic plan view of a semiconductor light emitting device according to another embodiment of the present invention as viewed from above. According to the present embodiment, unlike the embodiment illustrated in FIGS. 1 to 3, the plasmon generating layer 31 formed of a metal nano pattern having a square pillar shape may be interposed inside the second conductive semiconductor layer 20. have. At this time, the metal nano-pattern constituting the plasmon generating layer 31 is made of one or more metals or alloys thereof selected from the group consisting of Ag, Au, Pt, Al, Cu, Ni, and Ti as in the previous embodiment. The light emitting device may be disposed to be spaced apart from each other to have a width of 10 nm to 10 μm and an interval of 10 nm to 10 μm to cause plasmon resonance on light emitted from the active layer 22 of the light emitting structure 20 and a surface thereof. It can improve the internal quantum efficiency. However, in the present embodiment, the metal nano pattern is illustrated in the form of a square pillar, but is not limited thereto, and may be formed to have a polyhedron shape including various shapes such as a circle and a polygon which may maximize the plasmon resonance phenomenon. Can be.

5 is a perspective view schematically showing a semiconductor light emitting device according to still another embodiment of the present invention. The semiconductor light emitting device 200 according to the present embodiment is formed on the conductive substrate 40 and the conductive substrate 40, and has a first conductivity type semiconductor layer 21, an active layer 22, and a second conductivity type. The light emitting structure 20 including the semiconductor layer 23 and the first conductive type electrode 21a formed on the upper surface of the first conductive type semiconductor layer 21 are included. In this case, inside the first and second conductivity-type semiconductor layers 21 and 23, a plasmon generating layer 32 made of a metal nano pattern is formed to cause plasmon resonance on the light emitted from the active layer 22 and its surface. It may include.

The conductive substrate 40 may be a substrate for growing a semiconductor from a first conductive semiconductor layer 21, an active layer 22, and a second conductive semiconductor layer 23 sequentially formed on a growth substrate (not shown). (Not shown) serves as a support for supporting a light emitting structure including the first and second conductive semiconductor layers 21 and 23 and the active layer 22 in a process such as laser lift off. A material containing any one of Ni, Al, Cu, W, Si, Se, and GaAs, for example, may be formed of a material doped with Al on a Si substrate. In the present embodiment, the conductive substrate 40 may be bonded to the light emitting structure through a conductive adhesive layer (not shown). The conductive adhesive layer may use a eutectic metal material such as, for example, AuSn. In addition, the conductive substrate 40 may function as a second conductive electrode for applying an electrical signal to the second conductive semiconductor layer 23. As shown in FIG. 5, the electrode is formed in a vertical direction. In this case, the current flow region can be enlarged to improve the current spreading function.

In the present embodiment, unlike the embodiment shown in FIG. 1, the plasmon generating layer 32 may be formed in the first and second conductivity-type semiconductor layers 21 and 23, respectively. Specifically, inside the first conductive semiconductor layer 21 and the second conductive semiconductor layer 23, the metal nano-patterns may be used to cause plasmon resonance in light emitted from the active layer 22 and its surface. 32a, 32b may be disposed within a position adjacent to the active layer 22, preferably within a distance of 100 nm or less. In this case, light emitted from the active layer 22 is emitted toward the first and second semiconductor layers 21 and 23, and plasmons are generated in the first and second semiconductor layers 21 and 23, respectively. By the surface plasmon resonance phenomenon occurring in the layers 32a and 32b, the light output of the light emitting device can be improved.

6 is a cross-sectional view schematically showing a semiconductor light emitting device according to still another embodiment of the present invention. The semiconductor light emitting device 201 according to the present embodiment is formed on the conductive substrate 40 and the conductive substrate 40, and includes the first conductive semiconductor layer 21, the active layer 22, and the second conductive semiconductor. The light emitting structure 20 includes a layer 23 and a first conductive type electrode 21a formed on the first conductive type semiconductor layer 21. In the present embodiment, the plasmon generating layer 33 formed in the first conductivity type semiconductor layer 21 is formed of a metal nanopattern so as to cause plasmon resonance on the light emitted from the active layer 22 and its surface. It may be formed to contact the surface of the active layer 22. In order for surface plasmon resonance to occur on the surface of the metal nanopattern constituting the plasmon generating layer 33, the plasmon generating layer 33 should be positioned within a predetermined distance from the active layer 22 from which light is emitted. It is also possible. In this case, as in the foregoing embodiment, the light emitting structure 20 including the plasmon generating layer 33 may be formed on the growth substrate instead of the conductive substrate 40, and the first conductive semiconductor layer ( 21 as well as the second conductive semiconductor layer 22 may be formed.

7 to 10 are diagrams showing a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention. Specifically, a process diagram for manufacturing a semiconductor light emitting device according to the embodiment shown in FIG. 1, first, as shown in FIG. 7, the first conductivity-type semiconductor layer 21 on the semiconductor growth substrate 10, The active layer 22 and the second conductivity-type semiconductor layer 23 ′ are sequentially grown using a semiconductor layer growth process such as MOCVD, MBE, HVPE, etc. to form the light emitting structure 20. However, the step of forming the second conductivity-type semiconductor layer 23 'is not necessarily required, and unlike the present embodiment, except for the second conductivity-type semiconductor layer 23', the substrate for semiconductor growth Only up to the first conductivity-type semiconductor layer 21 and the active layer 22 may be formed on (10).

The semiconductor growth substrate 101 includes sapphire, SiC, MgAl 2 O 4 , MgO, LiAlO 2 , LiGaO 2 , GaN, or the like can be used. In this case, the sapphire is a Hexa-Rhombo R3c symmetric crystal and the lattice constants of c-axis and a-direction are 13.001 13. and 4.758Å, respectively, C (0001) plane, A (1120) plane, R 1102 surface and the like. In this case, the C plane is mainly used as a nitride growth substrate because the C surface is relatively easy to grow and stable at high temperatures. Although not shown, a buffer layer (not shown) made of an undoped semiconductor layer made of nitride or the like may be interposed to alleviate lattice defects of the light emitting structure grown on the substrate.

Next, as shown in FIG. 8, the metal layer 30 ′ is formed on the second conductive semiconductor layer 23 ′. The metal layer 30 ′ may be formed to have a thickness of several nm, and may be a material suitable for using a surface plasmon phenomenon, and may easily emit electrons by an external stimulus and have a negative dielectric constant, specifically, Ag, Au, It may consist of one or more metals or alloys thereof selected from the group consisting of Pt, Al, Cu, Ni and Ti. In this case, the metal layer 30 ′ may be formed by a deposition process using sputtering, e-beam evaporation, or the like.

Next, as shown in FIG. 9, in order to form the plasmon generating layer 30 formed of the metal nano-pattern, the metal layer is selectively removed using an electron beam (E-beam), or photo-lithography, holography A method of selectively etching the metal layer using various lithography methods such as lithography or nano-imprint lithography may be used. As the etching method, dry and wet etching methods such as ICP, RIE, and chemical etching may be variously used. In this case, through the etching process, it is possible to precisely control the shape, the position spacing, etc. of the metal nano-pattern, thereby maximizing the surface plasmon mutual ratio to improve the internal quantum efficiency.

Alternatively, an etching mask having a plurality of openings is formed on a surface of the second conductivity type semiconductor layer 23 ', a metal layer is deposited on the etching mask, and then the etching mask is removed to correspond to the mask opening. The metal nano pattern may be formed in the region. This is a process of forming a pattern without using a general etching process, which is called a lift-off process. In this case, the mask may be formed through a photo-resist process, and after forming a metal nanopattern through a deposition process, the mask may be removed by dissolving with a photoresist solvent to remove the mask without a separate etching process. A plasmon generating layer 30 of a desired shape may be formed on the light emitting structure 20.

Next, as shown in FIG. 10, the second conductive semiconductor layer 23 is surfaced by stacking the second conductive semiconductor layer 23 to cover the plasmon generating layer 30 including the metal nanopattern. Can be formed flat. In the present embodiment, as the second conductive semiconductor layer 23 surrounds the surface of the plasmon generating layer 30, the refractive index difference between the metal nano pattern and the second conductive semiconductor layer 23 is different. By forming the photonic crystal structure through the external light extraction efficiency can be improved.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

100, 101, 200, and 201: semiconductor light emitting device 10: substrate
20: light emitting structure 21: first conductive semiconductor layer
21a: first conductive electrode 22: active layer
23, 23 ': second conductivity-type semiconductor layer 23a: second conductivity-type electrode
30, 31, 32, 33: plasmon generating layer 40: conductive substrate

Claims (11)

A light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And
A plasmon generating layer formed in at least one of the first and second conductivity type semiconductor layers, the plasmon generating layer having a metal nano pattern to cause plasmon resonance at light emitted from the active layer and its surface;
Semiconductor light emitting device comprising a.
The method of claim 1,
The metal nano pattern is a semiconductor light emitting device, characterized in that made of at least one metal selected from the group consisting of Ag, Au, Pt, Al, Cu, Ni and Ti.
The method of claim 1,
The plasmon generating layer is a semiconductor light emitting device, characterized in that the separation distance from the active layer is 100nm or less.
The method of claim 1,
The metal nano-pattern is a semiconductor light emitting device, characterized in that formed with a plurality of metal having a plurality of bar shape arranged to be spaced apart at a predetermined interval.
The method of claim 1,
The metal nano pattern is a semiconductor light emitting device, characterized in that formed with a plurality of metal having a polygonal column shape arranged in a row and a row.
The method according to claim 4 or 5,
The interval between the metal nano pattern is a semiconductor light emitting device, characterized in that 1nm to 10㎛.
The method of claim 1,
The plasmon generating layer is a semiconductor light emitting device, characterized in that formed on the surface of the active layer.
The method of claim 1,
The plasmon generating layer is formed around the active layer, the semiconductor light emitting device, characterized in that formed symmetrically in the first and second conductive semiconductor layer.
Sequentially forming a first conductivity type semiconductor layer and an active layer on the substrate;
Forming a metal layer on the active layer;
Patterning the metal layer to form a metal nano pattern; And
Forming a second conductive semiconductor layer to cover the metal nano pattern;
Gt; a < / RTI > semiconductor light emitting device.
10. The method of claim 9,
Forming a second conductivity type semiconductor layer on the active layer;
The metal layer is a semiconductor light emitting device manufacturing method, characterized in that formed on the second conductive semiconductor layer.
10. The method of claim 9,
The patterning is a method of manufacturing a semiconductor light emitting device, characterized in that by selectively etching the metal layer by at least one of photo-lithography, holography- lithography and nano-imprint lithography.
KR1020110006410A 2011-01-21 2011-01-21 Semiconductor light emitting device and manufacturing method thereof KR20120085027A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015026691A (en) * 2013-07-25 2015-02-05 日本放送協会 Semiconductor light emitting element
US9847621B2 (en) 2013-10-31 2017-12-19 Samsung Electronics Co., Ltd. Apparatus for outputting directional light and light interconnection system having the same
US9911990B2 (en) 2013-10-01 2018-03-06 Samsung Electronics Co., Ltd. Fuel cell stack including end plate having insertion hole

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015026691A (en) * 2013-07-25 2015-02-05 日本放送協会 Semiconductor light emitting element
US9911990B2 (en) 2013-10-01 2018-03-06 Samsung Electronics Co., Ltd. Fuel cell stack including end plate having insertion hole
US9847621B2 (en) 2013-10-31 2017-12-19 Samsung Electronics Co., Ltd. Apparatus for outputting directional light and light interconnection system having the same

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