KR20120082012A - Continuous tunable lc resonator using a fet as a varactor - Google Patents

Abstract

The varactor includes a field effect transistor (FET) integrated with at least a portion of the bipolar junction transistor (BJT), in which the back gate of the FET shares an electrical connection with the base of the BJT and is applied to the back gate of the FET. The reverse voltage creates a continuous variable capacitance in the channel of the FET.

Description

CONTINUOUS TUNABLE LC RESONATOR USING A FET AS A VARACTOR}

A varactor diode, commonly referred to as a varactor, is one type of PN junction diode that has high junction capacitance upon reverse bias. The capacitance is variable and is a function of the voltage applied to its terminals. In general, such devices with variable or tunable capacitance are used in inductive (L) capacitive (C) (LC) resonant circuits used as tuning circuits, for impedance matching or as isolation circuits. .

One technique for fabricating semiconductor devices is a combined gallium arsenide (GaAs) heterojunction bipolar transistor (HBT)-field effect transistor (FET) technology, where the FET is a specialized FET in depletion-mode (d-mode). It is a specialized device integrated with HBT that has properties similar to metal oxide field effect transistors (MESFETs). Such integration techniques are generally referred to as "BiFETs", but alternative nomenclature and integration techniques exist for combining HBTs and FETs on GaAs.

Other semiconductor technologies can also be used to fabricate FETs. One example is complementary metal oxide semiconductor (CMOS) technology that integrates both n-type and p-type e-mode MOSFETs on the same silicon substrate. Regardless of the technique used to manufacture the FET, when the device is off, the FET can be controlled to have a variable capacitance. Therefore, it would be desirable to have a method of using FETs as varactors. If a varactor can be implemented to have a wide tuning range with continuous tunable characteristics, the varactor can be tuned to tunable LC circuits, tunable RF matching networks, and any other application requiring electronic tunable capacitance. Can be used.

Embodiments of the present invention include a varactor comprising a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which the back gate of the FET shares an electrical connection with the base of the BJT. In addition, the reverse voltage applied to the back gate of the FET creates a continuous variable capacitance in the channel of the FET.

Other embodiments are also provided. Other systems, methods, features and advantages of the present invention will become or become apparent to those skilled in the art upon review of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this description, to fall within the scope of the invention, and to be protected by the appended claims.

The invention can be better understood with reference to the drawings below. The components in the figures are not necessarily drawn to scale, but illustrate the principles of the invention. Moreover, in the drawings, like reference numerals designate corresponding elements throughout the different views.
1 is a cross-sectional view of a FET in a BiFET process that can function as a varactor.
2 is a cross-sectional view of a CMOS NFET device that can function as a varactor.
3 is a schematic diagram illustrating one embodiment of the FET of FIG. 1 implemented as a varactor.
4 is a schematic diagram illustrating an alternative embodiment of the circuit of FIG. 3.
5 is a graph illustrating a tuning range of the FET of FIG. 1.
FIG. 6 is a graph showing measurements of frequency versus scattering parameter S21 of the implementation shown in FIG. 3.
7 is a flow chart illustrating a method of operation of a circuit embodiment using the FET of FIG. 1 or 2 as a varactor.
8 is a block diagram illustrating a simplified portable communication device.

The reverse voltage applied across the PN junction of the semiconductor device creates an area in which there is little current and there are a few electrons or holes. This region is called the depletion region. In FET devices, this region may be formed in the "channel" of the FET. Since there are essentially no carriers, this region behaves as the dielectric of the capacitor and the capacitance is variable with voltage.

Examples of configurations of BiFET devices are shown in US Pat. No. 5,250,826 and US Pat. No. 6,906,359, both of which are incorporated herein by reference.

Regardless of how it is configured, one of the characteristics exhibited by a FET device, in particular a FET device formed in a BiFET process or other processes, is that when the device is switched off, the channel region is “gate” and / or “the” of the FET. "Back gate" has a capacitance that can be varied by changing the reverse voltage applied to it. In this way, the FET behaves like a varactor.

Continuously tunable LC resonators using FETs as varactors can be fabricated using a variety of materials. In embodiments using the technique described in FIG. 1, a continuous tunable LC resonator using a FET as a varactor is made by forming materials of various binary, ternary and quaternary bonds using elements of Groups 3 and 5 In one embodiment, an indium gallium phosphide (InGaP) / gallium arsenide (GaAs) material system is prepared.

In one embodiment, complementary metal oxide semiconductor (CMOS) technology can be used to fabricate NFETs or PFETs, which can also be used to implement continuous tunable LC resonators using FETs as varactors. When bipolar devices are incorporated into a CMOS process, this technique is commonly known as BiCMOS. In alternative embodiments, silicon junction field effect transistor (JFET) technology may be used to implement a continuous tunable LC resonator using FETs as varactors. JFET technology can also be incorporated with silicon bipolar technology.

Continuously tunable LC resonators using FETs as varactors may be used in applications including, but not limited to, input radio frequency (RF) switches in power amplifier modules. Such a switch is also referred to as an "RF pass gate" and may have a narrow frequency bandwidth. However, a continuous tunable LC resonator using FETs as a varactor can be used in any other circuit using a tunable LC resonant circuit.

1 is a cross-sectional view of FET 100 in a BiFET process that can function as a varactor. FETs that can function as varactors can be manufactured using other techniques, one of which is described below, but BiFET technology is attractive for this application because it allows the FET to have a wide tuning range. The epitaxy layer structure shown in FIG. 1 forms a FET 100 incorporating a MESFET into the emitter layers of the HBT, with some of the layers representing the HBT portion of the device omitted for simplicity. Only the FET portions of the BiFET process associated with the description of the continuous tunable LC resonator using the FET as a varactor are described herein.

FET 100 uses portions of base 102 formed using a layer of gallium arsenide (GaAs), on which emitter 104 is layered of gallium arsenide (GaAs) and indium gallium phosphide (InGaP). Are formed using them. PN junction 126 is formed at the interface of base 102 and emitter 104. Although not shown for clarity, as is known in the art, emitter 104 generally includes a lightly doped emitter layer, a lightly doped emitter cap layer, and a heavily doped emitter contact layer. As shown approximately, a back gate contact 118 is formed from an ohmic metal deposited on an exposed surface of the base 102. The back gate contact 118 is also understood to include a back gate.

A channel 108 is formed under the front gate contact 116 by an indium gallium phosphide (InGaP) layer and a gallium arsenide (GaAs) layer 106 forming the emitter 104. Although shown as including layers 104 and 106, channel 108 is formed by depletion regions 132 and 134 formed within portions of layers 104 and 106 under certain electrical conditions described below. Front gate contact 116 with Schottky barrier properties is located above layer 106. Over the layer 106 is a source 112 and drain 114 in the form of a “mesa”. Front gate contact 116 is also understood to include a front gate.

The layers of the epitaxy structure shown in FIG. 1 are the base layers of the device. Depending on the process and manufacturing techniques, other and / or additional layers may be included in the device 100.

A source contact 122 is formed on the source 112, and a drain contact 124 is formed on the drain 114. The voltage applied to the front gate contact 116 affects the depletion region 132 controlled by the front gate, and the voltage applied to the back gate contact 118 is applied to the depletion region 134 controlled by the back gate. Affect. In FIG. 1, the front gate contact 116 is shown electrically connected to the back gate contact 118, although this is not the case for all embodiments. In alternative embodiments, the front gate contact 116 may be electrically isolated from the back gate contact 118 to form a four terminal FET. Such an apparatus is schematically shown and described in FIG. 4. According to an embodiment, the voltage applied to the front gate contact 116 may be the same as or different from the voltage applied to the back gate contact 118. In addition, a reverse voltage may be applied only to the front gate contact 116 or the back gate contact 118. According to one embodiment, the reverse voltage applied to the front gate contact 116 and / or back gate contact 118 changes the capacitance of the channel 108 when the FET is off. Channel capacitance appears as the capacitance between source 112 and drain 114.

In one embodiment, the back gate contact 118 may be electrically coupled to the front gate contact 116, such that the reverse voltage applied to the front gate contact 116 and the back gate contact 118 is the same.

The total gate capacitance of the FET is determined by the number of individual capacitances. For example, the front gate capacitance Cg includes the area component Cga of the Schottky gate capacitance + the peripheral component Cgp of the Schottky gate capacitance. The capacitance Cbg of the back gate includes the base emitter junction capacitance Cbex in the region outside the gate + the base emitter junction capacitance Cbei under the front gate. Thus, in the embodiment where the back gate contact 118 and the front gate contact 116 are electrically connected to each other as shown in FIG. 3, the total gate capacitance Cg_total of the FET 100 is Cg + Cbg.

When FET 100 is turned off, the capacitance component of channel 108 is constant. However, the depletion depth for capacitance Cgp increases with the increase of the negative voltage applied to front gate contact 116, and the depletion depth for capacitance Cbex and capacitance Cgp is equal to back gate contact 118. It increases with the increase of the negative voltage applied to it. Thus, the total capacitance Cg_total of the FET 100 decreases with the increase of the negative voltage on the front gate contact 116 or back gate contact 118. In one embodiment, the front gate contact 116 and the back gate contact 118 are electrically connected, so they receive the same reverse voltage. However, the front gate contact 116 and the back gate contact 118 may be separate nodes and may be applied with different reverse voltages.

Changing the reverse voltage applied to the front gate contact 116 and / or back gate contact 118 continuously changes the capacitance of the FET 100 over a range of reverse voltages, as described below. By changing the capacitance of the FET 100, the RF isolation of the drain to the source of the FET can be improved when the device is in the off state, where the off capacitance of the FET 100 crosses the source 112 and the drain 114. This is because the resonance can be eliminated using an inductor (Figs. 3 and 4) connected in parallel. This is because the resonant frequency of the FET 100 continues to change with the reverse voltage applied on the front gate contact 116 and / or back gate contact 118. Depending on the parameters of the FET 100, the capacitance of the FET varies linearly with the reverse voltage applied to the front gate contact 116 and / or back gate contact 118, which spans at least the range of the reverse voltage.

In one embodiment, the FET 100 may be implemented as an RF pass gate, in which case the capacitance of the FET 100 is tuned off by external inductance, as described below. The FET 100, which is an RF pass gate, can be used to create a switch with frequency rejection characteristics beyond those of on-off control. For example, a first signal with a first frequency freq1 passes through a switch (with a minimum attenuation of ~ 3dB) and a second signal with a second frequency freq2 is blocked. After retuning the FET 100, the first signal with the first frequency freq1 may be cut off, and the second signal with the second frequency freq2 is switched (with a minimum attenuation of ~ 3 dB). Can pass through Such RF pass gate applications are useful wherever a tunable narrowband pass gate is needed. This is different under the conditions that the switch operates in on mode, where all frequencies pass with much lower losses (~ 0.5dB).

As another example, FET 100 may be used as a tunable output match element in an RF circuit.

Since the FET 100 is fabricated over the PN junction 126, a relatively large amount of parasitic capacitance occurs. However, the structure of the FET 100 also allows for the availability of the back gate 118. The back gate 118 enables tuning of parasitic capacitances by varying the reverse voltage applied to the back gate contact 118 to achieve a wide tuning range.

2 is a cross-sectional view of a CMOS NFET device that may be used to implement a continuous tunable LC resonator using FETs as a varactor. PFET devices can also be implemented.

The FET 200 includes a substrate 202, in which a p-type well region 204 is formed. The p-type well region 204 may be formed by ion implantation, diffusion, or other techniques known to those skilled in the art.

An n + region 206 that forms the drain of the FET 200 is formed in the p-type well region 204. An n + region 208 forming a source of the FET 200 is formed in the p-type well region 204. The p + region 212 forming the body of the FET 200 is formed in the p-type well region 204. Region 206 will alternatively be referred to as "drain", region 208 will also be referred to as "source", and region 212 will alternatively be referred to as "body".

Depletion layer 214 is formed in p-type well region 204, and inversion layer 216 is formed over depletion layer 214 in p-type well region 204.

An oxide layer 218, also referred to as a "gate oxide", is formed over the inversion layer 216 on the surface of the p-type well region 204. A metal or polysilicon layer 222 is formed over the oxide layer 218 and forms the “gate” of the FET 200.

The capacitance of the gate 222 includes a gate oxide capacitance Cox and a depletion capacitance Cdepl. The change in the bias voltage applied to the body 212 affects the depletion capacitance Cdepl, thus allowing the FET 200 to behave as a varactor.

When the voltage applied to the gate 222 is higher than the threshold voltage of the FET 200, an inversion layer 216 is formed below the gate oxide 218, and the gate oxide capacitance Cox blocks the depletion capacitance Cdepl. And the FET 200 functions normally. In such a situation, the total capacitance change obtained by changing the bias voltage applied to the body 212 from 0V to a negative voltage is minimal.

However, when the voltage applied to the gate 222 is lower than the threshold voltage of the FET 200, the total gate capacitance is a series combination of the gate oxide capacitance Cox and the depletion capacitance Cdepl, and Cox * Cdepl / (Cox + Cdepl) to Cdepl, the tuning range of the capacitance is significant at voltage levels below the threshold voltage. The capacitance Cox is much larger than the capacitance Cdepl, so the total capacitance is approximately equal to the depletion capacitance Cdepl.

As mentioned above, in one embodiment, the FET 200 may also be implemented as an RF pass gate, in which case the capacitance of the FET 200 is tuned off by external inductance.

3 is a schematic diagram illustrating one embodiment of the FET 100 of FIG. 1 implemented as a varactor. Schematic 300 includes a FET 310 that includes a front gate 316, a source 312 and a drain 314. The FET 310 also includes a back gate 318, which in this embodiment is electrically connected to the front gate 316, so that the front gate 316 and the back gate 318 receive the same voltage (Vgate). do. A resistor 322 is connected in series with the front gate 316, and an inductor 324 is coupled in parallel across the source 312 and drain 314. Optionally, capacitor 326 is coupled in parallel across inductor 324. In one embodiment, inductor 324 may have an inductance value of about 7 nanohenrys (nH). Depending on the width of the gate and the operating frequency of the FET 310 (eg, for gate widths less than 800 micrometers (μm) operating at 2 GHz), the capacitor 326 may be omitted. The values of the components largely depend on the physical layout of the circuit 300 and the technique used to manufacture the devices. In response to a change in the reverse voltage applied to the front gate 316 and the back gate 318, and thus a change in the capacitance of the FET 310, the FET 310 is resonantly removed to remove the capacitance of the FET 310 by using the parallel inductor 324. The drain-source (ds) isolation provided by 310 is improved.

The radio frequency (RF) signal applied to the source 312 causes the gate 316 and the back gate 318 to enter a state of “RF floating” due to the relatively large resistance of the resistor 322. The capacitance experienced by inductance 324 varies with the gate or back gate voltage applied, and is the capacitance between source 312 and drain 314. The source-drain capacitance is essentially the parallel sum of the front gate capacitance Cg and the back gate capacitance Cbg.

When analyzing the capacitance experienced by the inductor 324, the back gate capacitance Cbg is the series sum of the drain-back gate capacitance Cdrain-bg and the source-back gate capacitance Csource-bg. The front gate capacitance Cg is a series sum of drain-to-gate capacitance and source-to-gate capacitance.

This causes a condition in which the resonant frequency of the FET 310 varies with the reverse voltage applied to the front gate 316 and / or back gate 318. The reverse bias voltage applied to the front gate 316 changes the width of the front gate control depletion region 132 (FIG. 1), and the reverse bias voltage applied to the back gate 318 is the back gate control depletion region 134. The width of FIG. 1 is changed to change the overall capacitance between the source 312 and the drain 314.

4 is a schematic diagram illustrating an alternative embodiment of the FET 100 of FIG. 1. Schematic 400 includes a FET 410 that includes a front gate 416, a source 412, and a drain 414. The front gate voltage Vfgate is applied to the front gate 416 through the resistor 422. The FET 410 also includes a back gate 418, which is electrically isolated from the front gate 416 in this embodiment. The resistor 422 is connected in series with the front gate 416, with the inductor 424 coupled in parallel across the source 412 and drain 414. Optionally, capacitor 426 is coupled in parallel across inductor 424. The back gate 418 receives the back gate voltage Vbgate through the resistor 428.

In the embodiment illustrated in FIG. 4, a reverse voltage Vfgate may be applied to the front gate 416 regardless of the reverse voltage Vbgate applied to the back gate 418. In response to a change in the reverse voltage applied to the front gate 416 and / or back gate 418, and thus a change in the capacitance of the FET 410, a parallel inductor 424 is used, as described above with respect to FIG. Thus, the isolation provided by the FET 410 is improved by resonantly removing the capacitance of the FET 410. As an example, the ability to apply independent voltage signals to the front gate 416 and back gate 418 creates a four terminal FET switch capable of resonating at two different frequencies as a function of a digital controller (not shown). .

Note that when the FET device is an n-type device, that is, an NFET, a negative front gate or back gate voltage is applied. However, if the FET device is a p-type device such as a PFET, the front gate or back gate voltage will be positive.

5 is a graph 500 illustrating the tuning range of the FET 100 of FIG. 1. The abscissa 502 represents the gate voltage, and the ordinate 504 represents the total gate capacitance Cg_total in femtofarads fF. As shown in FIG. 5, the trajectory 506 is about 2.5: 1 continuous when the reverse voltage applied to the front gate or back gate of the FET 100 of FIG. 1 varies from about -0.5V to about -5.0V. Indicates the tuning range ratio. In the example shown in FIG. 5, the tuning range represents the ratio of capacitance change in the range of the variable applied voltage. In this example, the capacitance varies from about 200 fF to about 500 fF over the gate / back gate voltage range applied. Thus, in this example, the tuning range is 500fF / 200fF = 2.5: 1.

As shown in FIG. 5, a continuous tunable LC resonator using FETs as a varactor has a wide tuning range with a near linear CV response over a specific voltage range, such as, for example, -0.6V to -2.8V. to provide.

FIG. 6 is a graph 600 showing a measurement of frequency versus scattering parameter S21 of the implementation shown in FIG. 3. In the example shown in FIG. 6, the inductor 324 of FIG. 3 has L = 13.2nH, and the FET 310 includes eight elements each having a width of 100 μm, so the net FET width is 800 μm. . The abscissa 602 represents a frequency in gigahertz (GHz), and the ordinate 604 represents a scattering parameter S21 in dB. As shown in FIG. 6, the trajectory 606 is the FET 100 (FIG. 1) when the gate voltage changes in 0.4V steps from about -0.8V (606-1) to about -3.6V (606-8). The resonant frequency of Fr varies from about 1.7 GHz to about 2.3 GHz.

FIG. 7 is a flowchart illustrating operation of one embodiment of a continuously tunable LC resonator using FETs as the varactors of FIGS. 1 and 2. In block 702, a reverse voltage in the range of about −0.4 V to −5.0 V is applied to either the front gate 116 (gate 222 of FIG. 2) and the back gate 118 (body 212 of FIG. 2). Is approved. In block 704, the capacitance of the FET is adjusted according to the applied reverse voltage.

8 is a block diagram illustrating a simplified portable communication device 800 in which one embodiment of a continuous tunable LC resonator using a FET as a varactor may be implemented. In one embodiment, portable communication device 800 may be a portable cellular telephone. Embodiments of a continuous tunable LC resonator using a FET as a varactor may be implemented in any device that requires a tunable LC resonator, which in this example is implemented in portable communication device 800. The portable communication device 800 shown in FIG. 8 is a simple example of a cellular telephone and is intended to illustrate one of many possible applications in which a continuous tunable LC resonator using a FET as a varactor can be implemented. Those skilled in the art will understand the operation of the portable cellular telephone, so implementation details are omitted.

Portable communication device 800 includes a baseband subsystem 810, a transceiver 820, and a front end module (FEM) 830. Although not shown for clarity, transceiver 820 generally includes modulation and upconversion circuitry for preparing baseband information signals for amplification and transmission, and for receiving RF signals and restoring data. Filtering and downconversion circuitry for downconverting to a baseband information signal. Details of the operation of the transceiver 820 are known to those skilled in the art.

The baseband subsystem generally includes a processor 802, memory 814, application software 804, analog circuit elements 806 and digital circuit elements 808, which may be general purpose or special purpose microprocessors. These are coupled via the system bus 812. System bus 812 may include physical and logical connections to combine the aforementioned elements with each other and to enable their interoperability.

Input / output (I / O) element 816 is connected to baseband subsystem 810 via connection 824, and memory element 818 is coupled to baseband subsystem 810 via connection 826. Power source 822 is connected to baseband subsystem 810 via connection 828. I / O element 816 is, for example, a microphone, keypad, speaker, pointing device, user interface control elements, and any that allows a user to provide input commands and receive outputs from portable communication device 800. Other devices or systems.

Memory 818 may be any type of volatile or nonvolatile memory, and in one embodiment may include flash memory. The memory element 818 may be permanently installed in the portable communication device 800 or may be a removable memory element such as a removable memory card.

The power source 822 may be, for example, a battery or other rechargeable power source, or may be an adapter that converts AC power to the exact voltage used by the portable communication device 800. In one embodiment, the power supply may be a battery that provides a nominal voltage output of about 3.6 volts (V). However, the output voltage range of the power supply may range from about 3.0 to 6.0V.

Processor 802 may be any processor that executes application software 804 to control the operation and functionality of portable communication device 800. Memory 814 may be volatile or nonvolatile memory, and in one embodiment may be nonvolatile memory that stores application software 804.

Analog circuit 806 and digital circuit 808 include signal processing, signal conversion, and logic to convert the input signal provided by I / O element 816 into an information signal to be transmitted. Similarly, analog circuit 806 and digital circuit 808 include signal processing, signal conversion, and logic to convert the received signal provided by transceiver 820 into an information signal that includes reconstruction information. Digital circuit 808 may include, for example, a digital signal processor (DSP), an FPGA or any other processing device. Baseband subsystem 810 includes both analog and digital elements and is therefore sometimes referred to as mixed signal circuitry.

In one embodiment, the FEM 830 includes a transmit / receive (T / R) switch 842 and a power amplifier module 848. The T / R switch 842 may be a duplexer, diplexer, or any other physical or logic device or circuit that separates the transmit and receive signals. Depending on the implementation of the portable communication device 800, the T / R switch 842 may be implemented to provide half or full duplex functionality. The transmit signal provided by the transceiver 820 via the connection 836 is directed to the power amplifier module 848. The power amplifier module may include one or more amplification stages and may also include a continuously tunable LC resonator using an FET as a varactor as an input radio frequency (RF) switch.

The output of power amplifier module 848 is provided to antenna 846 via connection 844 after being provided to T / R switch 842 via connection 838.

The signal received by the antennas 846 is provided to the T / R switch 842 via a connection 844, which connects the received signal to a connection 834 for receive signal processing as known in the art. Provided to the transceiver 820 through.

While various embodiments of the invention have been described, it will be apparent to those skilled in the art that many more embodiments and implementations are possible that are within the scope of the invention.

Claims (20)

As a varactor,
A field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), the back gate of the FET sharing an electrical connection with the base of the BJT, and a reverse voltage applied to the back gate of the FET Is a variable that generates a continuously variable capacitance in the channel of the FET. The method of claim 1,
And a reverse voltage applied to the front gate of the FET. The method of claim 2,
The reverse voltage applied to the back gate or to the front gate ranges from -0.4 volts to -5.0 volts. The method of claim 2,
Wherein the continuously variable capacitance is a gate capacitance of the FET. The method of claim 2,
And the front gate of the FET is electrically connected to the back gate of the FET. The method of claim 4, wherein
Said continuously variable capacitance is achieved by a capacitance-voltage response that is substantially linear over at least a predefined voltage range. The method of claim 6,
The varactor is implemented as a radio frequency pass gate. Applying a reverse voltage to a back gate of a field effect transistor (FET) integrated with a bipolar junction transistor (BJT), the back gate of the FET sharing an electrical connection with a base of the BJT, A reverse voltage applied to the back gate creates a continuous variable capacitance in the channel of the FET. The method of claim 8,
Applying a reverse voltage to the front gate of the FET. 10. The method of claim 9,
The reverse voltage applied to the back gate or to the front gate ranges from -0.4 volts to -5.0 volts. 10. The method of claim 9,
The continuous variable capacitance is a gate capacitance of the FET. 10. The method of claim 9,
The front gate of the FET is electrically connected to the back gate of the FET. The method of claim 11,
The continuous variable capacitance is achieved by a capacitance-voltage response that is substantially linear over at least a predefined voltage range. 10. The method of claim 9,
Implementing the FET as a radio frequency pass gate. As FET,
An integrated bipolar junction transistor (BJT) and a field effect transistor (FET), the back gate of the FET shares an electrical connection with the base of the BJT, and either to the back gate of the FET or to the front gate of the FET. The applied reverse voltage produces a continuous variable capacitance in the channel of the FET. 16. The method of claim 15,
The reverse voltage applied to the back gate or to the front gate ranges from -0.4 volts to -5.0 volts. 16. The method of claim 15,
The continuous variable capacitance is a gate capacitance of the FET. 16. The method of claim 15,
The front gate of the FET is electrically connected to the back gate of the FET. 18. The method of claim 17,
The continuous variable capacitance is achieved by a capacitance-voltage response that is substantially linear over at least a predefined voltage range. As a CMOS NFET,
A field effect transistor (FET), the front gate of the FET shares an electrical connection with the body of the FET, and a reverse voltage applied to either the front gate of the FET or the body of the FET A CMOS NFET creating a continuous variable capacitance in a channel, wherein the CMOS NFET is implemented as a radio frequency pass gate.

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