CN102742016B - Make field-effect transistors as the continuously adjustable inductor capacitance resonance machine of variodenser - Google Patents

Abstract

A varactor comprising: a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), wherein the back gate of the FET shares an electrical connection with the base of the BJT, and wherein an inversion applied to the back gate of the FET Applying the voltage creates a continuously variable capacitance in the channel of the FET.

Description

Continuously adjustable LC resonator using FETs as varactors

Background technique

Varactor diodes, commonly referred to as varactors, are a class of PN junction diodes that have high junction capacitance when reverse biased. This capacitance is variable and a function of the voltage applied at its terminals. Such devices with variable or adjustable capacitance are commonly used in inductive (L) capacitive (C) (LC) resonant circuits used as tuned circuits, for impedance matching or as isolated circuits.

One technique used to fabricate semiconductor devices is the fusion of gallium arsenide (GaAs) heterojunction bipolar transistor (HBT)-field-effect transistor (FET) technology, where the FET is connected to a metal with a depletion mode (d-mode) similar to Semiconductor Field Effect Transistor (MESFET) is a dedicated device for HBT integration of characteristics, where MESFET is a dedicated FET. This integration technology is often referred to as "BiFET", but alternative nomenclature and integration technologies exist to combine HBTs and FETs on GaAs.

Other semiconductor technologies can also be used to create FETs. One example is Complementary Metal Oxide Semiconductor (CMOS) technology, which integrates both n-type and p-type e-mode MOSFETs onto the same silicon substrate. Regardless of the technology used to fabricate the FET, the FET can be controlled to exhibit variable capacitance when the device is off. Therefore, it is desirable to have a way of using FETs as varactors. If a varactor can be realized such that it has a wide tuning range with a continuously tunable characteristic, it can be used in tunable LC circuits, tunable RF matching networks and any other application requiring electrically tunable capacitance.

Contents of the invention

Embodiments of the invention include a varactor comprising: a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), wherein the back gate of the FET shares an electrical connection with the base of the BJT, and wherein applying A reverse voltage to the FET's back gate creates a continuously variable capacitance in the FET's channel.

Other embodiments may also be provided. Other systems, methods, features and advantages of the invention will be, or will become, apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the following claims.

Description of drawings

The invention will be better understood with reference to the following figures. The components in the figures are not necessarily to scale, illustrative instead of the principles of the invention. Furthermore, in the drawings, like reference numerals designate corresponding parts throughout the different views.

Figure 1 is a cross-sectional view of a FET in a BiFET process, which can be used as a varactor.

Figure 2 is a cross-sectional view of a CMOS NFET device that can be used as a varactor.

FIG. 3 is a schematic diagram illustrating an embodiment of the FET of FIG. 1 implemented as a varactor.

FIG. 4 is a schematic diagram illustrating an alternative embodiment of the circuit of FIG. 3 .

FIG. 5 is a graphical illustration showing the tuning range of the FET of FIG. 1 .

FIG. 6 is a graph illustration showing the measurement of the scattering parameter S21 versus frequency for the implementation shown in FIG. 3 .

FIG. 7 is a flowchart describing a method of operation of a circuit embodiment using the FET of FIG. 1 or 2 as a varactor.

Figure 8 is a block diagram illustrating a simplified portable communication device.

detailed description

A reverse voltage applied across the PN junction of a semiconductor device creates a region where little current and electrons or holes exist. This region is called the depletion region. In a FET device, this region may be formed in the "channel" of the FET. There are essentially no carriers, it acts as the dielectric of the capacitor, and the capacitance varies with voltage.

Examples of construction of BiFET devices are shown in US Patent No. 5,250,826 and US Patent No. 6,906,359, both of which are incorporated herein by reference.

Regardless of the method of construction, one of the characteristics exhibited by FET devices (in particular, FET devices formed in BiFET processes or other processes) is that when the device is off, the channel region exhibits a capacitance that can be changed by changing the capacitance applied to the FET. The reverse voltage of the “gate” and/or “back gate” changes. In this way, the FET acts like a varactor.

Continuously tunable LC resonators using FETs as varactors can be fabricated using a variety of materials. In an embodiment using the technique described in Figure 1, a continuously tunable LC resonator using FETs as varactors is fabricated using elements from groups III and V to form materials in various binary, ternary and quaternary combinations, And in an embodiment, fabricated using an indium gallium phosphide (InGaP)/gallium arsenide (GaAs) material system.

In an embodiment, complementary metal-oxide-semiconductor (CMOS) technology can be used to fabricate NFETs or PFETs, which can also be used to implement continuously tunable LC resonators using FETs as varactors. When bipolar devices are incorporated into a CMOS process, the technology is commonly known as BiCMOS. In an alternative embodiment, silicon junction field effect transistor (JFET) technology can be used to realize a continuously tunable LC resonator using FETs as varactors. JFET technology can also be merged with silicon bipolar technology.

Continuously tunable LC resonators using FETs as varactors can be used in applications including but not limited to input radio frequency (RF) switching in power amplifier modules. Such switches are also known as "RF pass gates" and can exhibit narrow frequency bands. However, a continuously tunable LC resonator using a FET as a varactor can be used in any other circuit using a tunable LC resonant circuit.

FIG. 1 is a cross-sectional view of a FET 100 in a BiFET process that can be used as a varactor. Although FETs that can be used as varactors can be fabricated using other technologies, one of which is described below, BiFET technology is attractive for this application because it allows the FET to exhibit a wide tuning range. The epitaxial layer structure shown in FIG. 1 forms a FET 100 that incorporates a MESFET into the emitter layer of a HBT, wherein, in FIG. 1 , some layers showing the HBT portion of the device are omitted for simplicity. Only the FET part of the BiFET process is described here, which is relevant to the description of continuously tunable LC resonators using FETs as varactors.

FET 100 uses a portion of base 102 formed using a layer of gallium arsenide (GaAs), on which emitter 104 is formed using a layer of gallium arsenide (GaAs) and indium gallium phosphide (InGaP). A PN junction 126 is formed at the interface of the base 102 and the emitter 104 . Although not shown for clarity, emitter 104 generally includes a lightly doped emitter layer, a lightly doped emitter protective layer, and a heavily doped emitter contact layer, as is known in the art. Back gate contact 118 is formed from ohmic metal deposited on the exposed face of base 102, generally as shown. Back gate contact 118 is also understood to include a back gate.

Channel 108 is formed below front gate contact 116 by a layer of indium gallium phosphide (InGaP) forming emitter 104 and gallium arsenide (GaAs) layer 106 . Although shown as including layers 104 and 106 , channel 108 is created by depletion regions 132 and 134 formed in portions of layers 104 and 106 under certain electrical conditions to be described below. A front gate contact 116 having Schottky barrier properties is located on layer 106 . Source 112 and drain 114 are located on “mesas” on layer 106 . Front gate contact 116 is also understood to include a front gate.

The layers of the epitaxial structure shown in Figure 1 are the basic layers of the device. Other and/or additional layers may be incorporated into device 100 depending on the process and fabrication techniques.

A source contact 122 is formed on the source 112 and a drain contact 124 is formed on the drain 114 . The voltage applied to the front gate contact 116 affects the front gate controlled depletion region 132 and the voltage applied to the back gate contact 118 affects the back gate controlled depletion region 134 . Although front gate contact 116 is shown in FIG. 1 as being electrically connected to back gate contact 118 , this is not the case for all embodiments. In an alternate embodiment, the front gate contact 116 may be electrically isolated from the back gate contact 118 so as to form a four terminal FET. Such a device is schematically shown and described in FIG. 4 . Depending on the embodiment, the voltage applied to the front gate contact 116 may be the same or different than the voltage applied to the back gate contact 118 . Additionally, the reverse voltage may be applied only to the front gate contact 116 or the back gate contact 118 . According to an embodiment, when the FET is off, a reverse voltage applied to the front gate contact 116 and/or the back gate contact 118 changes the capacitance of the channel 108 . The capacitance of the channel appears as capacitance between source 112 and drain 114 .

In an embodiment, the back gate contact 118 may be electrically coupled to the front gate contact 116 such that the same reverse voltage is applied to the front gate contact 116 and the back gate contact 118 .

The total gate capacitance of a FET is determined by the number of individual capacitors. For example, the front gate capacitance Cg includes the area component Cga of the Schottky gate capacitance plus the peripheral component Cgp of the Schottky gate capacitance. The capacitance Cbg of the back gate includes the base-emitter junction capacitance Cbex in the region outside the gate plus the base-emitter junction capacitance Cbei below the front gate. Thus, in an embodiment where back gate contact 118 and front gate contact 116 are electrically connected together as shown in FIG. 3 , the total gate capacitance Cg_total of FET 100 is equal to Cg plus Cbg.

When FET 100 is off, the capacitive component of channel 108 is constant. However, the depletion depth of capacitance Cgp increases with increasing negative voltage applied to front gate contact 116 , and the depletion depth of capacitance Cbex and capacitance Cgp increases with increasing negative voltage applied to back gate contact 118 . Therefore, the total capacitance Cg_total of FET 100 decreases with increasing negative voltage on front gate contact 116 or back gate contact 118 . In an embodiment, the front gate contact 116 and the back gate contact 118 are electrically connected such that they receive the same reverse voltage. However, the front gate contact 116 and the back gate contact 118 may be separate nodes and apply different reverse voltages.

As will be described below, varying the reverse voltage applied to the front gate contact 116 and/or the back gate contact 118 continuously changes the capacitance of the FET 100 over a range of reverse voltages. By varying the capacitance of FET 100, the drain-to-source RF isolation of the FET when the device is off can be improved because the off-off of FET 100 can be tuned using an inductor connected in parallel across source 112 and drain 114 (FIGS. 3 and 4). capacitance. This is because the resonant frequency of FET 100 varies continuously with a reverse voltage applied to front gate contact 116 and/or back gate contact 118 . Depending on the parameters of the FET 100 , the capacitance of the FET varies linearly with the reverse voltage applied to the front gate contact 116 and/or the back gate contact 118 at least in the range of reverse voltages.

In an embodiment, as will be described below, the FET 100 may be implemented as an RF pass gate, wherein the capacitance of the FET 100 is tuned out by an external inductance. As an RF pass gate, FET 100 can be used to create a switch with frequency rejection characteristics beyond on-off control. For example, a first signal with a first frequency freq1 passes through the switch (with minimum attenuation ~3dB), and a second signal with a second frequency freq2 is blocked. After retuning the FET 100, the first signal with the first frequency freq1 can be blocked and the second signal with the second frequency freq2 can pass through the switch (with a minimum attenuation of ~3dB). Such RF pass gate applications are useful where a tunable narrowband pass gate is required. This is the opposite of what happens when the switch is operated in on mode, where all frequencies are passed with very low loss (~0.5dB).

As another example, FET 100 may be used as a tunable output matching element in an RF circuit.

Because FET 100 is fabricated on PN junction 126, a relatively large amount of parasitic capacitance results. However, the structure of FET 100 also allows for the availability of back gate 118 . The back gate 118 allows tuning of this parasitic capacitance by varying the reverse voltage applied to the back gate contact 118 to achieve a wide tuning range.

Figure 2 is a cross-sectional view of a CMOS NFET device that can be used to implement a continuously tunable LC resonator using FETs as varactors. PFET devices can also be implemented.

FET 200 includes a p-substrate 202 in which a p-type well region 204 is formed. P-type well region 204 may be formed by ion implantation, diffusion, or other techniques known to those skilled in the art.

An n+ region 206 forming the drain of FET 200 is formed in p-type well region 204 . An n+ region 208 forming the source of FET 200 is formed in p-type well region 204 . A p+ region 212 forming the body of FET 200 is formed in p-type well region 212 . Region 206 will alternatively be referred to as a "drain," region 208 will alternatively be referred to as a "source," and region 212 will alternatively be referred to as a "body."

A depletion layer 214 is formed in the p-type well region 204 , and an inversion layer 216 is formed in the p-type well region 204 on the depletion layer 214 .

An oxide layer 218 , also referred to as “gate oxide” is formed on the surface of p-type well region 204 , on inversion layer 216 . Metal or polysilicon layer 222 is formed on oxide layer 218 and forms the “gate” of FET 200 .

The capacitance of the gate 222 includes a gate oxide capacitance Cox and a depletion capacitance Cdepl. Changing the bias voltage applied to body 212 affects depletion capacitance Cdepl, thus allowing FET 200 to act as a varactor.

If the voltage applied to gate 222 is higher than the threshold voltage of FET 200 , inversion layer 216 forms under gate oxide 218 and gate oxide capacitance Cox shields depletion capacitance Cdepl and FET 200 operates normally. In this case, the change in total capacitance obtained by changing the bias voltage applied to the body 212 from 0V to a negative voltage is minimal.

However, if the voltage applied to the gate 222 is below the threshold voltage of the FET 200, the total gate capacitance is the series combination of the gate oxide capacitance Cox and the depletion capacitance Cdepl, assuming Cox*Ddepl/(Cox+Cdepl)~Cdepl , and the tuning range of the capacitance is significant at voltage levels below the threshold voltage. The capacitance Cox is significantly higher than the capacitance Cdepl; therefore the total capacitance is approximately equal to the depletion capacitance Cdepl.

As mentioned above, in an embodiment, FET 200 may also be implemented as an RF pass gate, wherein the capacitance of FET 200 is trimmed by an external inductor.

FIG. 3 is a schematic diagram illustrating an embodiment of the FET 100 of FIG. 1 implemented as a varactor. Schematic 300 includes FET 310 including front gate 316 , source 312 and drain 314 . FET 310 also includes a back gate 318 which, in this embodiment, is electrically connected to front gate 316 such that front gate 316 and back gate 318 receive the same voltage Vgate. Resistor 322 is connected in series with front gate 316 and inductor 324 is coupled in parallel across source 312 and drain 314 . Optionally, capacitor 326 is coupled in parallel across inductor 324 . In an embodiment, inductor 324 may have an inductance value of approximately 7 nanohenries (nH). Depending on the width of the gate of FET 310 and the frequency of operation, capacitor 326 may be omitted (eg, for a gate width of less than 800 microns (μm) operating at 2 GHz). The values of the various components are highly dependent on the physical layout of circuit 300 and the techniques used to fabricate the device. The drain-to-source (d-s) isolation provided by FET 310 is improved by tuning the capacitance of FET 310 out using inductor 324 in parallel by varying the capacitance of FET 310 in response to changing the reverse voltage applied to front gate 316 and back gate 318 .

Due to the relatively high resistance of resistor 322 , a radio frequency (RF) signal applied to source 312 causes gate 316 and backgate 318 to enter a state known as “RF float”. The capacitance experienced by inductor 324 varies with the applied gate or backgate voltage and is the capacitance across source 312 and drain 314 . The source-drain capacitance is basically the parallel sum of the front gate capacitance Cg and the back gate capacitance Cbg.

When analyzing the capacitance experienced by the inductor 324, the back gate capacitance Cbg is the series sum of the drain to back gate capacitance Cdrain-bg and the source to back gate capacitance Csource-bg. The front-gate capacitance Cg is the series sum of the drain-to-gate capacitance Cdrain-to-gate and the source-to-gate capacitance Csource-to-gate.

This leads to a situation where the resonant frequency of FET 310 changes with reverse voltage applied to front gate 316 and/or back gate 318 . A reverse bias voltage applied to front gate 316 modulates the width of front gate controlled depletion region 132 ( FIG. 1 ), and a reverse bias voltage applied to back gate 318 modulates the width of back gate controlled depletion region 134 ( FIG. 1) in order to change the overall capacitance between the source 312 and the drain 314 .

FIG. 4 is a schematic diagram illustrating an alternate embodiment of the FET 100 of FIG. 1 . Schematic 400 includes FET 410 including front gate 416 , source 412 and drain 414 . The front gate voltage Vfgate is applied to the front gate 416 through a resistor 422 . FET 410 also includes a back gate 418 which, in this embodiment, is electrically separated from front gate 416 . Resistor 422 is connected in series with front gate 416 and inductor 424 is coupled in parallel across source 412 and drain 414 . Optionally, capacitor 426 is coupled in parallel across inductor 424 . The back gate 418 receives a back gate voltage Vbgate through a resistor 428 .

In the embodiment shown in FIG. 4 , the reverse voltage Vfgate may be applied to the front gate 416 independently of the reverse voltage Vbgate applied to the back gate 418 . As described with reference to FIG. 3 , the isolation provided by FET 410 is improved by tuning out the capacitance of FET 410 using parallel inductor 424 in accordance with varying the reverse voltage applied to front gate 416 and/or back gate 418, and thus varying the capacitance of FET 410. . As an example, the ability to apply independent voltage signals to the front gate 416 and back gate 418 results in a four terminal FET switch capable of resonating at two different frequencies as a function of a digital controller (not shown).

It should be noted that if the FET device is an n-type device, ie, an NFET, then a negative front gate back gate voltage is applied. However, if the FET device is a p-type device, such as a PFET, the front or back gate voltage should be positive.

FIG. 5 is a graph 500 illustrating the tuning range of FET 100 of FIG. 1 . The abscissa 502 represents the gate voltage, and the ordinate 504 represents the total gate capacitance Cg_total in femtofarads (fF). As shown in FIG. 5 , trace 506 illustrates a continuous tuning range ratio of approximately 2.5:1 as the reverse voltage applied to the front gate or back gate of FET 100 of FIG. 1 changes from approximately -0.5V to approximately -5.0V. In the example shown in FIG. 5, the tuning range refers to the rate at which the capacitance changes within the range of changing the applied voltage. In this example, the capacitance changes from about 200fF to about 500fF over the range of applied gate/backgate voltages. So, in this example, the tuning range is 500fF/200fF=2.5:1.

As shown in Fig. 5, a continuously tunable LC resonator using FETs as varactors provides a wide tuning range with near-linear C-V response at least over a specific voltage range (such as, for example, −0.6 V to −2.8 V).

FIG. 6 is a graph illustration 600 showing measurements of the scattering parameter S21 versus frequency for the implementation shown in FIG. 3 . In the example shown in Fig. 6, the inductor 324 of Fig. 3 has L = 13.2nH, and the FET 310 has 8 elements, each with a width of 100 μm, resulting in a net FET width of 800 μm. The abscissa 602 represents the frequency in gigahertz (GHz), and the ordinate 604 represents the scattering parameter S21 in dB. As shown in FIG. 6 , trace 606 illustrates the manner in which FET 100 (Fig. 1) The resonant frequency Fr changes from about 1.7GHz to 2.3GHz.

7 is a flowchart describing the operation of an embodiment of a continuously tunable LC resonator using the FET of FIG. 1 or 2 as a varactor. At block 702 , a reverse voltage in the range of approximately -0.4V to -5.0V is applied to either one of the front gate 116 (gate 222 of FIG. 2 ) and the back gate 118 (body 212 of FIG. 2 ). At block 704, the capacitance of the FET is adjusted based on the applied reverse voltage.

Figure 8 is a block diagram illustrating a simplified portable communication device 800 in which an embodiment of a continuously tunable LC resonator using FETs as varactors can be implemented. In an embodiment, the portable communication device 800 may be a portable cellular telephone. Embodiments of a continuously tunable LC resonator using FETs as varactors can be implemented in any device where a tunable LC resonator is desired, and in this example, portable communication device 800 . The portable communication device 800 shown in Figure 8 is intended to be a simplified example of a cellular telephone and illustrates one of many possible applications in which a continuously tunable LC resonator using FETs as varactors can be implemented. One of ordinary skill in the art will understand the operation of the portable cellular telephone, so implementation details are omitted.

The portable communication device 800 includes a baseband subsystem 810 , a transceiver 820 and a front end module (FEM) 830 . Although not shown for clarity, transceiver 820 typically includes modulation and upconversion circuitry for preparing a baseband information signal for amplification and transmission, and includes circuitry for receiving and downconverting RF signals to baseband information signals to recover data. filtering and down-conversion circuits. The details of the operation of transceiver 820 are known to those skilled in the art.

The baseband subsystem generally includes a processor 802 (which may be a general or special purpose microprocessor), memory 814 , application software 804 , analog circuit elements 806 and digital circuit elements 808 , coupled by a system bus 812 . System bus 812 may include physical and logical connections to couple the above-described elements together and allow their interoperability.

Input/output (I/O) element 816 is connected to base subsystem 810 through connection 824 , memory element 818 is coupled to base subsystem 810 through connection 826 , and power supply 822 is connected to base subsystem 810 through connection 828 . I/O elements 816 may include, for example, microphones, keypads, speakers, pointing devices, user interface controls, and any other device or system that allows a user to provide input commands and receive output from portable communication device 800 .

Memory 818 may be any type of volatile or non-volatile memory and, in an embodiment, may include flash memory. Memory element 818 may be permanently installed in portable communication device 800, or may be a removable memory element, such as a removable memory card.

Power source 822 may be, for example, a battery or other rechargeable power source, or may be an adapter that converts AC power to a DC voltage used by portable communication device 800 . In an embodiment, the power source may be a battery providing a nominal voltage output of approximately 3.6 volts (V). However, the output voltage range of the power supply may range from about 3.0 to 6.0V.

Processor 802 may be any processor that executes application software 804 to control the operation and functions of portable communication device 800 . Memory 814 may be volatile or non-volatile memory, and in an embodiment, may be non-volatile memory that stores application software 804 .

Analog circuitry 806 and digital circuitry 808 include signal processing, signal conversion, and logic to convert the input signal provided by I/O element 816 into an information signal to be transmitted. Similarly, analog circuitry 806 and digital circuitry 808 include signal processing, signal conversion and logic to convert the received signal provided by transceiver 820 into an information signal containing recovered information. Digital circuitry 808 may include, for example, a digital signal processor (DSP), FPGA, or any other processing device. Because baseband subsystem 810 includes both analog and digital components, it is sometimes referred to as a mixed-signal circuit.

In an embodiment, FEM 830 includes a transmit/receive (T/R) switch 842 and a power amplifier module 848 . The T/R switch 842 may be a duplexer, a diplexer, or any other physical or logical device or circuit that separates transmit and receive signals. Depending on the implementation of the portable communication device 800, the T/R switch 842 may be implemented to provide either half-duplex or full-duplex functionality. The transmit signal provided by transceiver 820 is directed to power amplification module 848 via connection 836 . The power amplification module may include one or more amplifier stages and may also include a continuously tunable LC resonator using FETs as varactors as input device (RF) switches.

The output of power amplifier module 848 is provided to T/R switch 842 via connection 838 and then to antenna 846 via connection 844 .

Signals received by antenna 846 are provided via connection 844 to T/R switch 842 which provides received signals via connection 834 to transceiver 820 for received signal processing as is known in the art.

While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of this invention.

Claims (23)

1. a variodenser, comprising:

With the field-effect transistor FET integrated at least partially of bipolar junction transistor BJT, the backgate of FET is shared with the base stage of BJT and is directly electrically connected, and the reverse voltage being applied to the backgate of FET produces continuous variable electric capacity in the raceway groove of FET.

2. variodenser as claimed in claim 1, also comprises the reverse voltage of the front grid being applied to FET.

3. variodenser as claimed in claim 2, is wherein applied to the scope of the reverse voltage of backgate or front grid from-0.4 to-5.0V.

4. variodenser as claimed in claim 2, wherein said continuous variable electric capacity is the grid capacitance of FET.

5. variodenser as claimed in claim 4, wherein at least in predetermined voltage range, utilizes linear capacitance-voltage response to realize described continuous variable electric capacity.

6. variodenser as claimed in claim 5, wherein said variodenser is embodied as radio frequency and passes through door.

7. variodenser as claimed in claim 2, wherein the front grid of FET are electrically connected to the backgate of FET.

8. a tuning methods, comprising:

Apply the backgate of reverse voltage to the field-effect transistor FET integrated with bipolar junction transistor BJT, the backgate of FET is shared with the base stage of BJT and is directly electrically connected, and the reverse voltage being applied to the backgate of FET produces continuous variable electric capacity in the raceway groove of FET.

9. tuning methods as claimed in claim 8, also comprises and applies the front grid of reverse voltage to FET.

10. tuning methods as claimed in claim 9, is wherein applied to the scope of the reverse voltage of backgate or front grid from-0.4 to-5.0V.

11. tuning methods as claimed in claim 9, wherein said continuous variable electric capacity is the grid capacitance of FET.

12. tuning methods as claimed in claim 11, wherein at least in predetermined voltage range, utilize linear capacitance-voltage response to realize described continuous variable electric capacity.

13. tuning methods as claimed in claim 9, wherein the front grid of FET are electrically connected to the backgate of FET.

14. tuning methods as claimed in claim 9, also comprise and FET is embodied as radio frequency passes through door.

15. 1 kinds of FET, comprising:

Integrated bipolar junction transistor BJT and the backgate of field-effect transistor FET, FET are shared with the base stage of BJT and are directly electrically connected, and the reverse voltage being applied to one of the backgate of FET or the front grid of FET produces continuous variable electric capacity in the raceway groove of FET.

16. FET as claimed in claim 15, are wherein applied to the scope of the reverse voltage of backgate or front grid from-0.4 to-5.0V.

17. FET as claimed in claim 15, wherein said continuous variable electric capacity is the grid capacitance of FET.

18. FET as claimed in claim 17, wherein at least in predetermined voltage range, utilize linear capacitance-voltage response to realize described continuous variable electric capacity.

19. FET as claimed in claim 15, wherein the front grid of FET are electrically connected to the backgate of FET.

20. 1 kinds of radio frequency RF power amplifier PA modules, comprising:

One or more amplifier stage, is configured to amplification RF signal; And

There is the input RF switch of variodenser, described variodenser comprises the field-effect transistor FET integrated at least partially with bipolar junction transistor BJT, the backgate of FET is shared with the base stage of BJT and is directly electrically connected, and makes the reverse voltage of the backgate being applied to FET produce continuous variable electric capacity in the raceway groove of FET.

21. 1 kinds of portable communication devices, comprising:

Transceiver, is configured to generate RF signal;

Antenna, with transceiver communication with the transmission of convenient RF signal;

Power amplifier PA module, to be arranged between transceiver and antenna and to be configured to amplification RF signal, described PA module has variodenser, described variodenser comprises the field-effect transistor FET integrated at least partially with bipolar junction transistor BJT, the backgate of FET is shared with the base stage of BJT and is directly electrically connected, and makes the reverse voltage of the backgate being applied to FET produce continuous variable electric capacity in the raceway groove of FET.

22. portable communication devices as claimed in claim 21, wherein said portable communication device comprises cellular phone.

23. 1 kinds of methods for the manufacture of variodenser, described method comprises:

Form bipolar junction transistor BJT; And

Form field-effect transistor FET so that integrated at least partially with BJT, the backgate of FET is directly electrically connected with the base stage of BJT is shared, makes the reverse voltage of the backgate being applied to FET produce continuous variable electric capacity in the raceway groove of FET.