KR20120079371A - Flash memory device and wordline voltage generating method thereof - Google Patents

Abstract

PURPOSE: A flash memory device and a method for generating a voltage of a word line thereof are provided to reduce program time by controlling each section with a positive word line voltage and a negative word line voltage with the optimum time. CONSTITUTION: A program voltage is generated by a high voltage generator. A first negative verification voltage(Vvfy1) is generated by pumping negative charges for the first pumping time. If a second negative verification voltage higher than the first negative verification voltage is generated after the first negative verification voltage is generated, the first negative verification voltage is discharged for the first discharge time. A second verification voltage(Vvfy2) is generated by pumping the negative charge for the second pumping time after the first discharge time. One or more positive program verification voltages corresponding to one or more data states are generated through a low voltage generator.

Description

FLASH MEMORY DEVICE AND WORDLINE VOLTAGE GENERATING METHOD THEREOF}

The present invention relates to a semiconductor memory device, and more particularly to a flash memory device and a method of generating a word line voltage thereof.

The semiconductor memory device may be largely classified into a volatile semiconductor memory device and a non-volatile semiconductor memory device. Volatile semiconductor memory devices are fast to read and write, but the stored contents are lost when the power supply is cut off. On the other hand, nonvolatile semiconductor memory devices retain their contents even when their power supplies are interrupted. Therefore, the nonvolatile semiconductor memory device is used to store contents to be preserved regardless of whether or not power is supplied.

Non-volatile semiconductor memory devices include mask read-only memory (MROM), programmable read-only memory (PROM), erasable and programmable ROM (EROM), and electrically Electrically erasable programmable read-only memory (EEPROM).

A typical example of a nonvolatile memory device is a flash memory device. Flash memory refers to computers, mobile phones, PDAs, digital cameras, camcorders, voice recorders, MP3 players, personal digital assistants (PDAs), handheld PCs, game machines, fax machines, scanners, printers, etc. It is widely used as a voice and video data storage medium of information devices such as).

In recent years, as the high integration demand for memory devices increases, multi-bit memory devices storing multiple bits in one memory cell have become popular.

An object of the present invention is to provide a flash memory device and a method for generating a word line voltage thereof capable of controlling each section for generating a negative word line voltage and a positive word line voltage with an optimized time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flash memory device capable of converting a negative word line voltage and a positive word line voltage level at a high speed and reducing the time required for a program and a method of generating the word line voltage thereof. .

Another object of the present invention is to provide a flash memory device capable of efficiently performing a read operation and a verify operation on a data state distributed in a negative voltage region and a positive voltage region, and a method of generating a word line voltage thereof. .

In order to achieve the above object, a word line voltage generation method of a flash memory according to the present invention includes: generating a program voltage through a high voltage generator; Generating a plurality of negative program verify voltages corresponding to the plurality of negative data states through the negative voltage generator; And generating at least one positive program verify voltage corresponding to the at least one data state via a low voltage generator, wherein generating the plurality of negative program verify voltages comprises: negative charge pumping for a first pumping time Generating a first negative verify voltage; If a second negative verify voltage higher than the first negative verify voltage is generated after the first negative verify voltage is generated, discharging the first negative verify voltage for a first discharge time; And performing the negative charge pumping during the second pumping time after the first discharge time to generate the second negative verification voltage.

In this embodiment, the discharge result may be higher than the second negative verify voltage and equal to or lower than the ground voltage.

In this embodiment, when a third negative verify voltage lower than the first negative verify voltage is generated after the first negative verify voltage is generated, negative charge pumping is performed during the third pumping time without the discharge operation. And performing the third negative verification voltage.

In this embodiment, when the at least one or more positive program verify voltages are generated after the second negative verify voltage is generated, the second negative verify voltage is a second discharge that is less than the first discharge time. The method may further include discharging for a time.

In this embodiment, the first and second discharge times may have a larger value as the difference in the verification voltage between the discharge intervals in which the discharge operation is performed is greater.

In order to achieve the above object, a word line voltage generation method of a flash memory according to the present invention includes generating a plurality of negative read voltages corresponding to a plurality of negative data states through a negative voltage generator; And generating at least one positive read voltage corresponding to at least one positive data state through a low voltage generator, wherein generating the plurality of negative read voltages comprises: generating a first negative read voltage; Discharging the first negative read voltage for a predetermined discharge time when a second negative read voltage is generated that is higher than the first negative read voltage after being generated; And performing a negative charge pumping during the first pumping time after the predetermined discharge time to generate the second negative read voltage.

In this embodiment, the discharge result may be higher than the second negative read voltage and equal to or lower than the ground voltage.

In this embodiment, when a third negative read voltage lower than the first negative read voltage is generated after the first negative verify voltage is generated, negative charge pumping is performed during the second pumping time without the discharge operation. And performing the third negative read voltage.

In this embodiment, the discharge time may have a larger value as the difference between two negative read voltages between the discharge periods in which the discharge operation is performed is greater.

In order to achieve the above object, a word line voltage generation method of a flash memory according to the present invention includes: generating a first negative voltage by performing negative charge pumping during a first pumping time; Converting a target negative voltage from the first negative voltage to a second negative voltage in response to control of a control logic; If the second negative voltage is higher than the first negative voltage, discharging the first negative voltage through a discharge unit for a predetermined discharge time in response to control of the control logic; An oscillator generating an oscillation signal in response to the control of the control logic after the discharge time; And in response to the oscillation signal, the negative voltage charge pump performs negative charge pumping for a second pumping time to generate the second negative voltage.

In this embodiment, the discharging of the output path of the negative voltage charge pump through the discharge unit may be finished after the discharge time has elapsed from when the first negative voltage starts to be discharged.

In this embodiment, the generating of the oscillation signal by the oscillator in response to the control of the control logic may be performed after the discharge time elapses from when the first negative voltage starts to be discharged.

In accordance with one aspect of the present invention, a flash memory device includes a flash memory cell array including a plurality of flash memory cells connected to a plurality of word lines; A voltage generator generating a plurality of word line voltages to be applied to the word lines; And a control logic for controlling a voltage generation operation of the voltage generator, wherein the voltage generator is configured to continuously generate a second negative voltage higher than the first negative voltage after the first negative voltage is generated. The negative voltage generator may generate the second negative voltage by discharging the first negative voltage for a predetermined discharge time in response to the control of the control logic and then performing negative charge pumping during the first pumping time.

In this embodiment, the discharge result may be higher than the second negative voltage and equal to or lower than the ground voltage.

In this embodiment, the negative voltage generator performs negative charge pumping for a second pumping time without the discharge operation when a third negative voltage lower than the first negative voltage is generated after the first negative voltage is generated. To generate the third negative voltage.

In this embodiment, the negative voltage generator includes an oscillator for generating an oscillation signal in response to the control of the control logic; A negative voltage charge pump performing negative charge pumping in response to the oscillation signal; A discharge unit for discharging the output of the negative voltage charge pump; And converting a target negative voltage from the first negative voltage to the second negative voltage according to the control of the control logic when the second negative voltage is generated, and comparing the negative charge pumping result of the negative voltage charge pump with the target negative voltage. The oscillator may generate the oscillation signal during the first pumping time in response to the comparison result of the voltage detector or the control of the control logic.

In this embodiment, the control logic may control the oscillator to generate the oscillation signal after the discharge time has elapsed.

In accordance with one aspect of the present invention, a data storage device includes: a plurality of flash memories connected to a plurality of channels; And a controller for controlling read, write, or erase operations of each flash memory through a corresponding channel, wherein each flash memory includes a flash memory cell array including a plurality of flash memory cells connected to a plurality of word lines. ; A voltage generator generating a plurality of word line voltages to be applied to the word lines; And a control logic for controlling a voltage generation operation of the voltage generator, wherein the voltage generator is configured to continuously generate a second negative voltage higher than the first negative voltage after the first negative voltage is generated. The negative voltage generator may generate the second negative voltage by discharging the first negative voltage for a predetermined discharge time and then performing negative charge pumping for a predetermined pumping time in response to the control of the control logic.

In this embodiment, the data storage device may be any one of a semiconductor disk, a PCMCIA card, a compact flash card, a smart media card, a memory stick, a multimedia card, an SD card, and a universal flash memory device.

In order to achieve the above object, a computing system according to the present invention includes a host; And a data storage device for recording data in response to a write command input from the host, the data storage device comprising: a plurality of flash memories connected to a plurality of channels; And a controller controlling read, write, or erase operations of each flash memory through a corresponding channel, wherein each flash memory includes a flash memory cell array including a plurality of flash memory cells connected to a plurality of word lines. ; A voltage generator generating a plurality of word line voltages to be applied to the word lines; And a control logic for controlling a voltage generation operation of the voltage generator, wherein the voltage generator is configured to continuously generate a second negative voltage higher than the first negative voltage after the first negative voltage is generated. The negative voltage generator may generate the second negative voltage by discharging the first negative voltage for a predetermined discharge time and then performing negative charge pumping for a predetermined pumping time in response to the control of the control logic.

According to the present invention as described above, it is possible to control each section for generating a negative word line voltage and a positive word line voltage at an optimized time. Therefore, it is possible to convert the negative word line voltage and the positive word line voltage levels at high speed, and to reduce the time required for the program. In addition, it is possible to efficiently perform a read operation and a verify operation on data states distributed in a negative voltage region and a positive voltage region.

1 is a view showing a schematic configuration of a flash memory according to the present invention.
FIG. 2 is a diagram illustrating a structure of the memory cell array illustrated in FIG. 1.
3 and 4 exemplarily illustrate threshold voltage distributions that may be formed in each cell of a 3-bit multi-bit flash memory by a program operation.
FIG. 5 is a diagram illustrating a threshold voltage distribution when a portion of a threshold voltage of a memory cell is distributed in a negative voltage region, and examples of corresponding verification and read voltages. FIG.
FIG. 6 is a diagram exemplarily illustrating levels and generating methods of first to seventh verification voltages corresponding to respective program states illustrated in FIG. 5.
7 is a block diagram illustrating a configuration of a negative voltage generator according to the present invention.
8 is a flowchart illustrating an example of a negative voltage generation method according to the present invention.
9 and 10 are views illustrating a negative voltage generation process according to the negative voltage generation method of the present invention.
FIG. 11 is a diagram illustrating a threshold voltage distribution when a part of a threshold voltage of a memory cell is distributed in a negative voltage region, and another example of verification voltages and read voltages corresponding thereto.
FIG. 12 is a diagram illustrating levels and generation methods of first to seventh pre-verify voltages and first to seventh main verify voltages corresponding to respective program states illustrated in FIG. 11.
13 is a diagram illustrating a structure of a memory cell array according to an embodiment of the present invention.
14 is a diagram illustrating the structure of a memory cell array in accordance with another embodiment of the present invention.
FIG. 15 is a diagram illustrating a configuration of a storage device having a flash memory device and a user device including the same according to the present invention.
16 is a block diagram illustrating a data storage device in accordance with another embodiment of the inventive concept.
17 is a block diagram illustrating a data storage device in accordance with another embodiment of the inventive concept.
18 is a view showing a schematic configuration of a flash memory device and a computing system including the same according to the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Identical components will be referred to using the same reference numerals. Similar components will be quoted using similar reference numerals. The circuit configuration of the flash memory device according to the present invention to be described below and the read operation performed by the present invention are just examples, and various changes and modifications can be made without departing from the technical spirit of the present invention.

1 is a view showing a schematic configuration of a flash memory 100 according to the present invention. 2 is a diagram illustrating a structure of the memory cell array 110 illustrated in FIG. 1.

Referring to FIG. 1, the flash memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 130, and a read / write circuit. 140, a voltage generating unit 170, a voltage selection switch 180, and a control logic 190.

The memory cell array 110 may be connected to the row decoder 120 through word lines WL and may be connected to the write read circuit 130 through the bit lines BL. The memory cell array 110 includes memory cells arranged in a plurality of rows (or word lines) and a plurality of columns (or bit lines). A plurality of memory cells included in the memory cell array 110 may constitute a plurality of memory blocks, and a configuration of one memory block is illustrated in FIG. 2. Memory cells included in each memory block may have a NAND string structure as shown in FIG. 2, and may have a NOR structure (not shown).

Referring to FIG. 2, each memory block may include a plurality of cell strings (or NAND strings) 111 connected to bit lines BL0 to BLm−1, respectively. Each cell string 111 may include at least one string select transistor SST, a plurality of memory cells MC0 to MCn-1, and at least one ground select transistor GST. In each cell string 111, the drain of the string select transistor SST is connected to the corresponding bit line, and the source of the ground select transistor GST is connected to the common source line CSL. The memory cells MC0 to MCn-1 are connected in series between the source of the string select transistor SST and the drain of the ground select transistor GST.

Each memory cell MC0 to MCn-1 may be configured to store data information of N bits (N is greater than or equal to 1) per cell. The memory cells MC0 to MCn-1 may inject charge into the charge storage layer to store respective bit information. In example embodiments, the memory cells MC0 to MCn-1 may use a conductive floating gate that is blocked by an insulating layer as a charge storage layer. In another embodiment, the memory cells MC0 to MCn-1 may use an insulating film such as Si 3 N 4, Al 2 O 3, HfAlO, HfSiO, or the like as the charge storage layer instead of the conventional conductive floating gate. A flash memory having a structure using an insulating film such as Si 3 N 4, Al 2 O 3, HfAlO, HfSiO, or the like as a charge storage layer is also referred to as a charge trap flash (“CTF”) memory. The operating characteristics of the flash memory 100 of the present invention to be described below are applicable to both a flash memory device in which the charge storage layer is formed of a conductive floating gate, as well as a charge trap type flash in which the charge storage layer is formed of an insulating film.

In addition, the memory cell array 110 of the present invention may be configured as any one of a stack flash structure in which a plurality of cell arrays are stacked in multiple layers, a flash structure without source-drain, a pin-type flash structure, and a three-dimensional flash structure. Can be.

2 illustrates a case in which the flash memory 100 of the present invention is configured as a NAND-type flash memory. However, this is only an embodiment to which the present invention is applied, and operation characteristics of the flash memory 100 of the present invention to be described below are not only NAND flash memory, but also NOR-type Flash memory, at least two. The present invention can be applied to a hybrid flash memory in which more than one kind of memory cells are mixed, or a flash memory in which a controller is embedded in a memory chip.

As shown in FIG. 2, the control gates of the memory cells arranged in the same row are commonly connected to the corresponding word lines WL0-WLn-1. The string select transistor SST is controlled by a voltage applied through the string select line SSL, and the ground select transistor GST is controlled by a voltage applied through the ground select line GSL. The memory cells MC0 to MCn-1 are controlled by voltages applied through corresponding word lines WL0 to WLn-1. Memory cells connected to each of the word lines WL0 to WLn−1 may store data corresponding to one page, a subpage smaller than one page, or a plurality of pages. A read operation for reading data stored in the NAND flash memory and a program operation for storing data in the NAND flash memory may be performed in units of one or a plurality of pages, and in some cases, may be performed in units of subpages. have. An erase operation for erasing data stored in the NAND flash memory may be performed in a block unit composed of a plurality of pages.

Referring back to FIG. 1, the control logic 190 controls all operations related to program, erase, and read operations of the flash memory 100. The voltage generator 170 may generate word line voltages to be supplied to respective word lines and a voltage to be supplied to a bulk (eg, a well region) in which memory cells are formed, according to an operation mode. The voltage generation operation of the voltage generator 170 may be performed by the control of the control logic 190.

The voltage generator 170 may include a high voltage generator 171, a low voltage generator 173, and a negative voltage generator 175. The high voltage level generator 171 may generate the high voltages required to drive the flash memory 100 under the control of the control logic 190. The positive high voltages generated from the high voltage level generator 171 may be used as the program voltage Vpgm, the pass voltage Vpass, and the like during the program operation.

The low voltage generator 173 may generate the low voltages required to drive the flash memory 100 under the control of the control logic 190. The positive low voltages generated from the low voltage level generator 173 may be used as a read voltage Vrd, a verify voltage Vvfy, a decoupling voltage, a blocking voltage, and the like during a program or read operation. In one embodiment, the positive pumping operation of the low voltage generator 173 may be performed after the command input is completed, and the read voltage Vrd, the verify voltage Vvfy, the decoupling voltage, and the blocking voltage generated by the low voltage generator 173 may be performed. The level of the back can be adjusted by distributing the positive pumping result using a plurality of resistors. In this case, a trim code may be used as a scheme for outputting a positive word line voltage at a desired level.

The negative voltage generator 175 may generate negative voltages for driving the flash memory 100 under the control of the control logic 190. The negative voltages generated from the negative voltage generator 175 may be used as a read voltage Vrd, a verify voltage Vvfy, a decoupling voltage, a blocking voltage, or the like during a program or read operation. The negative voltages generated from the negative voltage generator 175 may be supplied to a bulk (eg, a well region) in which memory cells are formed. Hereinafter, in the present invention, the voltages applied to the word lines for driving the flash memory 100 will be referred to as word line voltages.

As will be described in detail below, the negative voltage generator 175 of the present invention continuously generates a plurality of negative voltages under the control of the control logic 190, and controls each section for generating the negative voltage at an optimized time. Can be. As a result, the level of the negative voltage generated from the negative voltage generator 175 can be converted at high speed, and the time required for the program operation to which the negative voltage generator 175 is applied can be minimized.

In particular, when the negative voltage generator 175 generates the second negative voltage at a level higher than the first negative voltage after the first negative voltage is generated, the negative voltage generator 175 is output according to the control of the control logic 190 ( That is, after discharging the first negative voltage at a high speed for a predetermined time (or after discharging the constant voltage level), the negative charge pumping is performed to generate the second negative voltage. In this case, the sections in which discharge is performed and the sections in which negative charge pumping is performed may be set to optimized times, respectively. In addition, when the negative voltage generator 175 generates the second negative voltage having a level lower than the first negative voltage after generating the first negative voltage, the negative voltage generator 175 may be configured to perform negative charge pumping to generate the second negative voltage without a discharge operation. have. In this case, the section in which negative charge pumping is performed may be set to an optimized time. In an exemplary embodiment, the pumping time set to generate the second negative voltage at a level higher than the first negative voltage and the second negative voltage at a level lower than the first negative voltage may be set to the same value, It may be set to different values.

In another embodiment, the negative charge pumping operation involving the discharge operation and the negative charge pumping operation without the discharge operation are selectively performed according to the level of the negative voltage continuously generated by the negative voltage generator 175 according to the present invention. Each section (eg, discharge section, negative voltage pumping section, etc.) for generating a negative voltage may be set to an optimal time. In one embodiment, for the negative charge pumping operation that does not involve the discharge operation, the generation order of the negative voltage may be adjusted according to the level of the negative voltage to be generated, or the voltage generation order may be adjusted to alternately generate the negative voltage and the positive voltage. have. According to such a configuration, the delay time required for the voltage transition from the first negative voltage to the second negative voltage can be minimized, and a negative voltage of a desired level can be generated in a short time. The negative voltage generation characteristic of the present invention described above is also applicable to generating a word line voltage having a positive voltage level.

Outputs of the high voltage generator 171 and the low voltage generator 173 may be transmitted to the voltage selection switch 180. The output of the negative voltage generator 175 may be delivered to the voltage selection switch 180 and the row decoder 120.

The row decoder 120 is connected between the voltage selection circuit 180 and the memory cell array 110. The row decoder 120 is configured to operate under the control of the control logic 190. The row decoder 120 receives the row address X-ADDR from the outside and decodes the received row address X-ADDR. The row decoder 120 selects word lines WL based on the decoding result of the row address X-ADDR. The row decoder 120 performs a function of transferring an output (eg, a voltage) of the voltage selection switch 180 to selected word lines and unselected word lines.

The voltage selection switch 180 may be connected to the voltage generator 170, the row decoder 120, and the control logic 190. The voltage selection switch 180 may select one of the voltages output from the voltage generator 170 in response to the control of the control logic 190. The voltage selected by the voltage selection switch 180 may be provided to the corresponding word line WL through the row decoder 120.

In an exemplary embodiment, the voltage selection switch 180 may use a transistor as a switching element or a transfer gate. For example, the voltage selection switch 180 may use a field effect transistor (FET) as a switching element or a transmission gate.

When the output of the negative voltage generator 175 is selected by the control of the control logic 190, the voltage selection switch 180 may transfer the negative voltage generated from the negative voltage generator 175 to the row decoder 120. In order to transfer the negative voltage to the row decoder 120 through the field effect transistor, the well region of the voltage selector switch 180 and the well region of the row decoder 120 are caused by the negative voltage generated from the negative voltage generator 175. Can be biased.

When the negative voltage generator 175 is deactivated, the negative voltage generator 175 may generate a ground voltage in response to the control of the control logic 190. When a high voltage or a low voltage is transferred to the word lines WL through the voltage select switch 180 and the row decoder 120, the well regions of the voltage select switch 180 and the row decoder 120 may be biased to the ground voltage. Can be.

The column decoder 130 is connected to the write read circuit 140. The column decoder 130 is configured to operate in response to the control of the control logic 190. The column decoder 130 receives the column address Y-ADDR from the outside and decodes the received column address Y-ADDR. The decoding result of the column address Y-ADDR is provided to the write read circuit 140.

The write read circuit 140 is controlled by the control logic 190 and operates as a sense amplifier or as a write driver depending on the operation mode. For example, in the case of a verify / normal read operation, the write read circuit 140 operates as a sense amplifier for reading data from the memory cell array 110. In the normal read operation, the data DATA read through the column select circuit 140 is output to the outside of the flash memory 100 (for example, a memory controller or a host). In contrast, the data read through the column select circuit 140 during the verify read operation is provided to a pass / fail verify circuit (not shown) in the flash memory 100 to be used to determine whether the memory cells are successfully programmed. Can be.

In the case of a program operation, the write read circuit 140 operates as a write driver that drives the bit lines BL0 to BLm-1 according to data to be stored in the memory cell array 110. The write read circuit 140 receives data DATA to be used for the memory cell array 110 from a buffer (not shown) during a program operation, and according to the input data DATA, the bit lines BL0 to BLm-1. ). To this end, the write read circuit 140 may include a plurality of page buffers PB respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs). A plurality of latches may be provided in each page buffer PB. The plurality of latches may perform an operation of latching data sensed from the page buffer PB and / or latching data to be programmed.

3 and 4 exemplarily illustrate threshold voltage distributions that may be formed in each cell of a 3-bit multi-bit flash memory by a program operation.

3, the program shall be to the k bits in one memory cell, either one of the threshold voltage of the 2 ^k pieces (for example, ²³ = 8) are formed in the memory cell. Due to the difference in minute electrical characteristics between the memory cells, threshold voltages of the programmed memory cells may form a threshold voltage distribution of a predetermined range so as to correspond to the respective program states ST0 to ST7.

In an ideal case, the threshold voltage distributions corresponding to the respective program states ST0 to ST7 may be spaced apart from the adjacent threshold voltage distribution by a predetermined voltage interval to provide a read margin (see FIG. 3). Solid line). To this end, the threshold voltages of the respective memory cells may be distributed in voltage regions of predetermined program verify voltages corresponding to the program states ST0 to ST7.

As the number of bits stored per cell increases, the number of program states and the number of threshold voltage distributions corresponding to each program state increase. Therefore, in order to provide a sufficient read margin and the number of threshold voltage distributions corresponding to the number of bits stored per cell, a threshold voltage window in which the threshold voltages of the memory cells are distributed must be sufficiently secured. However, since the voltage window in which the threshold voltage distributions can be placed is limited to a certain range (see D1 in FIG. 3), as k increases, the distance between adjacent threshold voltage distributions decreases.

In a practical implementation of a multi-bit flash memory, the threshold voltage distribution of each data state can be transformed into a non-ideal form (see dotted line in FIG. 3). This phenomenon will become more serious as the number of bits of data stored in one memory cell increases. In addition, this phenomenon will be aggravated by various causes such as charge loss, time lapse, temperature increase, coupling when programming adjacent cells, reading adjacent cells, cell defects, and the like. The deformation of the threshold voltage distribution as described above may cause a read error and the like, and various methods have been proposed to prevent such a problem. As one of them, as shown in FIG. 4, a method of distributing a part of threshold voltages of a memory cell in a negative voltage region is proposed.

According to the configuration in which a part of the threshold voltages of the memory cells are distributed in the negative voltage region, the distribution range D2 of the total threshold voltages of the memory cells becomes wider than the distribution range D1 of the total threshold voltages shown in FIG. 3. (Ie, D2> D1). The wider distribution range D2 of the overall threshold voltage can secure a wider margin between the plurality of program states. As the distribution range D2 of the total threshold voltage is extended to the negative voltage region, the distribution range of the total threshold voltage becomes wider. In addition, as the distribution range D2 of the entire threshold voltage is extended to the negative voltage region, the level of the negative voltage generated by the negative voltage generator 175 becomes more diverse, and a scheme for generating various levels of negative voltage at high speed. This is desperately required.

Accordingly, the flash memory device 100 of the present invention provides a method of controlling each section for generating a negative voltage at an optimized time.

In the following, a method of continuously generating a negative verify voltage among negative voltages will be exemplarily described. However, this is only an example to which the present invention is applied, and the negative voltage generation method according to the present invention is not limited to a specific type of negative voltage (for example, a verification voltage and a read voltage), and various kinds of negative voltages. (E.g., various kinds of negative word line voltages) and various kinds of positive word line voltages. Therefore, according to the word line voltage generation method of the present invention, it is possible to convert the negative word line voltage and the positive word line voltage level at high speed, and to reduce the time required for the program. In addition, it is possible to efficiently perform a read operation and a verify operation on data states distributed in a negative voltage region and a positive voltage region.

FIG. 5 is a diagram illustrating a threshold voltage distribution when a portion of a threshold voltage of a memory cell is distributed in a negative voltage region, and examples of corresponding verification and read voltages. FIG.

In FIG. 5, the horizontal axis represents threshold voltages of the memory cells, and the vertical axis represents the number of memory cells. 5 exemplarily illustrates a case where memory cells have an erase state ST0 and first to seventh program states ST1 to ST7. However, this is only a configuration for explaining the present invention, and the distribution and number of logic states ST0 to ST7 that the memory cells can have is not limited to a specific form and can be variously configured.

Since the nonvolatile memory 100 cannot overwrite, the memory cells must be in the erase state ST0 before the program operation can be performed. Therefore, in order for the memory cells to have the threshold voltage distribution shown in FIG. 5, the threshold voltages of the memory cells must be erased so as to have a threshold voltage distribution lower than the erase verify voltage Vvfye (that is, ST0) before the program is executed. . After the threshold voltages of the memory cells are in the erase state ST0, the memory cells may be programmed to any one of the erase state ST0 and the first to seventh program states ST1 to ST7.

The flash memory 100 may be programmed by an incremental step pulse programming (ISPP) scheme to accurately control threshold voltage distribution of the memory cells. A cycle in which a memory cell is programmed is composed of a plurality of program loops, and each program loop may be divided into a program section P and a program verify section V. FIG.

In the program period P, memory cells may be programmed under a given bias condition. In the ISPP programming method, as the program loops are repeated, the level of the program voltage applied during the program period P may be increased step by step. The program voltage may consist of a positive high voltage. In an exemplary embodiment, the program voltage may be generated from the high voltage generator 171 under the control of the control logic 190.

In the program verifying period V, whether a memory cell is programmed to a desired threshold voltage (for example, ST0 to ST7) may be verified through a verify read operation. The above program loops are repeatedly performed within a predetermined number of times until all the memory cells are programmed. The first to seventh verification voltages Vvfy1 to Vvfy7 corresponding to the respective program states ST0 to ST7 may be applied to the verify read operation. The verify read operation is substantially the same as the normal read operation except that the read data is not output to the outside.

After the program operation for the memory cells is completed, the data of the respective program states ST0 to ST7 are read through the normal read operation. In the normal read operation, a plurality of read voltages Vrd1 to Vrd7 illustrated in FIG. 5 may be applied to distinguish each program state ST0 to ST7.

In an exemplary embodiment, the first and second read voltages Vrd1 and Vrd2 may be configured as negative voltages. Among the negative voltages, the second read voltage Vrd2 may be configured to have a negative voltage higher than the first read voltage Vrd1. The third to seventh read voltages Vrd3 to Vrd7 are positive voltages and may be configured as positive low voltages having a level higher than that of the second read voltage Vrd2. The third to seventh read voltages Vrd3 to Vrd7 may be generated from the low voltage generator 173 under the control of the control logic 190. The first and second read voltages Vrd1 and Vrd2 may both be generated from the negative voltage generator 175 under the control of the control logic 190.

In the threshold voltage distribution illustrated in FIG. 5, the negative voltage generator 175 generates the second read voltage Vrd2 immediately after the first read voltage Vrd1 is generated under the control of the control logic 190. Or after the second read voltage Vrd2 is generated, to generate the first read voltage Vrd1. The generation order of the read voltages applied when the continuous read operation is performed may be variously configured according to the control of the control logic 190.

For example, when the second read voltage Vrd2 is generated immediately after the first read voltage Vrd1 is generated, in the present invention, to reduce the time required for the change of the negative voltage level, the negative voltage generator 175 After discharging the output (that is, the first read voltage Vrd1) at a high speed for a predetermined time, negative charge pumping may be performed to generate the second read voltage Vrd2. According to the configuration of the present invention as described above, the negative voltage conversion speed from the low negative voltage level to the high negative voltage level can be improved.

For example, when the first read voltage Vrd1 is generated immediately after the second read voltage Vrd2 is generated, the output of the negative voltage generator 175 (that is, the second read voltage Vrd2) is generated in the present invention. The operation of discharging)) may be omitted, and negative charge pumping may be immediately performed to generate the first read voltage Vrd1. According to the configuration of the present invention as described above, the discharge operation can be selectively performed according to the levels of the negative read voltages of different levels that are continuously generated. Therefore, the voltage generation rate for the negative voltages of different levels can be improved.

On the other hand, the present invention has a configuration that controls each section (eg, discharge section, pumping section) for generating a negative read voltage and a positive read voltage at an optimized time. The generation characteristic of the read voltage as described above may be applied not only to the normal read operation but also to the verify read operation to be described below. In addition, the read voltage and verify voltage generation method according to the present invention may be applied to not only the read voltage and the verify voltage but also various kinds of word line voltages.

FIG. 6 is a diagram illustrating levels and generation methods of the first to seventh verification voltages Vvfy1 to Vvfy7 corresponding to the respective program states ST0 to ST7 illustrated in FIG. 5. FIG. 6 is a view illustrating levels and generation methods of the verification voltages Vvfy1 to Vvfy7 according to a one step verify scheme.

In the one-step verification scheme, one verify read operation may be performed for each program state ST0 to ST7 during the program verification interval V. FIG. In an exemplary embodiment, the first and second verify voltages Vvfy1 and Vvfy2 applied to the program verify of the first and second program states ST1 and ST2 may be configured with a negative voltage, and the second verify The voltage Vvfy2 may be configured as a negative voltage at a level higher than the first verification voltage Vvfy1. The third to seventh verification voltages Vvfy3 to Vvfy7 applied to the program verification of the third to seventh program states ST3 to ST7 may be configured with low voltages having different levels. The third to seventh verification voltages Vvfy3 to Vvfy7 may be generated from the low voltage generator 173 under the control of the control logic 190. Both the first and second verify voltages Vvfy1 and Vvfy2 may be generated from the negative voltage generator 175 under the control of the control logic 190.

In the one-step verification scheme, the negative voltage generator 175 should generate the second verification voltage Vvfy2 immediately after the first verification voltage Vvfy1 is generated. After the second verify voltage Vvfy2 is generated, the low voltage generator 173 should immediately generate the third to seventh verify voltages Vvfy3 to Vvfy7.

In the present invention, in order to reduce the time required to generate the second verification voltage Vvfy2 after the first verification voltage Vvfy1 is generated, the output of the negative voltage generator 175 is discharged at a high speed for a predetermined time. In addition, a negative charge pumping may be performed to generate the second verification voltage Vvfy2. In addition, in order to reduce the time required to generate the third to seventh verification voltages Vvfy3 to Vvfy7 after the second verification voltage Vvfy2 is generated, the output of the negative voltage generator 175 may be rapidly speeded up for a predetermined time. After the discharge, the low voltage generator 173 generates the third verification voltage Vvfy3. After the third verify voltage Vvfy3 is generated, the fourth to seventh verify voltages Vvfy4 to Vvfy7 may be sequentially generated in the low voltage generator 173 without a separate discharge operation.

In particular, in the present invention, in order to improve the efficiency of continuous negative voltage generation, after the period 1 in which the discharge operation is performed after the first verification voltage Vvfy1 is generated and after the second verification voltage Vvfy2 is generated, The periods 2 in which the discharge operation is performed may be controlled by setting the predetermined predetermined reference times Ref DT (for example, t2_d and t3_d). As a result, the predetermined reference time t2_d before generating the second verify voltage Vvfy2 without having to compare the output level of the first verify voltage Vvfy1 and the level of the discharge result of the first verify voltage Vvfy1. The first verification voltage Vvfy1 can be controlled to be discharged.

In an exemplary embodiment, the reference times t2_d and t3_d set in the discharge sections 1 and 2 may be set based on a voltage difference between adjacent verification voltages having the discharge sections 1 and 2 interposed therebetween. . For example, when the voltage difference between the first verify voltage Vvfy1 and the second verify voltage Vvfy2 is greater than the voltage difference between the second verify voltage Vvfy2 and the third verify voltage Vvfy3, the first verify. The reference time t2_d set in the section 1 for discharging the voltage Vvfy1 may be set larger than the reference time t3_d set in the section 2 in which the second verification voltage Vvfy2 is discharged.

The control method of the present invention, which sets each discharge section to an optimized predetermined reference time value, can be applied to not only the discharge section but also the section in which negative charge pumping is performed. In an exemplary embodiment, all of the sections in which negative charge pumping is performed may be set to the same reference time (Ref PT) value or may be set to different values. Each negative charge pumping section and reference time values (Ref DT, Ref PT) to be set in each discharge section can be set using values obtained by the manufacturer by experiment. The set reference time values Ref DT and Ref PT may be configured to vary within a predetermined range based on the number of times of program / erase, temperature, etc. of the flash memory.

According to the configuration of the present invention, each section for the generation of the continuous negative verify voltage and positive verify voltage can be controlled at an optimized time, so that the program verify speed can be further improved.

7 is a block diagram illustrating a configuration of a negative voltage generator 175 according to the present invention.

Referring to FIG. 7, the negative voltage generator 175 may include an oscillator 1751, a negative voltage charge pump 1753, a discharge unit 1575, and a voltage detector 1959.

The control logic 190 (see FIG. 1) may control the oscillation signal generation operation of the oscillator 1751 according to the order and level of the negative voltage generation required for the erase, program, and read operations performed in the flash memory. The oscillation signal generation of the oscillator 1751 may be controlled by the activation signal EN generated from the control logic 190. The oscillator 1751 may be activated by an activation signal EN generated from the control logic 190 or by a voltage detection result of the voltage detector 1959 to generate an oscillation signal. In an exemplary embodiment, the control logic 190 may generate an activation signal EN when the negative voltage generator 175 starts to operate for the first time to activate the oscillator 1751. The control logic 190 may activate the oscillator 1751 by generating an activation signal EN when a new level of negative voltage is generated (or when the level of the negative voltage is generated). For example, in the case of generating a negative voltage of a level higher than the negative voltage previously generated, the negative charge pumping result of the negative voltage charge pump 1753 is discharged for a predetermined reference time Re DT and then the activation signal EN ) Can be activated to activate the oscillator 1701. When a negative voltage having a lower level than a previously generated negative voltage is generated, the oscillator 1751 may be activated by immediately generating an activation signal EN without a discharge operation. The period in which the oscillator 1751 is activated to generate the oscillation signal, or the time when the activation signal EN is generated, is controlled by the control logic 190 based on the reference time Ref PT set in each negative voltage pumping period. Can be controlled.

The negative voltage charge pump 1753 may generate a negative voltage NV by performing a negative charge pumping operation in response to the oscillation signal generated from the oscillator 1751. The negative voltage NV generated from the negative voltage charge pump 1753 is provided to the output terminal. The negative voltage NV may be discharged through the discharge unit 1575 for a predetermined time Ref DT. The negative voltage NV generated from the negative voltage charge pump 1753 is discharged through the discharge unit 1575 under the control of the control logic 190.

The control logic 190 may control the operation of the discharge unit 1575 according to the order and level of negative voltage generation required for the erase, program, and read operations performed in the flash memory. The discharge unit 1575 may be configured as a field effect transistor (FET). The discharge operation of the discharge unit 1575 may be controlled by the discharge signal DS generated from the control logic 190.

For example, the negative voltage charge pump 1753 starts to generate a negative voltage for the first time, or the negative voltage charge pump 1753 is continuous with the first negative voltage and a second negative voltage equal to or lower than the first negative voltage. If so, the control logic 190 deactivates the discharge signal DS, and in response, the discharge unit 1575 does not discharge the negative charge pumping result of the negative voltage charge pump 1753. Alternatively, after the negative voltage charge pump 1753 generates the first negative voltage (eg, the first verification voltage Vvfy1 of FIG. 6), the second negative voltage (eg, higher than the first negative voltage) (eg, When generating the second verification voltage Vvfy2 of FIG. 6, the control logic 190 may control the first negative voltage to activate the discharge signal DS for a predetermined reference time Ref DT. . In this case, the discharge unit 1575 discharges the first negative voltage for a predetermined reference time Ref DT in response to the activated discharge signal DS. Then, after the predetermined reference time Ref DT, the discharge signal DS is deactivated, and the discharge unit 1575 is deactivated in response to the deactivated discharge signal DS. According to this operation, the negative charge pumping result of the negative voltage charge pump 1753 can be discharged at a high speed through the discharge unit 1575 for a predetermined time.

The discharge unit 1575 may be configured to discharge the negative voltage NV generated from the negative voltage charge pump 1753 within a short time. In one embodiment, the result discharged by the discharge unit 1575 may be configured to have a level higher than the target negative voltage (TNV1, TNV2, ...) (for example, the second verification voltage (Vvfy2)) level. have. In another embodiment, the result discharged by the discharge unit 1575 may be configured to have a level higher than the target negative voltage levels TNV1, TNV2,..., And the same as or lower than the ground level. The level of the voltage discharged by the discharge unit 1575 may be configured in various ways without being limited to a specific form.

The voltage detector 1959 detects the level of the negative voltage NV output through the output terminal and compares the detected negative voltage with the target negative voltages TNV1, TNV2,... Then, the voltage detector 1759 outputs the result of comparing the detected negative voltage with the target negative voltages TNV1, TNV2,... To the oscillator 1751 as a voltage detection result. The oscillator 1751 generates an oscillation signal in response to the voltage detection result of the voltage detector 1759 or the activation signal EN generated from the control logic 190. The target negative voltages TNV1, TNV2,... Used for the voltage comparison of the voltage detector 1959 may be controlled according to the order and level of negative voltage generation required by the erase, program, and read operations performed in the flash memory. 190 may be set or provided.

If the section in which the oscillator 1751 generates or activates the oscillation signal is controlled only by the reference time Ref PT set in each negative voltage pumping section, the level of the previously generated negative verify voltage is discharged. There is no need to compare the levels of negative verify voltages. Therefore, the configuration of the voltage detector 1759 in the negative voltage generator 175 can be omitted. Therefore, the control method and circuit configuration of negative charge pumping can be simplified, and efficient negative charge pumping can be performed within an optimized time.

In FIG. 7, the discharge unit 1575 and the voltage detector 1759 are illustrated separately from each other, but the discharge unit 1575 may be formed together with the voltage detector 1859.

The negative voltage NV (for example, the first and second verification voltages Vvfy1 and Vvfy 2) output through the output terminal is connected to the voltage switch circuit 180 and the row decoder 120 shown in FIG. 1. It can be applied to a word line. The negative voltage NV applied to the word line may be used as a verify voltage or a read voltage, and may be used as a decoupling voltage or a blocking voltage to prevent coupling between the selected word line and adjacent word lines during a program operation. May be In addition, the negative voltage NV output through the output terminal may be applied to the well region.

The negative voltage generator 175 of the present invention described above can generate a plurality of negative voltages continuously under the control of the control logic 190, and each section for generating the negative voltage can be controlled at an optimized time. have. As a result, the level of the negative voltage generated from the negative voltage generator 175 can be converted at high speed, and the time required for the program operation to which the negative voltage generator 175 is applied can be minimized. In particular, when continuously generating a negative voltage of a higher level than the previously generated negative voltage, the negative voltage generator 175 of the present invention discharges the previously generated negative voltage at a high speed for a predetermined time (or constant After discharging the voltage level), negative voltage is pumped to generate the desired level of negative voltage. As a result, it is possible to minimize the delay time required for voltage transition to a higher level of negative voltage than previously generated negative voltage, and to generate a desired level of negative voltage in a short time.

The configuration of the negative voltage generator 175 shown in FIG. 7 corresponds to an embodiment to which the present invention is applied. Therefore, the configuration of the negative voltage generator 175 is not limited to a specific form and can be changed and modified in various forms. For example, although not shown in FIG. 7, the output terminal of the negative voltage generator 175 of the present invention may further include a regulator for regulating the level of the negative voltage output, and various types of additional circuits may be further provided. Can be.

8 is a flowchart illustrating an example of a negative voltage generation method according to the present invention. 9 and 10 exemplarily illustrate a negative voltage generating process according to the negative voltage generating method of the present invention. 9 and 10 exemplarily illustrate a process of generating the first and second verification voltages Vvfy1 and Vvfy2 illustrated in FIGS. 5 and 6. However, the negative voltages shown in FIGS. 9 and 10 are merely examples to which the present invention is applied, and the types and voltage levels of the negative voltages that may be generated in the present invention are not limited to a specific form and are variously configured. It is possible.

Referring to FIG. 8, the negative voltage generation method of the present invention may first determine whether negative voltages are continuously generated (S1000). Whether the negative voltage is to be continuously generated may be determined by the control logic 190 that controls the program, erase, and read operations of the flash memory 100.

As a result of the determination in step S1000, when no negative voltage is continuously generated, the flow proceeds to step S1400 to perform negative charge pumping (step S1400). When the negative voltages are not continuously generated, for example, only one level of negative voltages may be generated, or when different levels of negative voltages are discontinuously generated. The negative voltage generated discontinuously may include negative read voltages Vrd1 and Vrd2 illustrated in FIG. 5.

Subsequently, in step S1500, it is determined whether the time at which the negative charge pumping is performed is greater than or equal to the predetermined reference time Ref PT. As a result of the determination in step S1500, when the time at which the negative charge pumping is performed is less than the predetermined reference time Ref PT, the negative charge pumping operation of the step S1400 is continued until the predetermined reference time Ref PT. As a result of the determination in step S1500, when the time when the negative charge pumping is performed is greater than or equal to the predetermined reference time Re PT, the negative charge pumping operation is stopped (step S1600).

As a result of the determination in step S1000, when the negative voltage is continuously generated, it is determined whether the target negative voltage is higher than the previous target negative voltage corresponding to the negative voltage generated immediately before (S1100). When the negative voltage is continuously generated, for example, the second verification voltage Vvfy2 may be generated immediately after the first verification voltage Vvfy1 is generated, as illustrated in FIG. 6. .

As a result of the determination in operation S1100, when the target negative voltage is higher than the previous target negative voltage, the output of the negative voltage generator 175 (that is, the first verification voltage Vvfy1) is determined by the discharge unit 1575 for a predetermined reference time. (Ref DT) may be discharged (step S1200). The discharge on the output of the negative voltage generator 175 may be controlled by controlling the discharge operation of the discharge unit 1575 by the discharge control signal DS generated from the control logic 190. Looking at the discharge operation performed in step S1200 in detail as follows.

9 and 10, the previous target negative voltage TNV1 may correspond to the first verify voltage Vvfy1, and the new target negative voltage TNV2 may correspond to the second verify voltage Vvfy2. Here, the second verify voltage Vvfy2 may be configured to have a negative voltage higher than the first verify voltage Vvfy1. The target negative voltages TNV1 and TNV2 are set to the negative voltage generator 175 by the control logic 190 in accordance with the order and level of negative voltage generation required for the erase, program, and read operations performed in the flash memory. Can be provided.

When the second verify voltage Vvfy2 is continuously generated after the first verify voltage Vvfy1 is generated, the control logic 190 sets a target negative voltage to be set or provided to the negative voltage generator 175 from TNV1 to TNV2. Will change to In this case, the output of the negative voltage generator 175 may be discharged for a predetermined reference time Ref DT through the discharge unit 1575 under the control of the control logic 190.

If the output of the negative voltage generator 175 is not discharged for a predetermined reference time Ref DT, the word line to which the first verify voltage Vvfy1 is applied is charged to the first verify voltage Vvfy1 level like a capacitor. It will stay intact. In this case, the discharge operation as well as the negative charge pumping operation when the negative voltage transitions from the first verification voltage Vvfy1 to the second verification voltage Vvfy2 will not be performed. Because the negative charge pumping operation is performed when generating a negative voltage of a lower level than the present time, the negative charge is generated when a second verifying voltage Vvfy2 that is a negative voltage of a level higher than the previously generated first verifying voltage Vvfy1 is generated. Instead of pumping it will have a gentle transition characteristic as shown in the graphs (dotted lines) shown in FIGS. 9 and 10. In this case, the transition from the first verify voltage Vvfy1 to the second verify voltage Vvfy2 will take a long time.

In contrast, in the present invention, when the negative voltage transitions from the first verify voltage Vvfy1 to the second verify voltage Vvfy2, the voltage accumulated in the word line by the first verify voltage Vvfy1 is gradually discharged. Without causing the output of the negative voltage generator 175 to be discharged at a high speed through the discharge portion 1575 for a predetermined time (see solid lines A, A 'and A "in FIGS. 9 and 10). A negative voltage transition can be performed at a speed.

During the discharge operation, the output of the negative voltage generator 175 may discharge only a partial level between the target negative voltage TNV2 and the ground voltage, or may be completely discharged to the ground level. The magnitudes DELTA V1, DELTA V2, and DELTA V3 at which the output of the negative voltage generator 175 is discharged are adjustable by adjusting the reference times t2_d, t2_d ', and t2_d " The magnitudes DELTA V1, DELTA V2, and DELTA V3 at which the output of 175 is discharged can be variously set within a range of voltages higher than the target negative voltage TNV2 and equal to or lower than the ground level. The larger the voltage difference between adjacent negative voltages having a discharge period is set to have a longer discharge time, and the smaller the voltage difference between adjacent negative voltages having a discharge period is set to have a short discharge time.

Referring back to FIG. 8, in operation 1300, it may be determined whether the discharge time is greater than or equal to the predetermined reference time Ref DT. As a result of the determination in operation 1300, when the discharge time is less than the predetermined reference time Ref DT, the discharge operation is continued until the predetermined reference time Ref DT is reached. As a result of the determination in operation 1300, when the discharge time is greater than or equal to the predetermined reference time Ref DT, the discharge operation is stopped and the negative charge pumping operation is performed (step S1400). The negative charge pumping operation performed in operation S1400 may be performed by a predetermined reference time Re PT PT under the control of the control logic 190.

Subsequently, in step 1500, it is determined whether the time at which the negative charge pumping is performed is greater than or equal to the predetermined reference time Ref PT. As a result of the determination in step S1500, when the time at which the negative charge pumping is performed is less than the predetermined reference time Ref PT, the negative charge pumping operation of the step S1400 is continued until the predetermined reference time Ref PT. As a result of the determination in step S1500, when the time when the negative charge pumping is performed is greater than or equal to the predetermined reference time Re PT, the negative charge pumping operation is stopped (step S1600).

In the above, a method of generating a negative verification voltage has been described as an example, but this is only an example for describing the present invention. For example, the voltage generation characteristics of the present invention for controlling each section (eg, the discharge section and the pumping section) for an optimized time to generate a negative verify voltage include various types of negative word line voltages and Both can be applied to generate a positive wordline voltage.

FIG. 11 is a diagram illustrating a threshold voltage distribution when a part of a threshold voltage of a memory cell is distributed in a negative voltage region, and another example of verification voltages and read voltages corresponding thereto. FIG. 12 shows the levels of the first to seventh pre-verify voltages Vvfy1_C to Vvfy7_C and the first to seventh main verify voltages Vvfy1_F to Vvfy7_F corresponding to the respective program states ST0 to ST7 shown in FIG. Illustrates a generation method by way of example.

11 and 12 exemplarily show a two-step verify read operation in which a verify read operation is performed twice for each program state ST0 to ST7 during the program verify interval V. Referring to FIG. Is shown. However, this is only an example to which the present invention is applied, and the number of verify read operations that can be applied to each program state ST0 to ST7 during the program verify interval V is not limited to a specific number, and variously configured. Can be.

11 and 12, in the two-step verify read operation, in order to determine whether or not the threshold voltage of the programmed memory cell exists within each of the target program states ST0 to ST7, the respective program state ( The first verify read operation using the pre verify voltage Vvfy_C and the second verify read operation using the main verify voltage Vvfy_F may be performed on the ST0 to ST7. If it is determined that the program has failed in the first verify read operation and / or the second verify read operation, the program loops may be repeatedly performed within a predetermined number of times until all the memory cells are determined to be the program pass. In an exemplary embodiment, the pre-verification voltage Vvfy_C may be configured to be lower than the main verify voltage Vvfy_F. The first verify read operation using the pre verify voltage Vvfy_C is called a coarse verify operation, and the second verify read operation using the main verify voltage Vvfy_F is called a fine verify operation.

In the case where the moving distance of the threshold voltage is long during programming or when the distribution of the threshold voltage is to be programmed more densely, the above-described two-step verification scheme may be applied to the program operation. The one-step verification method shown in FIGS. 5 and 6 and the two-step verification method shown in FIGS. 11 and 12 may be mixed with each other, and the verification method applicable to the present invention is not limited to a specific form. Various configurations are possible.

Except that two verify voltages correspond to the respective program states ST1 to ST7, the generation method of the verify voltages Vvfy1_C to Vvfy7_C and Vvfy1_F to Vvfy7_F shown in FIG. It is substantially the same as the voltages Vvfy1 to Vvfy7. Accordingly, duplicate descriptions will be omitted below.

When the verification voltages Vvfy1_C to Vvfy7_C and Vvfy1_F to Vvfy7_F shown in FIG. 12 are generated, four discharge periods 11 to 14 may exist.

In an exemplary embodiment, the reference time t1_d, t2_d, t3_d set in the discharge sections 11 to 14 shown in FIG. 12 is the voltage difference between adjacent verification voltages between the discharge sections 11 to 14. It may be set based on. For example, the first discharge time t1_d may be set in the discharge periods 11 and 13 between the verification voltages applied to the same negative program state. The second discharge time t2_d may be set in the discharge period 12 between the verify voltages applied to different negative program states. In addition, a third discharge time t3_d may be set in the discharge period 14 between the verification voltages applied to the negative program state and the positive program state.

In an embodiment, the magnitudes of the first to third discharge times t1_d to t3_d may have different values. For example, the third discharge time t3_d may have the smallest value. The second discharge time t2_d may have a value equal to or greater than the third discharge time t3_d. The first discharge time t1_d may have a value equal to or greater than the second discharge time t2_d. However, this is only an example to which the present invention is applied, and the sizes of the first to third discharge times t1_d to t3_d may be variously changed without being limited to specific forms.

The control method of the present invention, which sets each discharge section to an optimized predetermined reference time value, can be applied not only to the discharge section but also to the section in which negative charge pumping is performed and each section in which positive charge pumping is performed.

In an exemplary embodiment, all of the sections in which negative charge pumping is performed may be set to the same reference time (Ref PT) value, respectively, according to the type and voltage level of the negative verification voltage generated as shown in FIG. 12. It may be set to another value. For example, the negative voltage pumping period for generating the first negative verify voltage Vvfy1_C may be set as the first pumping time t1_p. The negative voltage pumping period for generating each negative fine verify read voltage Vvfy1_F and Vvfy2_F may be set as a second pumping time t2_p. Except for the first negative verify voltage Vvfy1_C, the negative voltage pumping period for generating the negative coarse verify read voltage Vvfy2_C may be set as the third pumping time t3_p. The positive voltage pumping interval for generating the positive coarse verify read voltages Vvfy3_C to Vvfy7_C may be set to the fourth pumping time t4_p, and the positive precision verify read voltages Vvfy3_F to Vvfy7_F may be set. The positive voltage pumping period to be generated may be set to the fifth pumping time t5_p.

The section in which the negative charge and positive charge pumping is performed may also be set based on the voltage difference between adjacent verification voltages having the pumping section therebetween. Therefore, the first pumping time t1_p having the largest voltage difference between the adjacent verify voltages may have the largest value. The second pumping time t2_p or the fifth pumping time t5_p having the smallest voltage difference between adjacent verification voltages may have the smallest value.

The reference time values (Ref DT, Ref PT) to be set in each negative charge pumping section, each discharge section, and each positive charge pumping section can be set using values obtained by the manufacturer by experiment. The set reference time values Ref DT and Ref PT may be configured to vary within a predetermined range based on the number of times of program / erase, temperature, etc. of the flash memory.

According to the configuration of the present invention, each section for the generation of the continuous negative verify voltage and positive verify voltage can be controlled at an optimized time, so that the program verify speed can be further improved.

13 is a diagram illustrating a structure of a memory cell array according to an embodiment of the present invention. 13 illustrates a cell array 110_1 of a stacked flash structure.

Referring to FIG. 13, a flash memory device according to an embodiment of the present invention may include three-dimensionally arranged memory cells. The memory cells may be formed in a plurality of stacked semiconductor layers used as semiconductor substrates for forming MOS transistors. Although two semiconductor layers (ie, the first semiconductor layer 10 ′ and the second semiconductor layer 20 ′) are illustrated in FIG. 13 for convenience of description, the number of semiconductor layers may be two or more.

In an exemplary embodiment, the first semiconductor layer 10 'may be a single crystal silicon wafer, and the second semiconductor layer 20' may use the first semiconductor layer 10 '(ie, wafer) as the seed layer. It may be a single crystal silicon epitaxial layer formed through an epitaxial process. In example embodiments, each of the semiconductor layers 10 ′ and 20 ′ may include a cell array having substantially the same structure, and the memory cells may constitute a multi-layer cell array 110_1.

Each of the semiconductor layers 10 ′ and 20 ′ may have active regions defined by well-known device isolation layer patterns 15. The active regions may be formed parallel to each other along one direction. The device isolation layer patterns 15 may be made of insulating materials including a silicon oxide layer and may electrically separate the active regions.

On each of the semiconductor layers 10 'and 20', a gate structure composed of a pair of selection lines GSL and SSL and M word lines WL across the active regions. Can be arranged. Source plugs 50 ′ may be disposed on one side of the gate structure, and bit line plugs 40 ′ may be disposed on the other side of the gate structure. The bit line plugs 40 ′ may be connected to N bit lines BL, respectively, across the word lines WL. In this case, the bit lines BL may be formed to cross the word lines WL on the uppermost semiconductor layer (eg, the second semiconductor layer 20 ′ in FIG. 13). The number N of bit lines BL may be an integer greater than 1, and preferably one of multiples of eight.

The word lines WL are disposed between the selection lines GSL and SSL, and the number M of the word lines WL constituting the gate structure is an integer greater than one. Preferably, the integer M may be one of multiples of eight. One of the selection lines GSL and SSL may be used as a ground selection line GSL that controls electrical connection between the common source line CSL and the memory cells. The other one of the selection lines may be used as a string selection line SSL for controlling the electrical connection between the bit lines and the memory cells.

Impurity regions may be formed in the active region between the selection lines and the word lines. In this case, the impurity regions 11S and 21S formed at one side of the ground selection line GSL may be used as source electrodes connected by the common source line CSL, and one of the string selection line SSL may be used. The impurity regions 11D and 21D formed at the side may be used as drain electrodes connected to the bit lines BL through the bit line plugs 40 '. In addition, the impurity regions 11I and 21I formed at both sides of the word lines WL may be used as internal impurity regions that connect the memory cells in series.

Source plugs 50 ′ are formed in the first and second semiconductor layers 10 ′ and 20 ′ and are used as source electrodes to form impurity regions 11S and 21S (hereinafter, referred to as first and second source regions). S) may be electrically connected to the semiconductor layers 10 'and 20'. As a result, the first and second source regions 11S and 21S form an equipotential with the semiconductor layers 10 'and 20'. For this electrical connection, the source plugs 50 ′ may be connected to the first source region 11S through the second semiconductor layer 20 ′ and the second source region 21S. In this case, the source plug 50 ′ may directly contact the inner walls of the second semiconductor layer 20 ′ and the second source region 21S.

The flash memory of the stack flash structure shown in FIG. 13 may also be applied to the voltage generation method of the present invention described above, and the negative voltage and the positive voltage generated in the present invention are applied as a word line voltage to the flash memory shown in FIG. Can be. In addition, the negative voltage generation method of the present invention may be applied to a three-dimensional flash memory cell structure in which memory cells are three-dimensionally formed. The manufacturing technique of the three-dimensional flash memory device is not based on the method of repeating the step of forming the memory cells in two dimensions, but because the word lines or word line planes are formed using a patterning process for defining an active region. As a result, the manufacturing cost per bit can be greatly reduced.

14 is a diagram illustrating the structure of a memory cell array in accordance with another embodiment of the present invention. 14 exemplarily illustrates a cell array 110_2 of a three-dimensional flash structure.

Referring to FIG. 14, a cell array 110_2 of a flash memory of the present invention includes a plurality of electrically isolated wordline plates WL_PT and a plurality of active arranged across the plurality of wordline planes. It may include pillars PL (or active regions). The semiconductor substrate may include a well region Well and a source region S. FIG. The source region S may be formed to have a different conductivity type from that of the well region Well. For example, the well region Well may be made of p-type silicon, and the source region S may be made of n-type silicon. In an exemplary embodiment, the well region Well is surrounded by at least one other well region (not shown) having a conductivity type different from that of the well region Well, thereby providing a pocket well structure. structure or triple well structure.

Each word line plane WL_PT may be composed of a plurality of local word lines LWL electrically connected on a coplanar to have an equipotential. Each of the word line planes WL_PT may be electrically separated by an interlayer insulating film (not shown). Each of the word line planes WL_PT may be connected to each of the global word lines GWL electrically separated through the word line contacts WL_CT. The word line contacts WL_CT may be formed at the edges of the memory cell array or the array blocks. The width of the word line planes WL_PT and the position where the word line contacts WL_CT are disposed may be configured in various forms. Can be.

Each active pillar PL has a body portion B adjacent to the well region Well and a drain region D adjacent the upper selection lone USLi (i is an integer less than or equal to N). ) May be included. The body portion B may be formed of the same conductivity type as the well region Well, and the drain region D may be formed of a different conductivity type than the well region Well. The plurality of active pillars PL may have long axes in a direction passing through the plurality of word line planes WL_PT. Intersections between the plurality of wordline planes WL_PT and the plurality of active pillars PL may be three-dimensionally distributed. That is, each of the memory cells MC of the 3D memory may be formed by three-dimensionally distributed intersections. The gate insulating layer GI may be disposed between the word line plane WL_PT and the active pillar PL. In example embodiments, the gate insulating layer GI may be a multilayer, for example, a stack of ONO. A portion of the gate insulating film may be used as a thin film (ie, a charge storage film or a charge storage layer) for storing information.

One end of the active pillars PL may be commonly connected to the well region, and the other ends thereof may be connected to the plurality of bit lines BL. A plurality of (eg, N) active pillars PL may be connected to one bit line BL. Therefore, a plurality of (eg, N) cell strings CSTR may be connected to one bit line BL. In addition, one cell string CSTR may be configured in one active pillar PL. One cell string CSTR may include a plurality of memory cells MCs formed in the plurality of word line planes WL_PT. One memory cell MC may be defined by one active pillar PL and one local word line LWL or wordline plane WL_PT.

In order to program each memory cell MC and read the programmed data, one cell string CSTR (that is, one active pillar PL) must be independently selected. To this end, a plurality of upper selection lines USLi may be disposed between the bit lines BL and the highest word line plane WL_PT. The upper selection lines USLi may be disposed to intersect the bit lines BL. The bit lines BL may be electrically connected to the drain region D through a predetermined plug, and may be in direct contact with the drain region D.

A plurality of upper select transistors controlling electrical connection between the corresponding active pillar PL and the corresponding bit line BL may be formed in an intersection area of the plurality of bit lines BL and the plurality of upper select lines USLi. upper selection transistor) may be formed. The upper selection gate USGi of each upper selection transistor may be connected to a corresponding upper selection line USLi, respectively. As a result, one active pillar PL (that is, one cell string CSTR) may be independently selected by one bit line BL and one upper selection line USLi.

As shown in FIG. 14, a source region S may be formed in the well region Well to form a charge path to / from the bit line BL. The source region S may be electrically connected to a common source line CSL. A source contact plug S_CT penetrating the word line planes WL_PT may be interposed between the common source line CSL and the source region S. The common source line CSL may be disposed on the bit lines BL through the source contact plug S_CT and may be formed of a metallic material. However, this corresponds to an example configuration of the common source line CSL, and the common source line CSL may be configured in various forms.

In order to control the charge path to / from the bitline BL, between the well region Well and the lowest wordline plane WL_PT, the electrical connection between the active pillars PL and the well region Well is controlled. A plurality of lower selection lines LSL may be disposed. In an exemplary embodiment, the plurality of lower selection lines LSL may constitute a lower selection plate LS_PT having an electrically equipotential. Each of the lower selection lines LSL is applied to the lower selection gate LSGi of the corresponding lower selection transistor, respectively, so as to separate between the corresponding active pillar PL and the well region Well. The electrical connection can be controlled. The flash memory of the three-dimensional structure described above can also be applied to the voltage generation method of the present invention described above, the negative word line voltage and the positive word line voltage generated in the present invention is the flash memory of FIG. It can be applied to the word line plane.

FIG. 15 is a diagram illustrating a configuration of a storage device 1500 including a flash memory device and a user device 1000 including the flash device according to the present invention.

Referring to FIG. 15, the user device 1000 may include a host 1300 and a data storage device 1500. The host 1300 may be configured to control the data storage device 1500. The host 1300 may include, for example, a portable electronic device such as a personal / portable computer, a personal digital assistant (PDA), a portable media player (PMP), an MP3 player, or the like. The host 1300 and the data storage device 1500 may be connected by a standardized interface such as a USB, SCSI, ESDI, SATA, SAS, PCI-express, or IDE interface. The interface method for connecting the host 1300 and the data storage device 1500 is not limited to a specific form and may be variously configured.

The data storage device 1500 may constitute a solid state disk or a solid state drive (SSD) device. In the present invention, a case in which the data storage device 1500 is configured of an SSD will be described as an example. However, this is only an example to which the present invention is applied, and the data storage device 1500 may be configured in various forms without being limited to an SSD. For example, the data storage device 1500 may be integrated into one semiconductor device, such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC), and a memory stick. , Multimedia cards (MMC, RS-MMC, MMC-micro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS), and the like.

The data storage device 1500 may include a memory controller 1200 and a flash memory 1100 that is a main storage unit. The memory controller 1200 may control a read / write / erase operation of the flash memory 1100 in response to a request from the host 1300.

The flash memory 1100 may include a plurality of nonvolatile memory chips, for example, a plurality of flash memory chips 100_1 to 100_4. The flash memory 1100 may include a plurality of channels. Each flash memory chip 100_1 to 100_4 may perform a read / write / erase operation in response to a request from the host 1300 provided through a corresponding channel.

The configuration and operation of each flash memory chip 100_1 to 100_4 are substantially the same as the flash memory 100 shown in FIG. 1. For example, each of the flash memory chips 100_1 to 100_4 may use a conductive floating gate blocked by an insulating layer as a charge storage layer, and replace Si3N4, Al2O3, HfAlO, HfSiO instead of the conventional conductive floating gate. An insulating film such as or the like may be used as the charge storage layer. The flash memory of the present invention may be composed of any one of a stack flash structure in which arrays are stacked in multiple layers, a flash structure without source-drain, a pin-type flash structure, and a three-dimensional flash structure.

In addition, the negative word line voltage and the positive word line voltage generation characteristics of each of the flash memory chips 100_1 to 100_4 are substantially the same as the negative voltage generation characteristics shown in FIGS. 5 to 12. For example, each of the flash memory chips 100_1 to 100_4 generates a plurality of negative voltages successively as a voltage to be applied to a word line, and has a configuration of converting the level of the generated negative voltage at high speed. In particular, when a second negative voltage having a level higher than the first negative voltage is generated after the first negative voltage is generated in each of the flash memory chips 100_1 to 100_4, the previously generated voltage (ie, the first negative voltage). ) Is discharged at a high speed for a predetermined time (Ref DT) (or after a certain voltage level is discharged), a negative charge pumping may be performed for a predetermined time (Ref PT) to generate a second negative voltage. According to such a configuration, each section for generating a negative voltage can be controlled at an optimized time, and a negative voltage of a desired level can be generated within a short time.

In the above, the negative voltage generation method when the negative verification voltage is continuously generated has been described as an example. However, this is only an example to which the present invention is applied, and the negative voltage generation method according to the present invention is not limited to a specific type of negative voltage (for example, a verification voltage and a read voltage), and various kinds of negative voltages. (E.g., various kinds of negative word line voltages) and various kinds of positive word line voltages. Therefore, according to the word line voltage generation method of the present invention, it is possible to convert the negative word line voltage and the positive word line voltage level at high speed, and to reduce the time required for the program. In addition, it is possible to efficiently perform a read operation and a verify operation on data states distributed in a negative voltage region and a positive voltage region.

16 is a block diagram illustrating a data storage device 2000 according to another exemplary embodiment.

Referring to FIG. 16, the data storage device 2000 according to the present invention may include a memory controller 2200 and a flash memory 2100.

The flash memory 2100 shown in FIG. 16 is substantially the same as the flash memory 100 shown in FIG. , Pin-type flash structure, and three-dimensional flash structure. In addition, the negative word line voltage and the positive word line voltage generation characteristics of the flash memory 2100 illustrated in FIG. 16 are also substantially the same as the voltage generation characteristics illustrated in FIGS. 5 to 12. Therefore, redundant description is omitted below.

The memory controller 2200 may be configured to control the flash memory 2100. The memory controller 2200 may be configured in the same manner as the memory controller 1200 illustrated in FIGS. 1 and 15.

The SRAM 2230 may be used as a working memory of the CPU 2210. The host interface 2220 may include a data exchange protocol of a host connected to the data storage device 2000. The error correction circuit 2240 included in the memory controller 2200 may detect and correct an error included in read data read from the flash memory 2100. The memory interface 2260 may interface with the flash memory 2100 of the present invention. The CPU 2210 may perform various control operations for exchanging data of the memory controller 2200. Although not shown in the drawing, the data storage device 2000 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host.

The data storage device 2000 according to the present invention includes a computer, a portable computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA, a portable computer, a web tablet, a wireless device. Wireless phone, mobile phone, smart phone, digital camera, digital audio recorder, digital audio player, digital video recorder picture recorder, digital picture player, digital video recorder, digital video player, device that can send and receive information in wireless environment, and various user devices that make up home network It can be applied to one of these.

The data storage device 2000 may be applied to one of various user devices forming a computer network and may be applied to one of various user devices forming a telematics network. In addition, the data storage device 2000 may be applied to an RFID device or one of various components constituting the computing system (eg, a semiconductor drive (SSD), a memory card, etc.).

17 is a block diagram illustrating an example of a data storage device 3000 according to another exemplary embodiment.

Referring to FIG. 17, the data storage device 3000 according to the present invention may include a flash memory 3100 and a flash controller 3200. The flash controller 3200 can control the flash memory 3100 based on control signals received from outside the data storage device 3000. [ The configuration and operation of the flash controller 3200 are substantially the same as the memory controllers 1200 and 2200 illustrated in FIGS. 15 and 16. Therefore, redundant description is omitted below.

In addition, the configuration of the flash memory 3100 is substantially the same as the flash memory 100 shown in FIG. 1, and the inventive flash memory includes a stack flash structure in which arrays are stacked in multiple layers, a flash structure without source-drain, and a pin. And a three-dimensional flash structure. In addition, the negative word line voltage and the positive word line voltage generation characteristics of the flash memory 2100 illustrated in FIG. 17 are also substantially the same as the voltage generation characteristics illustrated in FIGS. 5 to 12. Therefore, redundant description is omitted below.

The data storage device 3000 of the present invention may constitute a memory card device, an SSD device, a multimedia card device, an SD device, a memory stick device, a hard disk drive device, a hybrid drive device, or a general-purpose serial bus flash device. For example, the data storage device 3000 of the present invention can configure a card that meets industry standards for using a user device such as a digital camera, a personal computer, and the like.

18 is a diagram illustrating a schematic configuration of a flash memory device 4100 and a computing system 4000 including the same according to the present invention.

Referring to FIG. 18, a computing system 4000 according to the present invention may include a flash memory device 4100, a memory controller 4200, and a modem 4300 such as a baseband chipset electrically connected to a bus 4400. , Microprocessor 4500, and user interface 4600. The configuration of the flash memory device 4100 shown in FIG. 18 is substantially the same as that of the flash memory 100 shown in FIG. 1. One of a flash structure, a pin-type flash structure, and a three-dimensional flash structure. The negative word line voltage and the positive word line voltage generation characteristics of the flash memory 4100 according to the present invention are substantially the same as the voltage generation characteristics shown in FIGS. 5 to 12. Therefore, redundant description is omitted below.

When the computing system according to the present invention is a mobile device, a battery 4700 for supplying an operating voltage of the computing system may be additionally provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, or the like. The memory controller 4200 and the flash memory device 4100 may configure, for example, an SSD (Solid State Drive / Disk) that uses a nonvolatile memory to store data.

The nonvolatile memory device and / or memory controller according to the present invention may be mounted using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package ( It can be implemented using packages such as WSP).

As described above, the embodiments are disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100, 1100, 2100, 3100, 4100: flash memory
110: cell array 111: cell string
120: row decoder 130: column decoder
140: write-out circuit 170: voltage generator
171: high voltage generator 173: low voltage generator
175: negative voltage generator 180: voltage selection switch
190: control logic

Claims (10)

Generating a program voltage through a high voltage generator;
Generating a plurality of negative program verify voltages corresponding to the plurality of negative data states through the negative voltage generator; And
Generating at least one positive program verify voltage corresponding to at least one data state via a low voltage generator,
The generating of the plurality of negative program verify voltages may include:
Performing negative charge pumping for a first pumping time to generate a first negative verify voltage;
If a second negative verify voltage higher than the first negative verify voltage is generated after the first negative verify voltage is generated, discharging the first negative verify voltage for a first discharge time; And
And performing the negative charge pumping during the second pumping time after the first discharge time to generate the second negative verify voltage. The method of claim 1,
And the discharge result is higher than the second negative verify voltage and equal to or lower than a ground voltage. The method of claim 1,
When a third negative verification voltage lower than the first negative verification voltage is generated after the first negative verification voltage is generated, the third negative sound is performed by performing negative charge pumping for a third pumping time without the discharge operation. Generating a verify voltage of the word line voltage of the flash memory. The method of claim 1,
Discharging the second negative verify voltage for a second discharge time less than the first discharge time, when the at least one positive program verify voltage is generated after the second negative verify voltage is generated. The word line voltage generation method of the flash memory further comprising. The method of claim 4, wherein
And the first and second discharge times have a larger value as a difference between verification voltages having a discharge period in which the discharge operation is performed increases. A flash memory cell array including a plurality of flash memory cells connected to a plurality of word lines;
A voltage generator generating a plurality of word line voltages to be applied to the word lines; And
Control logic for controlling the voltage generation operation of the voltage generator,
When the second negative voltage higher than the first negative voltage is continuously generated after the first negative voltage is generated, the voltage generator may generate the first negative voltage under a predetermined discharge time in response to the control of the control logic. And a negative voltage generator configured to generate the second negative voltage by performing negative charge pumping during the first pumping time after discharge. The method according to claim 6,
And the discharge result is higher than the second negative voltage and equal to or lower than the ground voltage. The method according to claim 6,
When the third negative voltage lower than the first negative voltage is generated after the first negative voltage is generated, the negative voltage generator performs negative charge pumping for a second pumping time without the discharge operation, thereby performing the third negative voltage. Causing flash memory device. The method according to claim 6,
The negative voltage generator
An oscillator for generating an oscillation signal in response to the control of the control logic;
A negative voltage charge pump performing negative charge pumping in response to the oscillation signal;
A discharge unit for discharging the output of the negative voltage charge pump; And
Converting a target negative voltage from the first negative voltage to the second negative voltage when the second negative voltage is generated, and comparing the negative charge pumping result of the negative voltage charge pump with the target negative voltage; A voltage detector,
And the oscillator generates the oscillation signal during the first pumping time in response to a comparison result of the voltage detector or control of the control logic. The method of claim 9,
And the control logic controls the oscillator to generate the oscillation signal after the discharge time has elapsed.

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