KR20120100004A

KR20120100004A - Non volatile memory device and program method thereof

Info

Publication number: KR20120100004A
Application number: KR1020110018584A
Authority: KR
Inventors: 권오석; 박기태
Original assignee: 삼성전자주식회사
Priority date: 2011-03-02
Filing date: 2011-03-02
Publication date: 2012-09-12

Abstract

The program method of the nonvolatile memory device of the present invention includes reading first page data from selected memory cells, and programming second page data into the selected memory cells with reference to the read first page data. Wherein at least one of the memory cells having a threshold voltage corresponding to a first negative program state in the reading step is a second negative program state in the programming step. Is programmed.

Description

Nonvolatile memory device and its program method {NON VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF}

The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device and a program method thereof.

The semiconductor memory device may be largely classified into a volatile semiconductor memory device and a non-volatile semiconductor memory device. Volatile semiconductor memory devices are fast to read and write, but the stored contents are lost when the power supply is cut off. On the other hand, nonvolatile semiconductor memory devices retain their contents even when their power supplies are interrupted. Therefore, the nonvolatile semiconductor memory device is used to store contents to be preserved regardless of whether or not power is supplied.

Non-volatile semiconductor memory devices include mask read-only memory (MROM), programmable read-only memory (PROM), erasable and programmable ROM (EROM), and electrically Electrically erasable programmable read-only memory (EEPROM).

A typical example of a nonvolatile memory device is a flash memory device. Flash memory refers to computers, mobile phones, PDAs, digital cameras, camcorders, voice recorders, MP3 players, personal digital assistants (PDAs), handheld PCs, game machines, fax machines, scanners, printers, etc. It is widely used as a voice and video data storage medium of information devices such as).

In recent years, as the high integration demand for memory devices increases, multi-bit memory devices storing multiple bits in one memory cell have become popular.

It is an object of the present invention to provide a program method and apparatus for data states distributed in a negative voltage region.

According to another aspect of the present invention, there is provided a method of programming a nonvolatile memory device, including reading first page data from selected memory cells, and referring to the read first page data. Programming data, wherein at least one of the memory cells having a threshold voltage corresponding to a first negative program state in the reading step is a second negative program state in the programming step; Programmed as (2nd negative program state).

According to an aspect of the present invention, there is provided a nonvolatile memory device including a cell array including a plurality of memory cells disposed in an intersection region of a plurality of word lines and a plurality of bit lines, and a word line voltage at the plurality of word lines. A voltage generator configured to provide a plurality of data lines, a write read circuit connected to the plurality of bit lines, to write or read data to selected memory cells, and to select selected memory cells from among the plurality of memory cells in a first negative program state. Control logic to control the voltage generator or the write read circuit to program to a second negative program state.

According to the present invention as described above, the data state that can be accommodated in the negative voltage region can be increased, thereby increasing the read margin of the nonvolatile memory device.

1 is a block diagram showing the configuration of a flash memory according to the present invention.
FIG. 2 is a diagram illustrating a structure of a memory cell array shown in FIG. 1.
3A and 3B are block diagrams illustrating the structure of the negative voltage generator 155 of FIG. 1.
4 is a diagram illustrating a program method according to a first embodiment of the present invention.
5 is a waveform diagram illustrating a change in word line voltage during a program operation according to the exemplary embodiment of FIG. 4.
6 is a diagram illustrating a program method according to a second embodiment of the present invention.
7 is a waveform diagram illustrating a change in word line voltage during a program operation according to the exemplary embodiment of FIG. 6.
8 is a diagram illustrating a program method according to a third embodiment of the present invention.
9 is a waveform diagram illustrating a change in a word line voltage during a program operation according to the exemplary embodiment of FIG. 8.
10 is a flowchart showing a program method according to the present invention.
11 is a diagram illustrating a structure of a memory cell array according to an embodiment of the present invention.
12 is a diagram illustrating a structure of a memory cell array according to another embodiment of the present invention.
13 is a block diagram illustrating a configuration of a storage device having a flash memory device and a user device including the same according to the present invention.
14 is a block diagram illustrating a data storage device in accordance with another embodiment of the inventive concept.
15 is a block diagram illustrating a data storage device in accordance with another embodiment of the inventive concept.
16 is a schematic block diagram of a flash memory device and a computing system including the same according to the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Identical components will be referred to using the same reference numerals. Similar components will be quoted using similar reference numerals. The circuit configuration of the flash memory device according to the present invention to be described below and the read operation performed by the present invention are just examples, and various changes and modifications can be made without departing from the technical spirit of the present invention.

1 is a block diagram illustrating a flash memory device 100 according to an embodiment of the present invention. Referring to FIG. 1, the flash memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 130, and a read / write circuit. 140, a voltage generating unit 150, a voltage selection switch 160, and control logic 170.

The memory cell array 110 may be connected to the row decoder 120 through word lines WL, and may be connected to the write read circuit 140 through bit lines BL. The memory cell array 110 includes memory cells arranged in a plurality of rows (or word lines) and a plurality of columns (or bit lines). The plurality of memory cells included in the memory cell array 110 may constitute a plurality of memory blocks. A detailed description of the memory cell array 110 will be described in detail later with reference to FIG. 2.

The row decoder 120 is connected between the voltage selection circuit 160 and the memory cell array 110. The row decoder 120 is configured to operate under the control of the control logic 170. The row decoder 120 receives the row address X-ADDR from the outside and decodes the received row address X-ADDR. The row decoder 120 selects word lines WL based on the decoding result of the row address X-ADDR. The row decoder 120 performs a function of transferring an output (eg, a voltage) of the voltage selection switch 160 to selected word lines and unselected word lines.

The column decoder 130 is connected to the write read circuit 140. The column decoder 130 is configured to operate in response to the control of the control logic 170. The column decoder 130 receives the column address Y-ADDR from the outside and decodes the received column address Y-ADDR. The decoding result of the column address Y-ADDR is provided to the write read circuit 140.

The write read circuit 140 is controlled by the control logic 170 and operates as a sense amplifier or as a write driver depending on the operation mode. For example, in the case of a verify / normal read operation, the write read circuit 140 operates as a sense amplifier for reading data from the memory cell array 110. In the normal read operation, the data DATA read through the column selection circuit 130 is output to the outside of the flash memory 100 (for example, the memory controller or the host). In contrast, the data read through the column select circuit 130 during the verify read operation is provided to a pass / fail verify circuit (not shown) in the flash memory 100 to be used to determine whether the memory cells are successfully programmed. Can be.

In the case of a program operation, the write read circuit 140 operates as a write driver that drives the bit lines BL0 to BLm-1 according to data to be stored in the memory cell array 110. The write read circuit 140 receives data DATA written into the memory cell array 110 from a buffer (not shown) during a program operation, and according to the input data DATA, the bit lines BL0 to BLm−. Drive 1). To this end, the write read circuit 140 may include a plurality of page buffers PB corresponding to columns (or bit lines) or column pairs (or bit line pairs), respectively. A plurality of latches may be provided in each page buffer PB. The plurality of latches may perform an operation of latching data sensed from the page buffer PB and / or latching data to be programmed.

The voltage generator 150 may include a high voltage generator 151, a low voltage generator 153, and a negative voltage generator 155. The high voltage generator 151 may generate the high voltages required to drive the flash memory 100 under the control of the control logic 170. The positive high voltages generated from the high voltage generator 151 may be used as the program voltage Vpgm, the pass voltage Vpass, and the like during the program operation.

The low voltage generator 153 may generate the low voltages required to drive the flash memory 100 under the control of the control logic 170. The positive low voltages generated from the low voltage generator 153 may be used as a read voltage Vrd, a verify voltage Vvfy, a decoupling voltage, a blocking voltage, or the like during a program or read operation.

The negative voltage generator 155 may generate negative voltages for driving the flash memory 100 under the control of the control logic 170. The negative voltages generated from the negative voltage generator 155 may be used as a read voltage Vrd, a verify voltage Vvfy, a decoupling voltage, a blocking voltage, or the like during a program or read operation. The negative voltages generated from the negative voltage generator 155 may be supplied to a bulk (eg, a well region) in which memory cells are formed. Hereinafter, in the present invention, the voltages applied to the word lines for driving the flash memory 100 will be referred to as word line voltages. Outputs of the high voltage generator 151 and the low voltage generator 153 may be transmitted to the voltage selection switch 160. The output of the negative voltage generator 155 may be delivered to the voltage selection switch 160 and the row decoder 120.

The voltage selection switch 160 may be connected to the voltage generator 150, the row decoder 120, and the control logic 170. The voltage selection switch 160 may select one of the voltages output from the voltage generator 150 in response to the control of the control logic 170. The voltage selected by the voltage selection switch 160 may be provided to the corresponding word line WL through the row decoder 120.

When the output of the negative voltage generator 155 is selected by the control of the control logic 170, the voltage selection switch 160 may transfer the negative voltage generated from the negative voltage generator 155 to the row decoder 120. In order to transfer the negative voltage to the row decoder 120 through the field effect transistor, the well region of the voltage selector switch 160 and the well region of the row decoder 120 are caused by the negative voltage generated from the negative voltage generator 155. Can be biased.

When the negative voltage generator 155 is deactivated, the negative voltage generator 155 may generate a ground voltage in response to the control of the control logic 170. When a high voltage or a low voltage is transferred to the word lines WL through the voltage select switch 160 and the row decoder 120, the well regions of the voltage select switch 160 and the row decoder 120 may be biased to the ground voltage. Can be.

The control logic 170 controls various operations related to program, erase, and read operations of the flash memory 100. The voltage generator 150 may generate word line voltages to be supplied to respective word lines according to an operation mode, and a voltage to be supplied to a bulk (eg, a well region) in which memory cells are formed. The voltage generation operation of the voltage generator 150 may be performed by the control of the control logic 170.

FIG. 2 is a block diagram illustrating a memory cell array of FIG. 1 in detail. Referring to FIG. 2, each memory block may include a plurality of cell strings (or NAND strings) 111 connected to bit lines BL0 to BLm−1, respectively.

The cell string 111 may include at least one string select transistor SST, a plurality of memory cells MC0 to MCn-1, and at least one ground select transistor GST. In each cell string 111, the drain of the string select transistor SST is connected to the bit line, and the source of the ground select transistor GST is connected to the common source line CSL. The memory cells MC0 to MCn-1 are connected in series between the source of the string select transistor SST and the drain of the ground select transistor GST.

Each of the memory cells MC0 to MCn-1 may be configured to store data information of N bits (N is greater than or equal to 1) per cell. The memory cells MC0 to MCn-1 may inject charge into the charge storage layer to store respective bit information. In an embodiment, the memory cells MC0 to MCn-1 may use a conductive floating gate that is blocked by an insulating layer as a charge storage layer. In another embodiment, the memory cells MC0 ˜ MCn-1 may use an insulating layer such as Si ₃ N ₄ , Al ₂ O ₃ , HfAlO, HfSiO, or the like as the charge storage layer instead of the conventional conductive floating gate. A flash memory having a structure using an insulating film such as Si ₃ N ₄ , Al ₂ O ₃ , HfAlO, HfSiO, or the like as a charge storage layer is also referred to as a charge trap flash (“CTF”) memory. The operating characteristics of the flash memory 100 of the present invention to be described below are applicable to both a flash memory device in which the charge storage layer is formed of a conductive floating gate, as well as a charge trap type flash in which the charge storage layer is formed of an insulating film.

In addition, the memory cell array 110 of the present invention may be configured as any one of a stack flash structure in which a plurality of cell arrays are stacked in multiple layers, a flash structure without source-drain, a pin-type flash structure, and a three-dimensional flash structure. Can be.

2 illustrates a case in which the flash memory 100 of the present invention is configured as a NAND-type flash memory. However, this is only an embodiment to which the present invention is applied, and the operating characteristics of the flash memory 100 of the present invention to be described below are not only NAND flash memory, but also NOR-type flash memory, at least two. The present invention can be applied to a hybrid flash memory in which more than one kind of memory cells are mixed, or a flash memory in which a controller is embedded in a memory chip.

As shown in FIG. 2, control gates of memory cells arranged in the same row are commonly connected to corresponding word lines WL0-WLn−1. The string select transistor SST is controlled by a voltage applied through the string select line SSL, and the ground select transistor GST is controlled by a voltage applied through the ground select line GSL. The memory cells MC0 to MCn-1 are controlled by voltages applied through corresponding word lines WL0 to WLn-1. Memory cells connected to each of the word lines WL0 to WLn−1 may store data corresponding to one page, a subpage smaller than one page, or a plurality of pages. A read operation for reading data stored in the NAND flash memory and a program operation for storing data in the NAND flash memory may be performed in units of one or a plurality of pages, and in some cases, may be performed in units of subpages. have. An erase operation for erasing data stored in the NAND flash memory may be performed in a block unit composed of a plurality of pages.

3A is a diagram illustrating an embodiment of the negative voltage generator 155 illustrated in FIG. 1. Referring to FIG. 3A, the negative voltage generator 155a according to an embodiment may include a DC voltage generator 210, a reference voltage generator 220, an oscillator 230, a negative voltage detector 240, and a negative voltage pump 250. And a negative voltage generator 260 for the word line.

The DC voltage generator 210 generates a DC voltage VDC_NEG.

The reference voltage generator 220 generates a reference voltage Vref_NEG.

The oscillator 230 oscillates the negative voltage clock CLK_NEG. In an embodiment, the negative voltage clock CLK_NEG may be 30 ns. Here, the oscillator 230 may be configured as another oscillator independent of the oscillator included in the high voltage generator 151 shown in FIG. 1. Alternatively, the oscillator 230 may be used in combination with an oscillator used in the high voltage generator 151 of FIG. 1 to generate a negative voltage clock CLK_NEG.

The negative voltage detector 240 receives the DC voltage VDC_NEG, the reference voltage Vref_NEG, and the negative voltage clock CLK_NEG, detects the negative voltage NWELL for the well voltage, and corresponds to the negative voltage pump clock CLK_NEGP. ).

The negative voltage pump 250 generates the negative voltage NWELL for the well voltage in response to the clock CLK_NEGP. Meanwhile, the negative voltage NWELL for the well voltage is easily changed by external factors, and may be particularly affected by the capacitances of the wells. Therefore, a stable negative voltage needs to be applied to the word line.

The negative voltage generator 260 for the word line receives the negative voltage NWELL, the DC voltage VDC_NEG, and the reference voltage Vref_NEG for the well voltage from the negative voltage pump 250, and the negative voltage NWL to be applied to the word line. ) Here, the negative voltage NWELL for the well voltage is applied to a well having a circuit (not shown) to which the negative voltage is applied, and the negative voltage NWL corresponds to at least one word line and at least one word line. It is applied to one line (e.g., a selection line).

3B is a block diagram illustrating another embodiment of the negative voltage generator 155 of the present invention. Referring to FIG. 3B, the negative voltage generator 155b according to another embodiment may not include the negative voltage generator 260 for a word line, unlike the negative voltage generator 155a illustrated in FIG. 3A. That is, the negative voltage generator 155b includes a DC voltage generator 210, a reference voltage generator 220, an oscillator 230, a negative voltage detector 240, and a negative voltage pump 250. According to the negative voltage generator 155b, the negative voltage output by the negative voltage pump 250 is supplied to both the well and the word line.

4 is a diagram illustrating a program method according to a first embodiment of the present invention. Referring to FIG. 4, in the first embodiment of the present invention, the program state P of the first page 1st page may be programmed into the program states Q2 and Q3 of the second page 2nd page.

When the first page (1st page, or LSB page) is programmed in the selected memory cells, each of the memory cells has a data state of either the erase state E or the program state P. Here, the threshold voltage distribution corresponding to the program state P may be distributed in the threshold voltage region lower than 0V.

When a second page is programmed in the selected memory cells, each of the memory cells has a data state of one of an erase state E0 and a plurality of program states Q1, Q2, and Q3. Here, the erase state E0 and the program state Q1 mean states programmed from the erase state E by the program of the second page. The program states Q2 and Q3 are threshold voltage distributions formed according to the program of the second page from the program state P. The program state P distributed in the negative voltage region may be programmed from the program state P distributed in the negative voltage region.

The procedure for programming the second page is as follows. First, an initial read operation for latching first page data programmed in each of the selected memory cells is performed. In this case, the read voltage Vrd0 provided for the initial read may be provided as a negative voltage. The bit value of the first page stored in each of the memory cells is sensed by the read voltage Vrd0 provided as a negative voltage to the word line of the selected memory cells. The first page data sensed according to the initial read operation may be stored in latches provided in the page buffer (not shown). In addition, data bits corresponding to the second page may be loaded into other latches provided in the page buffer. The target state is determined according to the bit value of the first page latched by the initial read and the bit value of the second page provided as data to be written.

In a program operation, a program voltage is applied to a word line of selected memory cells. Subsequently, a verify read for detecting whether the selected memory cells are programmed is performed a number of times corresponding to the respective program states Q1, Q2, and Q3. That is, the verification voltages Vvfy1, Vvfy2, and Vvfy3 may be sequentially applied to the word lines of the selected memory cells. Here, the verification voltages Vvfy1 and Vvfy2 will be provided as negative voltages.

As described above, according to the voltage distribution formed after programming the second page, at least two program states Q1 and Q2 are included between the erase state E0 and 0V. To be programmed from a negative program state P to another negative program state Q2, a negative voltage window (NVW) is set for accommodating at least two program states between the erase state E0 and 0V. It should be.

FIG. 5 is a waveform diagram illustrating an exemplary program operation of memory cells having the program state of FIG. 4. Referring to FIG. 5, the waveform of the word line voltage provided during the program-verify cycle for the selected memory cells is shown. The initial read operation performed to store the multi-bits in the selected memory cells and the word line voltage waveforms in the verify operation performed before the program voltage is provided are omitted.

First, a program voltage Vpgm1 is provided to a word line of selected memory cells. In this case, when the verify read operation is performed before the program, the memory cells to which logic '1' is written among the selected memory cells will be program inhibited. On the other hand, charge injection by the program voltage Vpgm0 is performed in the charge storage layer of the memory cells to which logic '0' is written among the selected memory cells.

Following the provision of the program voltage Vpgm1, the verify read voltages Vvfy1, Vvfy2, and Vvfy3 are provided to the word lines of the selected memory cells. This program-verify cycle may be repeated until all memory cells are programmed to their target state. In order to accurately control the threshold voltage distribution of the memory cells, the flash memory 100 may be programmed by an incremental step pulse programming (ISPP) scheme. In this case, the program voltages Vpgm1 to VpgmN to be used for the program in each program loop have a voltage level increased stepwise by ΔVp in accordance with the ISPP scheme. In an exemplary embodiment, each verify loop performs three verify read operations using the first to third verify voltages Vvfy1, Vvfy2, and Vvfy3 whenever one program voltage Vpgm1 to VpgmN is applied. Can be. Here, the program voltages Vpgm1 to VpgmN may be configured as positive high voltages. In an exemplary embodiment, the program voltages Vpgm1 to VpgmN may be generated from the high voltage generator 171 by the control of the control logic 170.

In example embodiments, the first and second verification voltages Vvfy1 and Vvfy2 may be configured as negative voltages. The second verify voltage Vvfy2 may be configured as a negative voltage at a level higher than the first verify voltage Vvfy1. Both the first and second verify voltages Vvfy1 and Vvfy2 may be provided from the negative voltage generator 155 under the control of the control logic 170. The third verification voltage Vvfy3 may be configured as a positive voltage. The third verify voltage Vvfy3 may be provided from the low voltage generator 153 by the control of the control logic 170.

6 is a diagram illustrating a program method according to a second embodiment of the present invention. Referring to FIG. 6, in the second embodiment of the present disclosure, the program state Q1 of the second page may be programmed into the program states P2 and P3 of the third page.

When a second page is programmed in the selected memory cells, each of the memory cells has a data state of one of an erase state E0 and a plurality of program states Q1, Q2, and Q3. Here, the threshold voltage distribution corresponding to the program state Q1 may be distributed in the threshold voltage region lower than 0V.

When the selected memory cells are programmed with third page data, each of the memory cells may be selected from one of an erase state E0 and a plurality of program states P1, P2, P3, P4, P5, P6, and P7. It has a data state. Here, the erase state E0 and the program state P1 mean states programmed from the erase state E0 by the program of the third page. The program states P2 and P3 are threshold voltage distributions formed according to the program of the third page from the program state Q1. According to an embodiment of the present disclosure, the memory cell may be programmed from the program state Q1 distributed in the negative voltage region to the program state P2 distributed in the negative voltage region.

The procedure for programming the third page is as follows. First, an initial read operation for latching first page data programmed in each of the selected memory cells is performed. In this case, the read voltage Vrd1 provided for the initial read may be provided as a negative voltage. The read voltage Vrd2 may be provided at a negative voltage of OV or lower. The read voltage Vrd3 may be provided as a positive voltage.

The bit value of the second page stored in each of the memory cells is sensed by the read voltages Vrd1, Vrd2, and Vrd3 provided to the word lines of the selected memory cells. The second page data sensed according to the initial read operation may be stored in latches provided in the page buffer (not shown). In addition, data bits corresponding to the third page may be loaded into other latches provided in the page buffer. The target state is determined according to the bit value of the second page latched by the initial read and the bit value of the third page provided as data to be written.

In a program operation, a program voltage is applied to a word line of selected memory cells. Subsequently, a verify read for detecting whether the selected memory cells are programmed is performed a number of times corresponding to the respective program states P1, P2, P3, P4, P5, P6, and P7. That is, the verification voltages Vvfy1, Vvfy2, Vvfy3, Vvfy4, Vvfy5, Vvfy6, and Vvfy7 may be sequentially applied to the word lines of the selected memory cells. Here, the verification voltages Vvfy1 and Vvfy2 will be provided as negative voltages.

As described above, according to the voltage distribution formed after programming the third page, at least two program states P1 and P2 are included between the erase state E0 and 0V. To be programmed from negative program state Q1 to another negative program state P2, a negative voltage window (NVW) is set for accommodating at least two program states between the erase state E0 and 0V. It should be.

FIG. 7 is a waveform diagram illustrating an exemplary program operation of memory cells having the program state of FIG. 6. Referring to Figure 7, the waveform of the word line voltage provided during the program-verify cycle for the selected memory cells is shown. The initial read operation performed to store the multi-bits in the selected memory cells and the word line voltage waveforms in the verify operation performed before the program voltage is provided are omitted.

First, a program voltage Vpgm1 is provided to a word line of selected memory cells. In this case, when the verify read operation is performed before the program, the memory cells to which logic '1' is written among the selected memory cells will be program inhibited. On the other hand, charge injection by the program voltage Vpgm1 is performed in the charge storage layer of the memory cells to which logic '0' is written among the selected memory cells.

Following the provision of the program voltage Vpgm1, the verify read voltages Vvfy1, Vvfy2, Vvfy3, Vvfy4, Vvfy5, Vvfy6, Vvfy7 are provided as word lines of the selected memory cells. This program-verify cycle may be repeated until all memory cells are programmed to their target state. In order to accurately control the threshold voltage distribution of the memory cells, the memory cells may be programmed by an incremental step pulse programming (ISPP) scheme. In this case, the program voltages Vpgm1 to VpgmN to be used for the program in each program loop have a voltage level increased stepwise by ΔVp in accordance with the ISPP scheme. In an exemplary embodiment, each program loop applies the first to third verification voltages Vvfy1, Vvfy2, Vvfy3, Vvfy4, Vvfy5, Vvfy6, and Vvfy7 each time one program voltage Vpgm1 to VpgmN is applied. The seven verified read operations used may be performed. Here, the program voltages Vpgm1 to VpgmN may be configured as positive high voltages. In an exemplary embodiment, the program voltages Vpgm1 to VpgmN may be generated from the high voltage generator 171 by the control of the control logic 170.

8 is a diagram illustrating a program method according to a third embodiment of the present invention. Referring to FIG. 8, in the third embodiment of the present invention, the program state Q1 of the n-th page is divided into the program states P2 of the n + 1 page (n + 1-th page). Can be programmed as P3). The program state Q2 of the n-th page may be programmed to the program states P4 and P5 of the n + 1th page n + 1-th page. The program states P1, P2, P3, and P4 when one page is programmed are distributed in the negative threshold voltage regions, and among these, the program states P2, P3, and P4 are the program states Q1. , Q2) have been moved according to the program of data.

When the selected memory cells are programmed to the n + 1th page, each of the memory cells has data of one of an erase state E0 and a plurality of program states P1, P2, P3, P4, P5, P6, P7,... You have a state. Here, the erase state E0 and the program states P1 mean a state programmed from the erase state E0 by the program of the n + 1th page. The program states P2, P3, and P4 are threshold voltage distributions formed according to the program of the n + 13th page from the program states Q1 and Q2. According to an embodiment of the present disclosure, a memory cell may be programmed from program states Q1 and Q2 distributed in a negative voltage region to program states P2, P3 and P4 distributed in a negative voltage region.

The procedure for programming the n + 1th page is as follows. First, an initial read operation for latching n-th page data programmed in each of the selected memory cells is performed. In this case, the read voltages Vrd1 and Vrd2 provided for the initial read may be provided as negative voltages. The read voltage Vrd3 may be provided at a negative voltage of OV or lower. The read voltage Vrd4 may be provided as a positive voltage.

The bit value of the n th page stored in each of the memory cells is sensed by the read voltages Vrd1, Vrd2, Vrd3,..., Which are provided to the word lines of the selected memory cells. The n th page data sensed according to the initial read operation may be stored in latches provided in the page buffer (not shown). In addition, data bits corresponding to the n + 1th page may be loaded into other latches provided in the page buffer. The target state is determined according to the bit value of the n th page latched by the initial read and the bit value of the n + 1 page provided as data to be written.

In a program operation, a program voltage is applied to a word line of selected memory cells. Subsequently, a verify read for detecting whether the selected memory cells are programmed is performed a number of times corresponding to the respective program states P1, P2, P3, P4, P5, P6, P7,... That is, the verification voltages Vvfy1, Vvfy2, Vvfy3, Vvfy4, Vvfy5, Vvfy6, Vvfy7,... May be sequentially applied to the word lines of the selected memory cells. Here, the verification voltages Vvfy1, Vvfy2, Vvfy3, and Vvfy4 may be provided as negative voltages.

As described above, according to the voltage distribution formed after programming the n + 1th page, a plurality of program states P1, P2, P3, and P4 are included between the erase state E0 and 0V. In order to be programmed from negative program states Q1 and Q2 to other negative program states P2, P3 and P4, at least two program states P1, P2, P3 and P4 between the erase state E0 and 0V. The Negative Voltage Window (NVW) must be set to accommodate this.

9 is a waveform diagram illustrating an exemplary program operation of memory cells having the program state of FIG. 8. 9, the waveform of the word line voltage provided during the program-verify cycle for the selected memory cells is shown. The initial read operation performed to store the multi-bits in the selected memory cells and the word line voltage waveforms in the verify operation performed before the program voltage is provided are omitted.

First, a program voltage Vpgm1 is provided to a word line of selected memory cells. Following the provision of the program voltage Vpgm1, the word lines of the selected memory cells are provided with the verify read voltages VVvfy1, Vvfy2, Vvfy3, Vvfy4, Vvfy5, Vvfy6, Vvfy7,... This program-verify cycle may be repeated until all memory cells are programmed to their target state. In order to accurately control the threshold voltage distribution of the memory cells, the memory cells may be programmed by an incremental step pulse programming (ISPP) scheme. In this case, the program voltages Vpgm1 to VpgmN to be used for the program in each program loop have a voltage level increased stepwise by ΔVp in accordance with the ISPP scheme. In an exemplary embodiment, in each program loop, each time one program voltage Vpgm1 to VpgmN is applied, the first to third verification voltages Vvfy1, Vvfy2, Vvfy3, Vvfy4, Vvfy5, Vvfy6, Vvfy7,... 7 verify read operations may be performed. Here, the program voltages Vpgm1 to VpgmN may be configured as positive high voltages. In an exemplary embodiment, the program voltages Vpgm1 to VpgmN may be generated from the high voltage generator 171 by the control of the control logic 170.

In example embodiments, the first to fourth verification voltages Vvfy1, Vvfy2, Vvfy3, and Vvfy4 may be configured as negative voltages. The second verify voltage Vvfy2 may be configured as a negative voltage at a level higher than the first verify voltage Vvfy1. The third verify voltage Vvfy3 may be configured as a negative voltage at a level higher than the second verify voltage Vvfy2. The fourth verify voltage Vvfy4 may be configured as a negative voltage at a level higher than the third verify voltage Vvfy3. The first to fourth verification voltages Vvfy1, Vvfy2, Vvfy3, and Vvfy4 may all be provided from the negative voltage generator 155 under the control of the control logic 170. The fifth verification voltage Vvfy5 or more may be configured as a positive voltage. The fifth verify voltage Vvfy5 and higher verify voltages Vvfy6, Vvfy7,... May be provided from the low voltage generator 153 by control of the control logic 170.

10 is a flow chart briefly showing the program method of the present invention. Referring to FIG. 10, an initial read operation or a verify read operation may be performed before executing a program loop.

In operation S110, an initial read operation is performed on the memory cells before writing the multi-bit data. At this time, data stored in each of the memory cells is sensed and stored in the latch of the corresponding page buffer. The data to be programmed will then be loaded into another latch of the page buffer.

In operation S120, a read verification may be performed on the selected memory cells. In this case, the verify read voltage may be provided to verify read voltages (eg, Vvfy1 and Vvfy2 of FIG. 6) included in the negative voltage region. According to the verify read operation, the bit line of the memory cells may be biased to be program inhibited or biased to 0V.

In operation S130, a program execution operation in which a program voltage is applied to the word lines of the selected memory cells is performed. The program voltage Vpgm0 in the original program loop may be provided at the lowest high voltage, and the program voltage provided thereafter may be provided in an ISPP manner in which the program voltage is gradually increased.

In operation S140, the memory cells to which the program voltage Vpgm is applied are sensed by the plurality of verify read voltages Vvfy1, Vvfy2,..., VvfyN. It will be detected whether the selected memory cells have been programmed to the target state by the verify read voltages Vvfy1, Vvfy2,..., VvfyN. Memory cells programmed in the target state will be set to be program inhibited by the page buffer.

In step S150, it is detected whether all selected memory cells have been programmed. If all memory cells are detected to be programmed (Yes), the program procedure for the selected memory cells ends. On the other hand, if it is detected that there are still memory cells that are not programmed to the target state (No), the procedure moves to step S160 when the program voltage is increased by the step voltage ΔVp.

In step S160, an increased program voltage is generated than in the previous loop. The procedure then returns to step S130 for applying the increased program voltage to the selected memory cells. Steps S130 to S160 constitute one program loop and will be repeated until the selected memory cells are programmed.

According to the program method according to the exemplary embodiment described above, the threshold voltages of some of the selected memory cells may be programmed from the program state existing in the negative voltage region to the program state existing in another negative voltage region. Can be. Here, step S120 may be selectively performed or not performed.

11 is a diagram illustrating a structure of a memory cell array according to an embodiment of the present invention. 11 illustrates a cell array 110_1 of a stacked flash structure. Referring to FIG. 11, a flash memory device according to the present invention may include memory cells arranged in three dimensions. Memory cells may be formed in a plurality of stacked semiconductor layers used as semiconductor substrates for forming MOS transistors. Although two semiconductor layers (ie, the first semiconductor layer 10 ′ and the second semiconductor layer 20 ′) are shown in FIG. 13 for convenience of description, the number of semiconductor layers may be two or more.

In an exemplary embodiment, the first semiconductor layer 10 'may be a single crystal silicon wafer, and the second semiconductor layer 20' uses the first semiconductor layer 10 '(ie, wafer) as the seed layer. It may be a single crystal silicon epitaxial layer formed through an epitaxial process. In example embodiments, each of the semiconductor layers 10 ′ and 20 ′ may include a cell array having substantially the same structure, and the memory cells may form a multi-layer cell array 110_1.

Each of the semiconductor layers 10 ′ and 20 ′ may have active regions defined by well-known device isolation layer patterns 15. The active regions may be formed parallel to each other along one direction. The device isolation layer patterns 15 may be made of insulating materials including a silicon oxide layer and may electrically separate the active regions.

On top of each of the semiconductor layers 10 'and 20', a gate structure composed of a pair of selection lines GSL, SSL and M word lines WL across the active regions is provided. Can be deployed. Source plugs 50 ′ may be disposed on one side of the gate structure, and bit line plugs 40 ′ may be disposed on the other side of the gate structure. The bit line plugs 40 'may be connected to N bit lines BL, respectively, across the word lines WL. In this case, the bit lines BL may be formed to cross the word lines WL on the uppermost semiconductor layer (eg, the second semiconductor layer 20 ′ in FIG. 13). The number N of bit lines BL may be an integer greater than 1, and preferably one of multiples of eight.

The word lines WL are disposed between the selection lines GSL and SSL, and the number M of the word lines WL constituting the gate structure is an integer greater than one. Preferably, the integer M may be one of multiples of eight. One of the selection lines GSL and SSL may be used as a ground selection line GSL that controls electrical connection between the common source line CSL and the memory cells. The other one of the selection lines may be used as a string selection line SSL for controlling the electrical connection between the bit lines and the memory cells.

Impurity regions may be formed in the active region between the selection lines and the word lines. In this case, the impurity regions 11S and 21S formed at one side of the ground selection line GSL may be used as source electrodes connected by the common source line CSL, and one of the string selection line SSL may be used. The impurity regions 11D and 21D formed at the side may be used as drain electrodes connected to the bit lines BL through the bit line plugs 40 '. In addition, the impurity regions 11I and 21I formed at both sides of the word lines WL may be used as internal impurity regions that connect the memory cells in series.

Source plugs 50 ′ are formed in the first and second semiconductor layers 10 ′ and 20 ′ and are used as source electrodes to form impurity regions 11S and 21S (hereinafter, referred to as first and second source regions). ) May be electrically connected to the semiconductor layers 10 ', 20'. As a result, the first and second source regions 11S and 21S form an equipotential with the semiconductor layers 10 'and 20'. For this electrical connection, the source plugs 50 ′ may be connected to the first source region 11S through the second semiconductor layer 20 ′ and the second source region 21S. In this case, the source plug 50 ′ may directly contact the inner walls of the second semiconductor layer 20 ′ and the second source region 21S.

The flash memory of the stack flash structure shown in FIG. 13 may also be applied to the voltage generation method of the present invention described above, and the negative voltage and the positive voltage generated in the present invention are applied as a word line voltage to the flash memory shown in FIG. Can be. In addition, the negative voltage generation method of the present invention may be applied to a three-dimensional flash memory cell structure in which memory cells are three-dimensionally formed. The manufacturing technique of the three-dimensional flash memory device is not based on the method of repeating the step of forming the memory cells two-dimensionally, but because the word lines or word line planes are formed using a patterning process for defining an active region. As a result, the manufacturing cost per bit can be greatly reduced.

12 is a diagram illustrating a structure of a memory cell array according to another embodiment of the present invention. 12 illustrates an exemplary cell array 110_2 of a three-dimensional flash structure. Referring to FIG. 12, the cell array 110_2 of the flash memory of the present invention includes a plurality of word line planes WL_PT electrically separated from each other, and a plurality of word line planes arranged across the plurality of word line planes. It may include active pillars PL (or active regions). The semiconductor substrate may include a well region (Well) and a source region (S). The source region S may be formed to have a different conductivity type from that of the well region Well. For example, the well region Well may be made of p-type silicon, and the source region S may be made of n-type silicon. In an exemplary embodiment, the well region Well is surrounded by at least one other well region (not shown) having a conductivity type different from that of the well region Well, thereby providing a pocket well structure. structure or triple well structure.

Each word line plane WL_PT may be composed of a plurality of local word lines LWL electrically connected on a coplanar to have an equipotential. Each of the word line planes WL_PT may be electrically separated by an interlayer insulating film (not shown). Each of the word line planes WL_PT may be connected to each of the global word lines GWL electrically separated through the word line contacts WL_CT. The word line contacts WL_CT may be formed at edges of the memory cell array or array blocks, and the width of the word line planes WL_PT and the location where the word line contacts WL_CT are disposed may be configured in various forms. Can be.

Each active pillar PL has a body portion B adjacent to the well region Well and a drain region D adjacent the upper selection lone USLi (i is an integer less than or equal to N). ) May be included. The body portion B may be formed of the same conductivity type as the well region Well, and the drain region D may be formed of a different conductivity type than the well region Well. The plurality of active pillars PL may have long axes in a direction passing through the plurality of word line planes WL_PT. Intersections between the plurality of word line planes WL_PT and the plurality of active pillars PL may be three-dimensionally distributed. That is, each of the memory cells MC of the 3D memory may be formed by three-dimensionally distributed intersections. The gate insulating layer GI may be disposed between the word line plane WL_PT and the active pillar PL. In example embodiments, the gate insulating layer GI may be a multilayer, for example, a stack of ONO. Some of the gate insulating film may be used as a thin film (ie, a charge storage layer or a charge storage layer) for storing information.

One end of the active pillars PL may be commonly connected to the well region, and the other ends thereof may be connected to the plurality of bit lines BL. A plurality of (eg, N) active pillars PL may be connected to one bit line BL. Therefore, a plurality of (eg, N) cell strings CSTR may be connected to one bit line BL. In addition, one cell string CSTR may be configured in one active pillar PL. One cell string CSTR may include a plurality of memory cells MCs formed in the plurality of word line planes WL_PT. One memory cell MC may be defined by one active pillar PL and one local word line LWL or word line plane WL_PT.

In order to program each memory cell MC and read the programmed data, one cell string CSTR (that is, one active pillar PL) must be independently selected. To this end, a plurality of upper select lines USLi may be disposed between the bit lines BL and the highest word line plane WL_PT. The upper selection lines USLi may be disposed to intersect the bit lines BL. The bit lines BL may be electrically connected to the drain region D through a predetermined plug, and may be in direct contact with the drain region D.

A plurality of upper selection transistors controlling electrical connection between the corresponding active pillar PL and the corresponding bit line BL may be formed in an intersection area of the plurality of bit lines BL and the plurality of upper selection lines USLi. upper selection transistor) may be formed. The upper selection gate USGi of each upper selection transistor may be connected to a corresponding upper selection line USLi, respectively. As a result, one active pillar PL (that is, one cell string CSTR) may be independently selected by one bit line BL and one upper select line USLi.

As illustrated in FIG. 12, a source region S may be formed in the well region Well to form a charge path to / from the bit line BL. The source region S may be electrically connected to a common source line CSL. A source contact plug S_CT penetrating the word line planes WL_PT may be interposed between the common source line CSL and the source region S. FIG. The common source line CSL may be disposed on the bit lines BL through the source contact plug S_CT and may be formed of a metallic material. However, this corresponds to an example configuration of the common source line CSL, and the common source line CSL may be configured in various forms.

In order to control the charge path to / from the bit line BL, between the well region Well and the lowest word line plane WL_PT, the electrical connection between the active pillars PL and the well region Well is controlled. A plurality of lower selection lines LSL may be disposed. In an exemplary embodiment, the plurality of lower selection lines LSL may constitute a lower selection plate LS_PT having an electrically equipotential. Each of the lower selection lines LSL is applied to the lower selection gate LSGi of the corresponding lower selection transistor, respectively, so as to separate between the corresponding active pillar PL and the well region Well. The electrical connection can be controlled. The flash memory of the three-dimensional structure described above may also be applied to the voltage generation method of the present invention described above, and the negative word line voltage and the positive word line voltage generated in the present invention may be applied to the flash memory of FIG. It can be applied to the word line plane.

FIG. 13 is a diagram illustrating a configuration of a storage device 1500 including a flash memory device and a user device 1000 including the flash memory device according to the present invention.

Referring to FIG. 13, a user device 1000 of the present invention may be configured of a host 1300 and a data storage device 1500. The host 1300 may be configured to control the data storage device 1500. The host 1300 may include, for example, a portable electronic device such as a personal / portable computer, a personal digital assistant (PDA), a portable media player (PMP), an MP3 player, or the like. The host 1300 and the data storage device 1500 may be connected by a standardized interface such as a USB, SCSI, ESDI, SATA, SAS, PCI-express, or IDE interface. The interface method for connecting the host 1300 and the data storage device 1500 is not limited to a specific form and may be variously configured.

The data storage device 1500 may constitute a solid state disk or a solid state drive (SSD) device. In the present invention, a case in which the data storage device 1500 is configured of an SSD will be described as an example. However, this is only an example to which the present invention is applied, and the data storage device 1500 may be configured in various forms without being limited to an SSD. For example, the data storage device 1500 may be integrated into one semiconductor device, such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC), and a memory stick. , Multimedia cards (MMC, RS-MMC, MMC-micro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS), and the like.

The data storage device 1500 may include a memory controller 1200 and a flash memory 1100 that is a main storage unit. The memory controller 1200 may control a read / write / erase operation of the flash memory 1100 in response to a request from the host 1300.

The flash memory 1100 may include a plurality of nonvolatile memory chips, for example, a plurality of flash memory chips 100_1 to 100_4. The flash memory 1100 may include a plurality of channels. Each flash memory chip 100_1 to 100_4 may perform a read / write / erase operation in response to a request from the host 1300 provided through a corresponding channel.

The configuration and operation of each flash memory chip 100_1 to 100_4 are substantially the same as the flash memory 100 shown in FIG. 1. For example, each of the flash memory chips 100_1 to 100_4 may use a conductive floating gate blocked by an insulating layer as a charge storage layer, and replace Si3N4, Al2O3, HfAlO, HfSiO instead of the conventional conductive floating gate. An insulating film such as or the like may be used as the charge storage layer. The flash memory of the present invention may be composed of any one of a stack flash structure in which arrays are stacked in multiple layers, a flash structure without source-drain, a pin-type flash structure, and a three-dimensional flash structure.

In addition, the negative word line voltage and the positive word line voltage generation characteristics of each of the flash memory chips 100_1 to 100_4 are substantially the same as the negative voltage generation characteristics shown in FIGS. 5 to 12. For example, each of the flash memory chips 100_1 to 100_4 generates a plurality of negative voltages successively as a voltage to be applied to a word line, and has a configuration of converting the level of the generated negative voltage at high speed. In particular, when a second negative voltage having a level higher than the first negative voltage is generated after the first negative voltage is generated in each of the flash memory chips 100_1 to 100_4, the previously generated voltage (ie, the first negative voltage). ) Is discharged at a high speed for a predetermined time (Ref DT) (or after a certain voltage level is discharged), a negative charge pumping may be performed for a predetermined time (Ref PT) to generate a second negative voltage. According to such a configuration, each section for generating a negative voltage can be controlled at an optimized time, and a negative voltage of a desired level can be generated within a short time.

In the above, the negative voltage generation method when the negative verification voltage is continuously generated has been described as an example. However, this is only an example to which the present invention is applied, and the negative voltage generation method according to the present invention is not limited to a specific type of negative voltage (for example, a verification voltage and a read voltage), and various kinds of negative voltages. (E.g., various kinds of negative word line voltages) and various kinds of positive word line voltages. Therefore, according to the word line voltage generation method of the present invention, it is possible to convert the negative word line voltage and the positive word line voltage level at high speed, and to reduce the time required for the program. In addition, it is possible to efficiently perform a read operation and a verify operation on data states distributed in a negative voltage region and a positive voltage region.

14 is a block diagram illustrating a data storage device 2000 according to another exemplary embodiment. Referring to FIG. 14, the data storage device 2000 according to the present invention may include a memory controller 2200 and a flash memory 2100.

The flash memory 2100 shown in FIG. 14 is substantially the same as the flash memory 100 shown in FIG. 1, and the flash memory of the present invention has a stack flash structure in which arrays are stacked in multiple layers, a flash structure without source-drain , Pin-type flash structure, and three-dimensional flash structure. In addition, the negative word line voltage and the positive word line voltage generation characteristics of the flash memory 2100 illustrated in FIG. 16 are also substantially the same as the voltage generation characteristics illustrated in FIGS. 5 to 12. Therefore, redundant description is omitted below.

The memory controller 2200 may be configured to control the flash memory 2100. The memory controller 2200 may be configured in the same manner as the memory controller 1200 illustrated in FIGS. 1 and 13.

The SRAM 2230 may be used as a working memory of the CPU 2210. The host interface 2220 may include a data exchange protocol of a host connected to the data storage device 2000. The error correction circuit 2240 included in the memory controller 2200 may detect and correct an error included in read data read from the flash memory 2100. The memory interface 2260 may interface with the flash memory 2100 of the present invention. The CPU 2210 may perform various control operations for exchanging data of the memory controller 2200. Although not shown in the drawing, the data storage device 2000 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host.

The data storage device 2000 according to the present invention includes a computer, a portable computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA, a portable computer, a web tablet, a wireless device. Wireless phone, mobile phone, smart phone, digital camera, digital audio recorder, digital audio player, digital video recorder picture recorder, digital picture player, digital video recorder, digital video player, device that can send and receive information in wireless environment, and various user devices that make up home network It can be applied to one of these.

The data storage device 2000 may be applied to one of various user devices forming a computer network and may be applied to one of various user devices forming a telematics network. In addition, the data storage device 2000 may be applied to an RFID device or one of various components constituting the computing system (eg, a semiconductor drive (SSD), a memory card, etc.).

15 is a block diagram illustrating an example of a data storage device 3000 according to another exemplary embodiment. Referring to FIG. 15, the data storage device 3000 according to the present invention may include a flash memory 3100 and a flash controller 3200. The flash controller 3200 can control the flash memory 3100 based on control signals received from outside the data storage device 3000. [ The configuration and operation of the flash controller 3200 are substantially the same as the memory controllers 1200 and 2200 illustrated in FIGS. 13 and 14. Therefore, redundant description is omitted below.

In addition, the configuration of the flash memory 3100 is substantially the same as the flash memory 100 shown in FIG. 1, and the inventive flash memory includes a stack flash structure in which arrays are stacked in multiple layers, a flash structure without source-drain, and a pin. And a three-dimensional flash structure.

The data storage device 3000 of the present invention may constitute a memory card device, an SSD device, a multimedia card device, an SD device, a memory stick device, a hard disk drive device, a hybrid drive device, or a general-purpose serial bus flash device. For example, the data storage device 3000 of the present invention can configure a card that meets industry standards for using a user device such as a digital camera, a personal computer, and the like.

FIG. 16 is a diagram illustrating a schematic configuration of a flash memory device 4100 and a computing system 4000 including the same.

Referring to FIG. 16, a computing system 4000 according to the present invention includes a flash memory device 4100, a memory controller 4200, and a modem 4300 such as a baseband chipset electrically connected to a bus 4400. , Microprocessor 4500, and user interface 4600. The flash memory device 4100 shown in FIG. 16 is substantially the same as the flash memory 100 shown in FIG. 1, and the flash memory of the present invention has a stack flash structure in which arrays are stacked in multiple layers, and source-drain. One of a flash structure, a pin-type flash structure, and a three-dimensional flash structure.

When the computing system according to the present invention is a mobile device, a battery 4700 for supplying an operating voltage of the computing system may be additionally provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, or the like. The memory controller 4200 and the flash memory device 4100 may configure, for example, an SSD (Solid State Drive / Disk) that uses a nonvolatile memory to store data.

The nonvolatile memory device and / or memory controller according to the present invention may be mounted using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package ( It can be implemented using packages such as WSP).

As described above, the embodiments are disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100, 1100, 2100, 3100, 4100: flash memory device
110: cell array 111: cell string
120: row decoder 130: column decoder
140: write read circuit 150: voltage generator
151: high voltage generator 153: low voltage generator
155: negative voltage generator 160: voltage selection switch
170: control logic

Claims

In the method of programming a nonvolatile memory device:
Reading first page data from selected memory cells; And
Programming second page data into the selected memory cells with reference to the read first page data;
At least one of the memory cells having a threshold voltage corresponding to a first negative program state in the reading step is programmed to a second negative program state in the programming step. Program method.

The method of claim 1,
In the reading step, the read voltage for reading the memory cells includes at least one negative voltage.

The method of claim 2,
The programming step,
A program execution step of providing a program voltage to program the at least one memory cell into a second program state; And
Verifying that the at least one memory cell has been programmed to the second program state;
And at least one verify voltage used in the verify step is a negative voltage.

The method of claim 1,
And reading the memory cells with a verify read voltage that includes at least one negative voltage prior to programming the second page data.

The method of claim 4, wherein
Programming cells of the memory cells that have already been programmed to a second negative program state according to the verify read voltage are programmed prohibited in the programming step.

The method of claim 1,
A program method in which another one of memory cells having a threshold voltage corresponding to a first negative program state in the reading step is programmed to a positive program state in the programming step .

The method of claim 1,
And a voltage section provided between the erase state of the memory cells and 0V to accommodate the first negative program state or the second negative program state.

A cell array including a plurality of memory cells disposed in an intersection region of a plurality of word lines and a plurality of bit lines;
A voltage generator configured to provide a word line voltage to the plurality of word lines;
A write read circuit connected to the plurality of bit lines and configured to write or read data in selected memory cells; And
And control logic for controlling the voltage generator or the write read circuit to program selected memory cells of the plurality of memory cells from a first negative program state to a second negative program state.

The method of claim 8,
And the voltage generator generates negative verify read voltages for a verify read operation on the first negative program state or the second negative program state.

The method of claim 9,
And the voltage generator generates a first positive verify voltage for programming at least one of the memory cells corresponding to the first negative program state to a positive program state.