CN102446553B - Flash memory and word line voltage thereof generate method - Google Patents
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Abstract
The word line voltage of a kind of flash memory generates method and includes: use positive voltage maker to generate program voltage；Negative voltage generator is used to generate the multiple negative programming verifying voltage corresponding with multiple negative data states；And use described positive voltage maker to generate at least one or more programming verifying voltage corresponding with at least one or more state.Generate multiple negative programming verifying voltage to include: generate the first negative verifying voltage；The output of electric discharge negative voltage generator so that it is become to be above described first negative verifying voltage；And perform negative charge pump operation, until the output of negative voltage generator reaches the second negative verifying voltage level.
Description
Cross-Reference to Related Applications
This application claims the korean patent application the 10-2010-0095406th in JIUYUE in 2010 submission on the 30th, in 2010
Korean patent application the 10-2010-0130812nd that on December is submitted to for 20, the Korean Patent submitted on January 4th, 2011
Apply for No. 10-2011-0000609, on January 5th, 2011 submit to korean patent application the 10-2011-0001010th with
And the priority of the U.S. Provisional Patent Application the 61/447136th in submission on February 28th, 2011, by quoting in full it
It is herein incorporated.
Technical field
Inventive concept described herein relates to semiconductor storage unit, more particularly, to flash memory and word thereof
Line voltage generation method.
Background technology
Semiconductor storage unit can be categorized as volatile semiconductor memory part and non-volatile memory semiconductor device.
Volatile semiconductor memory part can perform at a high speed read and write operation, the content meeting being simultaneously stored therein when device power-off
Lose.Even if non-volatile memory semiconductor device can also retain the content wherein stored when power is off.For this reason,
Non-volatile memory semiconductor device may be used for storing the content that not tube device is switched on also being powered off all will retaining.
Non-volatile memory semiconductor device can include mask ROM (mask read-only memory,
MROM), programming ROM (PROM), erasable programmable ROM (EPROM), electrically erasable ROM (EEPROM) etc..
Flash memory can be typical nonvolatile semiconductor memory member.Flash memory can be widely used as such as
Computer, cell phone, PDA, digital camera, camcorder apparatus, voice recorder, MP3 player, Hand held PC, game machine, biography
Speech in the massaging device of prototype, scanner, printer etc. and image storage medium.This massaging device respectively can be by
Use hosted.
Day by day increase recently as to the demand of high integration memory device, in the memory unit storing multi-bit data
Many bit storage device become increasingly prevalent.
Summary of the invention
In the embodiment of present inventive concept, the word line voltage of a kind of flash memory generates method and includes: use positive electricity
Pressure maker generates program voltage；Use negative voltage generator to generate the multiple negative programming corresponding with multiple negative data states to test
Card voltage；And use described positive voltage maker to generate at least one or more corresponding with at least one or more state
Programming verifying voltage.Wherein, generate multiple negative programming verifying voltage and include: generating the first negative verifying voltage, electric discharge negative voltage is raw
The output grown up to be a useful person makes it become to be above the first negative verifying voltage, and it is straight to perform negative charge pumping (charge pumping) operation
Output to negative voltage generator reaches the second negative verifying voltage level.
In another embodiment of present inventive concept, the word line voltage of a kind of flash memory generates method and includes: use
Negative voltage generator generates the multiple negative read voltage corresponding with multiple negative data states；And use low-voltage maker raw
Become at least one or more positive read voltage corresponding with at least one or more correction data state.Wherein, multiple bearing is generated
Read voltage includes: generating the first negative read voltage, the output of electric discharge negative voltage generator is so that it becomes to be above the first negative reading
Power taking pressure, and perform negative charge pump operation until the output of negative voltage generator reaches the second negative read voltage level.
In another embodiment of present inventive concept, the word line voltage of a kind of flash memory generates method and includes: via
The negative charge pumping of negative voltage pump generates the first negative voltage；The output of electric discharge negative voltage pump；The electric discharge of negative voltage pump is exported with
The second negative voltage as target negative voltage compares；And if the electric discharge output of negative voltage pump is higher than the second negative voltage, then swash
Negative charge pumping alive is to generate the second negative voltage, wherein, activates the negative charge pumping electric discharge until negative voltage pump of negative voltage pump
Output and the second negative voltage are same or below the second negative voltage.
In another embodiment of present inventive concept, a kind of flash memory includes: memory cell array, it includes cloth
Put the multiple flash memory cells in multiple wordline Yu multiple bit line infalls；Voltage generating unit, it is configurable to generate many
The individual word line voltage that will be applied to that wordline；And control logic, its voltage being configured to control voltage generating unit generates
Operation, wherein, described voltage generating unit includes negative voltage generator, and it is configurable to generate the first negative voltage, electric discharge first
Negative voltage, and perform negative charge pumping until generating the second negative voltage higher than the first negative voltage.
In another embodiment of present inventive concept, a kind of flash memory includes: memory cell array, it includes cloth
Put the multiple flash memory cells in multiple wordline Yu multiple bit line infalls；Positive voltage maker, its be configurable to generate by
It is applied to the positive high voltage of selected word line and at least one or more corresponding with at least one or more data mode
Positive low-voltage；Negative voltage generator, it is configurable to generate corresponding with multiple negative data states and will be applied to that selected
Multiple negative voltages of wordline；And control logic, it is configured to control positive voltage maker and negative voltage generator, wherein,
When generating the second negative voltage after generating the first negative voltage less than the second negative voltage, negative voltage generator electric discharge negative voltage
The output of maker is to make it become to be above the second negative voltage, and performs the negative charge pumping output until negative voltage generator
Reach the second negative voltage.
In another embodiment of present inventive concept, a kind of data storage device include with multiple channel attached multiple soon
Flash memory；And controller, it is configured to via each in the respective channel the plurality of flash memory of control
Read, write and wipe operation.Wherein, each in the plurality of flash memory includes: memory cell array, and it includes
It is arranged in multiple flash memory cells of multiple wordline and multiple bit line infalls；Voltage generating unit, it is configurable to generate
Will be applied to that multiple word line voltages of wordline；And control logic, its voltage being configured to control voltage generating unit is raw
Becoming operation, wherein, described voltage generating unit includes negative voltage generator, and it is configurable to generate the first negative voltage, electric discharge the
One negative voltage, and generate the second negative voltage via negative charge pumping.
In another embodiment of present inventive concept, the word line voltage of a kind of flash memory generates method and includes: make
Program voltage is generated with positive voltage maker；Negative voltage generator is used to generate multiple negative programming verifying voltages；And just use
Voltage generator generates at least one or more and is just programming verifying voltage.Wherein, generate multiple negative programming verifying voltage to include:
Generate and before there is low level negative programming verifying voltage, generate the negative programming verifying voltage with high level.
In another embodiment of present inventive concept, the word line voltage of a kind of flash memory generates method and includes: raw
Become program voltage；Generate the first negative programming verifying voltage；Generate at least one corresponding with at least one data mode just to compile
Journey verifying voltage；And generate the second negative programming verifying voltage.
In another embodiment of present inventive concept, a kind of flash memory includes: memory cell array, it includes cloth
Put the multiple flash memory cells in multiple wordline Yu multiple bit line infalls；Voltage generating unit, its be configurable to generate by
It is applied to multiple word line voltages of described wordline；And control logic, its voltage being configured to control voltage generating unit
Generating operation, wherein, the negative wordline voltage that described voltage generating unit is sequentially generated from having maximum level is minimum to having
Multiple negative wordline voltage of the negative wordline voltage of level.
The flash memory of another embodiment according to present inventive concept includes: memory cell array, and it includes arranging
Multiple flash memory cells in multiple wordline Yu multiple bit line infalls；Voltage generating unit, it is configurable to generate quilt
It is applied to multiple word line voltages of described wordline；And control logic, its voltage being configured to control voltage generating unit is raw
Becoming operation, wherein, described voltage generating unit sequentially generates negative wordline voltage and positive word line voltage during programming verification operation.
The word line voltage of the flash memory of another embodiment according to present inventive concept generates method and includes: via negative electricity
The negative charge pumping of pressure maker generates the first negative verifying voltage；Discharged during the first discharge time the defeated of negative voltage generator
Go out；And generate the second negative verifying voltage via the negative charge pumping of negative voltage generator after the first discharge time, wherein,
Described first discharge time is determined according to the voltage difference between the first negative verifying voltage and the second negative verifying voltage.
In another embodiment of present inventive concept, the checking electricity of a kind of flash memory including negative voltage generator
Pressure generation method includes: generate the first negative verifying voltage via negative voltage generator；Discharged during the first discharge time negative electricity
The output of pressure maker；The second negative verifying voltage higher than the first negative verifying voltage is generated via negative voltage generator；Second
Discharge during discharge time the output of negative voltage generator；And generate higher than the second negative verifying voltage via negative voltage generator
The 3rd negative verifying voltage.
In another embodiment of present inventive concept, the verifying voltage of a kind of flash memory generates method and includes: via
The negative charge pump operation of negative voltage generator generates the first negative verifying voltage；And generate the higher than the first negative verifying voltage
Two negative verifying voltages and without negative charge pump operation, wherein set up (set up) according to the electric discharge of negative voltage generator described
Second negative verifying voltage.
According to another embodiment of present inventive concept, a kind of flash memory including positive voltage maker and negative voltage generator
The verifying voltage of memory device generates method and includes: use negative voltage generator to generate negative verifying voltage；By negative voltage generator
Output discharges into ground level；And generate positive verifying voltage via the positive charge pump operation of positive voltage maker.
In another embodiment of present inventive concept, a kind of flash memory includes: memory cell array, it includes cloth
Put the multiple flash memory cells in multiple wordline Yu multiple bit line infalls；Voltage generating unit, its be configurable to generate by
It is applied to multiple word line voltages of described wordline；And control logic, its voltage being configured to control voltage generating unit
Generating operation, wherein, described voltage generating unit was discharged the first negative voltage during discharge time, then generated negative higher than first
Second negative voltage of voltage, and wherein, described discharge time is according to the voltage difference between the first negative voltage and the second negative voltage
Determine.
In another embodiment of present inventive concept, a kind of data storage device includes: channel attached multiple with multiple
Flash memory；And controller, it is configured to control each in the plurality of flash memory via respective channel
Reading, write and wipe operation.Wherein, each in the plurality of flash memory includes: memory cell array, its bag
Include the multiple flash memory cells being arranged in multiple wordline with multiple bit line infalls；Voltage generating unit, it is configured to make a living
Become to will be applied to that multiple word line voltages of described wordline；And control logic, it is configured to control voltage generating unit
Voltage generates operation, and wherein, described voltage generating unit includes negative voltage generator, and wherein, when generate the first negative voltage,
When then generating the second negative voltage higher than the first negative voltage, described negative voltage generator is negative according to the first negative voltage and second
The outfan of discharge voltage signal generating unit during the discharge time that voltage difference between voltage determines, then generates the second negative electricity
Pressure.
Accompanying drawing explanation
From described below with reference to the following drawings, above-mentioned and other purpose and feature will be clear from, wherein, unless separately
Row explanation, the most similar reference refers to similar parts all the time.In accompanying drawing:
Fig. 1 is the block diagram of the flash memory illustrating the one exemplary embodiment according to present inventive concept；
Fig. 2 is the showing of the memory cell array that figure 1 illustrates illustrating the one exemplary embodiment according to present inventive concept
Figure；
Fig. 3 is the block diagram illustrating the negative voltage generator that figure 1 illustrates；
Fig. 4 is the circuit diagram illustrating the negative voltage detector 74 that figure 3 illustrates；
Fig. 5 is the block diagram illustrating the negative voltage generator for wordline that figure 3 illustrates；
Fig. 6 is the negative voltage generator that figure 3 illustrates illustrating another one exemplary embodiment according to present inventive concept
Block diagram；
Fig. 7 and Fig. 8 is the threshold voltage distribution of the multi-bit flash memory device illustrating that every unit stores 3 Bit datas
Diagram；
Fig. 9 is to illustrate that the threshold voltage when the threshold voltage of some memory element is distributed in negative voltage region is distributed, tests
Card voltage and the diagram of read voltage；
Figure 10 is the diagram for describing the programming operation using the verifying voltage in Fig. 9；
Figure 11 is the flow chart generating method for describing the negative voltage of the one exemplary embodiment according to present inventive concept；
Figure 12 and Figure 13 is the diagram illustrating the waveform generating the negative voltage that method generates according to negative voltage；
Figure 14 is to illustrate that the threshold voltage when the threshold voltage of some memory element is distributed in negative voltage region is distributed, tests
Card voltage and the diagram of read voltage；
Figure 15 is for describing the diagram of method generating the first to the 7th verifying voltage Vvfy1 to Vvfy7, wherein first
To the 7th verifying voltage Vvfy1 to Vvfy7, each corresponds to programming state ST0 to the ST7 shown in Figure 14；
Figure 16 is the flow chart generating method for describing the negative voltage of the one exemplary embodiment according to present inventive concept；
Figure 17 and Figure 18 is the diagram illustrating the waveform generating the negative voltage that method generates according to negative voltage；
Figure 19 is to illustrate that the threshold voltage when the threshold voltage of some memory element is distributed in negative voltage region is distributed, tests
Card voltage and the diagram of read voltage；
Figure 20 is to illustrate that the first to the 7th pre-authentication voltage Vvfy1_C being associated with programming state ST0 to ST7 arrives
The diagram of main verifying voltage Vvfy1_F to the Vvfy7_F of Vvfy7_C and first to the 7th；
Figure 21 is the diagram generating method for describing the word line voltage of the one exemplary embodiment according to present inventive concept；
Figure 22 is for describing showing of the word line voltage of another one exemplary embodiment according to present inventive concept generation method
Figure；
Figure 23 is for describing the first verifying voltage Vvfy1 shown in Figure 22 and the diagram of the second verifying voltage Vvfy2；
Figure 24 is the perspective view of the memory cell array of the one exemplary embodiment according to present inventive concept；
Figure 25 is the perspective view of the memory cell array of another one exemplary embodiment according to present inventive concept；
Figure 26 is that the data storage including flash memory illustrating the one exemplary embodiment according to present inventive concept sets
Standby block diagram；
Figure 27 is the block diagram of the data storage device illustrating another one exemplary embodiment according to present inventive concept；
Figure 28 is the block diagram of the data storage device illustrating another one exemplary embodiment according to present inventive concept；And
Figure 29 is the calculating system including flash memory illustrating the one exemplary embodiment according to present inventive concept
Block diagram.
Detailed description of the invention
It is described more fully with present inventive concept, shown in the drawings of the embodiment of present inventive concept now with reference to accompanying drawing.
But, present inventive concept can realize in many different forms, and is not intended to be limited to embodiments set forth herein.
On the contrary, these embodiments are provided so that the disclosure is more abundant and complete, and all sidedly to those skilled in the art
Pass on the scope of present inventive concept.In the accompanying drawings, for the sake of clarity, layer and the size in region and relative size may be put
Greatly.Similar reference refers to similar element all the time.
Although it will be appreciated that word first, second, third, etc. may be used to describe different element, assembly, district herein
Territory, layer and/or parts, but these elements, assembly, region, layer and/or parts are not so limited.These words
Language is used only for separating an element, assembly, region, layer or parts with another element, assembly, region, layer or component region
Come.Thus, the first element discussed below, assembly, region, layer or parts are referred to as the second element, assembly, region, layer
Or parts, without departing from the teaching of present inventive concept.
Describe for convenience, herein may use such as " under ", " lower section ", " being less than ", " below ", " top ", " on "
Etc. spatial relationship word shown in accompanying drawing a element or feature and other elements or the relation of feature are described.Will reason
Solution arrives, these spatial relationship words be intended to encompass in use or operate in device, except in accompanying drawing describe direction in addition to
Other directions.Such as, if upset accompanying drawing in device, then be described as be in other elements or feature " lower section " or " under "
Or the direction of the element of " below " will change " top " at other elements described or feature into.Thus, exemplary word " under
Side " and " below " upper and lower both direction can be comprised.Device is likely to have other towards (90-degree rotation or be in its other party
To), therefore should correspondingly explain spatial relation description word used herein.Additionally, it will also be understood that when one layer is referred to as in two-layer
Between " " time, it can be only layer between described two-layer, or can also there is one or more intervenient layer.
Term used herein is only used to describe specific embodiment, is not intended to limit present inventive concept.Make herein
Singulative " ", " being somebody's turn to do " be intended to also include plural form, unless context clearly provides contrary instruction.It will also be appreciated that
Arriving, when using term " to include " and/or time " comprising " in this specification, it shows to exist described feature, entirety, step, behaviour
Make, element and/or assembly, but do not preclude the presence or addition of other features one or more, entirety, step, operation, element,
Assembly and/or combinations thereof.Word "and/or" used herein includes any one in the Listed Items being correlated with or wherein
One or more whole combinations.
It will be appreciated that when element or layer be referred to as another element or layer " on ", or " being connected to ", " being coupled to " or
When " neighbouring " another element or layer, its can directly another element described or layer " on ", or be directly connected to, be coupled to or
Neighbouring another element described or layer, or element between two parties or layer can also be there is.On the contrary, it is referred to as " directly " separately when element
One element or layer " on " or " being directly connected to ", " being directly coupled to " or " next-door neighbour " another element or during layer, do not exist between two parties
Element or layer.
Unless otherwise defined, what all terms the most used herein (including technical term and scientific terminology) were had contains
Justice is identical with the implication that the those of ordinary skill in present inventive concept art is generally understood that.It will also be understood that term,
Those terms as defined in normally used dictionary, it should be interpreted had implication with they association area and/
Or the implication in the context of this specification is unanimously, and should ideally or too formally it not explained, unless
It is so defined the most clearly.
Fig. 1 is the block diagram of the flash memory illustrating the one exemplary embodiment according to present inventive concept.Fig. 2 is to illustrate root
Diagram according to the memory cell array in Fig. 1 of the one exemplary embodiment of present inventive concept.
With reference to Fig. 1, flash memory 100 can include memory cell array 110, line decoder 120, column decoder
130, read/write circuit 140, voltage generating unit 170, voltage selecting switch 180 and control logic 190.
Memory cell array 110 can be connected and via bit line BL and read/write circuit with line decoder 120 via wordline WL
140 connect.Memory cell array 110 can include the storage list arranged according to multiple row (or wordline) and multiple row (or bit line)
Unit.Multiple memory element in memory cell array 110 may be constructed multiple memory block.Schematically illustrate one in fig. 2
Individual memory block.Memory element in each memory block can be aligned to have NAND string structure as shown in Figure 2 or NOR structure
(not shown).
With reference to Fig. 2, multiple unit strings that each memory block can include being connected with bit line BL0 to BLm-1 respectively (or
NAND goes here and there) 111.Each unit string 111 can include at least one string select transistor SST, multiple memory element MC0 to MCn-
1 and at least one ground selection transistor GST.In each unit string 111, the drain electrode of string select transistor SST can be with phase
The bit line answered couples, and ground selects the source electrode of transistor GST can couple with common source polar curve CSL.At each unit string 111
In, memory element MC0 to MCn-1 can be connected in series in the source electrode of string select transistor SST and the leakage of ground selection transistor GST
Between pole.
Memory element MC0 to MCn-1 can be configured to store N-bit data message (N be 1 or bigger whole
Number).Memory element MC0 to MCn-1 can carry out stored bits information by charging injection in its charge storage layer.In demonstration
Property embodiment in, memory element MC0 to MCn-1 can use respectively by insulate membrane-enclosed conductive floating gates store as electric charge
Layer.In another one exemplary embodiment, memory element MC0 to MCn-1 can use such as Si3N4、Al2O3、HfAlO、HfSiO
Etc. dielectric film as charge storage layer.Use such as Si3N4、Al2O3, HfAlO, HfSiO etc. dielectric film as electric charge
The flash memory of accumulation layer can be referred to as charge trap-type quick flashing (charge trap flash, CTF) memorizer.As follows
The feature of described flash memory 100 goes for the flash memory using conductive floating gates as charge storage layer
With use dielectric film as the CTF memorizer of charge storage layer.
Additionally, memory cell array 110 can be to be configured with the multiple cell arrays including stacking in multilamellar mode
Stacking flash memory structure, without source-drain (source-drain free) flash memory structure, needle-like (pin-type) flash memory structure, three-dimensional
(or vertical-type) flash memory structure etc..
In fig. 2, the situation that flash memory 100 is formed is schematically illustrated by NAND type flash memory part.
But, present inventive concept is not limited to this.Such as, the feature of flash memory 100 goes for NAND flash
Device, NOR type flash memory part, include the mixing flash memory of at least two type memory device, which is embedded
Flash memory of controller etc..
As in figure 2 it is shown, can jointly couple with respective word with the control gate of the memory element in a line.String selects crystalline substance
Body pipe SST can be controlled by the voltage selecting line SSL to apply via string, and ground selects transistor GST can pass through warp
The voltage being selected line GSL to apply by ground controls.Memory element MC0 to MCn-1 can be by via respective word WL0 to WLn-
1 voltage applied controls.
Can store with each memory element being connected in wordline WL0 to WLn-1 with page, less than page subpage or
The data that multipage is corresponding.The reading of NAND type flash memory part and programming operation can be held in units of one page or multipage
OK.According to circumstances need, read and programming operation can perform according to subpage.The erasing operation of NAND type flash memory part
Can carry out according to by the multiple pages of blocks formed.
Return to Fig. 1, control that logic 190 can control flash memory 100 with programming, read and wipe operation phase
The overall operation closed.According to operator scheme, voltage generating unit 170 can be configurable to generate and will be supplied to the wordline of wordline
Voltage and the voltage of memory bank (bulk) (such as, well area) will be supplied to.It is known that can be at memory bank, i.e. well region
Memory element is formed at territory.Voltage generating unit 170 can operate in response to the control controlling logic 190.
Voltage generating unit 170 can include high voltage maker 171, low-voltage maker 173 and negative voltage generator
175.High voltage maker 171 can be configured to respond to control the control of logic 190 and generate driving flash memory 100
Required positive high voltage.The positive high voltage generated from high voltage maker 171 can be used as program voltage when programming operation
Vpgm, by voltage Vpass etc..
Low-voltage maker 173 can be configured to respond to control the control of logic 190 and generate driving flash memory
Positive low-voltage needed for part 100.The positive low-voltage generated from low-voltage maker 173 can programming or during read operation by with
Make read voltage Vrd, verifying voltage Vvfy, decoupling voltage (decoupling voltage), blocking voltage (blocking
Voltage) etc..In the present embodiment, the positive pumping behaviour of low-voltage maker 173 can be performed after order has inputted
Make, and can regulate, by using multiple resistors to align pumping result dividing potential drop, the reading generated from low-voltage maker 173
Power taking pressure Vrd, verifying voltage Vvfy, the level of decoupling voltage, blocking voltage etc..In which case it is possible to use adjust
Code (trim code) controls positive word line voltage, in order to the required level of output.
Negative voltage generator 175 can be configured to generate according to the control controlling logic 190 drive flash memory
Negative voltage needed for 100.Can be used as reading when programming or read operation from the negative voltage that negative voltage generator 175 generates
Voltage Vrd, verifying voltage Vvfy, decoupling voltage, blocking voltage etc..
Memory bank (the example forming memory element wherein can be supplied to from the negative voltage of negative voltage generator 175 generation
As, well area).Hereinafter, can be applied to wordline for driving the voltage of flash memory 100 to be referred to as word line voltage.
The output of high voltage maker 171 and low-voltage maker 173 can be sent to voltage selecting switch 180, and
The output of negative voltage generator 175 can be sent to voltage selecting switch 180 and line decoder 120.
Here, high voltage maker 171 and low-voltage maker 173 can realize with a voltage generator.At this
In the case of Zhong, owing to high voltage maker 171 and low-voltage maker 173 generate positive voltage, therefore they can use positive voltage
Maker represents.It is to say, voltage generating unit 170 can be raw by positive voltage maker (171 and 173) and negative voltage
Grow up to be a useful person 175 formation.
Line decoder 120 can couple with voltage selecting switch 180 and memory cell array 110.Line decoder 120 is permissible
It is configured to respond to control the control of logic 190 and operate.Line decoder 120 can decode the row ground received from external equipment
Location X-ADDR.Line decoder 120 can select wordline WL according to the decoding result of row address X-ADDR.Line decoder 120 is permissible
The output of voltage selecting switch 180 is sent to selected word line and unselected word line.
Voltage selecting switch 180 can couple with voltage generating unit 170, line decoder 120 and control logic 190.Electricity
Pressure selects to switch 180 can be in response to one of control output voltage selecting voltage generating unit 170 controlling logic 190.Can
It is supplied to corresponding wordline WL via line decoder 120 with the voltage selected by voltage selecting switch 180.
In the present embodiment, voltage selecting switch 180 can use transistor as switch element or transmission gate
(transfer gate).Such as, voltage selecting switch 180 can make field-effect transistors FET as switch element or transmission
Door.
If have selected the output of negative voltage generator 175, then voltage selecting switch according to the control controlling logic 190
The negative voltage that negative voltage generator 175 generates can be sent to line decoder 120 by 180.Can be used to from negative voltage generator
The negative voltage bias voltage selecting switch 180 of 175 and the well area of line decoder 120, in order to will be negative via field-effect transistor
Voltage sends line decoder 120 to.
If deexcitation, then negative voltage generator 175 can generate ground voltage in response to the control controlling logic 190.?
When sending high voltage or low-voltage to wordline via voltage selecting switch 180 and line decoder 120, can generate with negative voltage
The ground voltage bias voltage that device 175 generates selects switch 180 and the well area of line decoder 120.
Column decoder 130 can couple with read/write circuit 140.Column decoder 130 can be configured to respond to control and patrol
Collect the control of 190 and operate.Column decoder 130 can decode column address Y-ADDR received from external equipment.Can be by row ground
The decoding result of location Y-ADDR is supplied to read/write circuit 140.
Read/write circuit 140 can operate in response to the control controlling logic 190, and can use according to operator scheme
Make sensing amplifier or write driver.Such as, during checking reading/normal read operation, read/write circuit 140 can be used
Make sensing amplifier, for reading data from memory cell array 110.During normal read operation, via read/write circuit
140 data read can export external equipment (such as, storage control or main frame).During checking read operation, warp
What the data read by read/write circuit 140 can be supplied in flash memory 100 pass through/unsuccessfully check that circuit (does not shows
Go out), to judge that whether memory element is by normal program.
During programming operation, read/write circuit 140 can serve as write driver, for according to being stored in storage
Data-driven bit line BL0 to BLm-1 in cell array 110.During programming operation, read/write circuit 140 can be from buffer
(not shown) receives and will be written into the data of memory cell array 110, and can arrive according to the data-driven bit line BL0 of input
BLm-1.Read/write circuit 140 can include multiple page buffer PB, each page buffer PB and row (or, bit line) or row
Corresponding, as shown in Figure 2 to (or, bit line to).Each page buffer can include multiple latch, for latching sense
Data and/or latch will be programmed that data.
Fig. 3 is the block diagram illustrating the negative voltage generator that figure 1 illustrates.
With reference to Fig. 3, negative voltage generator 175 can include direct current (DC) voltage generator 71, reference voltage maker 72,
Agitator (OSC) 73, negative voltage detector 74, negative voltage pump 75 and the negative voltage generator 76 for wordline.
DC voltage maker 71 can be configurable to generate DC voltage VDC_NEG, and reference voltage maker 72
Reference voltage Vref _ NEG can be configurable to generate.
Agitator 73 can generate the clock CLK_NEG for negative voltage.In the present embodiment, the week of clock CLK_NEG
Phase can be 30ns (nanosecond).Here, agitator 73 may be implemented as independent of the high voltage maker 171 shown in Fig. 1
Agitator.In another embodiment, the agitator of the high voltage maker 171 shown in Fig. 1 can be used as negative voltage raw
Grow up to be a useful person 175 agitator 73.
Negative voltage detector 74 can receive DC voltage VDC_NEG and clock CLK_NEG, and can detect for trap
The negative voltage NWELL of voltage is to generate the clock CLK_NEGP for negative voltage pump.
Negative voltage detector 74 can include discharge component 743, and can be configured to the negative voltage that optionally discharges
NWELL.Such as, controlling logic 190 can at the level of the electric discharge result of discharge component 743 higher than reference voltage Vref _ NEG also
And the level of this electric discharge result equal to or less than ground voltage time, deexcitation discharge component 743.Alternatively, controlling logic 190 can
With during the scheduled time, perform discharge component 743 discharge operation after deexcitation discharge component 743.If by electric discharge
The discharge operation negative voltage NWELL of parts 743 gets lower than reference voltage Vref _ NEG, then can activate the negative of negative voltage pump 75
Voltage pump operates.
The negative voltage NWELL generated from negative voltage pump 75 and the use using negative voltage NWELL to generate can be changed rapidly
Level in the negative voltage NWL of wordline.This means to minimize the time that programming operation is spent.
In the present embodiment, the level of the electric discharge result of discharge component 743 can higher than with target negative voltage (TNV1,
TNV2 etc.) corresponding reference voltage Vref _ NEG.In another embodiment, the level of the electric discharge result of discharge component 743
Can be higher than the reference voltage Vref _ NEG corresponding with target negative voltage (TNV1, TNV2 etc.) and equal to or less than ground electricity
Pressure.But, discharge component 743 level of the voltage discharged is not limited to this.
Negative voltage pump 75 can generate the negative voltage NWELL for trap voltage in response to clock CLK_NEGP.Negative voltage
NWELL can be applied to the circuit (not shown) by applying negative voltage to it.Negative voltage NWELL is sensitive to external factor.Example
As, trap voltage NWELL can be affected by trap electric capacity.Bearing for wordline can be provided between negative voltage pump 75 and wordline
Voltage generator 76, for stably supplying negative voltage to wordline.
Negative voltage generator 76 can receive trap voltage NWELL, DC voltage VDC_NEG and reference voltage Vref _ NEG,
And the negative voltage NWL that will be applied to that wordline can be generated.Negative voltage NWL can be applied at least one wordline and with
At least one circuit (such as, selecting line) that at least one wordline described is corresponding.
Negative voltage generator 76 can include discharge component 763, and can be configured to the negative voltage that optionally discharges
NWL.According to the discharge operation of discharge component 763, owing to applying negative voltage NWL from negative voltage generator 76 to wordline, therefore may be used
To avoid the impact of word line capacitance.The discharge operation of discharge component 763 can also perform at short notice, and discharge component
The level of the voltage of 763 electric discharges is not limited to present disclosure.
According to above-mentioned negative voltage generator 175, can differently determine the relation between negative voltage NWELL and NWL.Example
As, negative voltage NWELL and NWL can be determined that have identical level.Alternatively, negative voltage NWELL and NWL can be by
It is defined as the skew with particular level.It is to say, negative voltage NWELL and NWL can be determined that the skew keeping 0.5V.
Or, alternatively, negative voltage NWELL can have the fixed level in negative voltage range, and negative voltage NWL can be changed
To have different level.
Fig. 4 is the circuit diagram illustrating the negative voltage detector 74 that figure 3 illustrates.
With reference to Fig. 4, negative voltage detector 74 can include power supply unit 741, dividing potential drop parts 742, discharge component 743, ratio
Relatively parts 747 and control parts 744.
Power supply unit 741 can enable signal NV_EN in response to negative voltage and determine the supply of DC voltage VDC_NEG.Electricity
Source block 741 can include PMOS transistor PM and resistor R1.The grid of PMOS transistor PM can be connected to receive negative electricity
Pressure enables the inversion signal (inverted version) of signal NV_EN.Resistor R1 can be connected to PMOS transistor PM
Between one end and comparison node NC.When power supply unit 741 is activated, with DC voltage VDC_NEG and the electricity of comparison node NC
The corresponding electric current of difference between pressure can flow through resistor R1.
Dividing potential drop parts 742 can be configured to DC voltage VDC_NEG dividing potential drop.Dividing potential drop parts 742 can include resistance
Device R2 to R5, high voltage transistor HM0 to HM2 and level shifter LS0 to LS2.
Resistor R2 to R5 can be connected in series between node NC and ND.Three resistors in resistor R2 to R5
R2, R3 and R4 can be configured to be shorted according to corresponding adjustment code TRM0 to TRM2 and nTRM0 to nTRM2.But, joined
The quantity of the resistor being set to short circuit is not limited to this.Such as, at least one resistor can be configured to according at least one
Adjust code and be shorted.
First high voltage transistor HM0 can be connected in parallel with resistor R4, and the second high voltage transistor HM1 can be with electricity
Resistance device R3 is connected in parallel, and the 3rd high voltage transistor HM2 can be connected in parallel with resistor R2.Can be to first to the 3rd
The main body of high voltage transistor HM0 to HM2 (or, trap) the negative voltage NWELL for trap voltage is provided.
First level shifter LS0 can include receiving the positive input terminal In of adjustment code TRM0, receiving anti-phase adjustment code
The negative input end nIn of nTRM0, the trap voltage input end Vneg receiving trap voltage NWELL and output are relative with adjusting code TRM0
The outfan Out of the level answered.The outfan Out of the first level shifter LS0 can be with the grid of the first high voltage transistor HM0
Pole connects.Second can be configured to the 3rd level shifter LS1 with LS2 identical with the first level shifter LS0.
Discharge component 743 can be configured to respond to negative voltage and enable the inversion signal discharge examination joint of signal NV_EN
The negative voltage NWELL of some ND.Discharge component 743 can be connected to detect between node ND and earth terminal.In the present embodiment, put
Electricity parts 743 can include nmos pass transistor HNM.Here, nmos pass transistor HNM can be high voltage transistor.NMOS crystal
The main body of pipe HNM can couple with detection node ND.If the electricity by the discharge operation negative voltage NWELL of discharge component 763
Put down and get lower than reference voltage Vref _ NEG, then can activate the negative voltage pump operation of negative voltage pump 75.Therefore, it can quickly
The level of the negative voltage that ground conversion generates one by one.But, discharge component 763 level of the voltage discharged does not limits to
In this.
Comparing unit 747 can compare the voltage of the reference voltage Vref _ NEG for negative voltage and comparison node NC, with
Generate the clock CLK_NEGP for negative voltage as comparative result.Comparing unit 747 can include comparator 748 and logic
Operator 749.Comparator 748 can include the positive input terminal receiving reference voltage Vref _ NEG and receive the voltage of comparison node NC
Negative input end.In the present embodiment, comparator 748 can realize with differential amplifier.Logical operator 749 can perform logic
Or (OR) operation, when it can enable signal NV_EN generation in response to clock CLK_NEG, the output of comparator 748 and negative voltage
Clock CLK_NEGP.
Control parts 744 and can determine power supply unit 741 and discharge component 743 in response to negative voltage enable signal NV_EN
Activation.Control parts 744 and can include the first phase inverter the 745, second phase inverter 746 and level shifter LS.First is anti-phase
It is anti-phase that negative voltage can be enabled signal NV_EN by device 745.The output of the first phase inverter 745 can be applied to power supply unit 741
The grid of PMOS transistor PM.Second phase inverter 746 can be by anti-phase for the output of the first phase inverter 745.Level shifter LS
The level conversion of the output of the second phase inverter 746 can be become high-tension level.Can second anti-phase by through level conversion
The output of device 746 is applied to the grid of the nmos pass transistor HNM of discharge component 743.
Level shifter LS can include receiving the positive input terminal In of the output of the first phase inverter 745, to receive second anti-phase
The negative input end nIn of the output of device 746, receive the trap voltage input end Vneg of the negative voltage NWELL for trap voltage and defeated
Go out to hold Out.Level shifter LS may be implemented as identical with the first level shifter LS0 of dividing potential drop parts 742.
As will be described below, control as the predetermined reference time RefPT by arranging in being spaced in negative voltage pumping
Wherein when negative voltage generator 175 generates the interval of negative voltage NWL and NWELL, negative voltage generator 175 can be removed
Voltage detector 74.In such a case, it is possible to simplify negative charge pump pump circuit and control method thereof.Therefore, it can at optimum
Negative charge pumping is carried out efficiently in the time changed.
Fig. 5 is the block diagram illustrating the negative voltage generator for wordline in Fig. 3.
With reference to Fig. 5, negative voltage detector 76 can include power supply unit 761, dividing potential drop parts 762, discharge component 763, ratio
Relatively parts 764 and control parts 765.
Power supply unit 761 can enable signal NV_EN in response to negative voltage and determine the supply of DC voltage VDC_NEG.Electricity
Source block 761 can include PMOS transistor PM_W and resistor R1W.The grid of PMOS transistor PM_W can be connected to receive
Negative voltage enables the inversion signal of signal NV_EN.Resistor R1_W can be connected to one end of PMOS transistor PM_W and compare
Between node NC_W.When power supply unit 761 is activated, and between DC voltage VDC_NEG and the voltage of comparison node NC_W
The corresponding electric current of difference can flow through resistor R1_W.
Dividing potential drop parts 762 can be configured to DC voltage VDC_NEG dividing potential drop.Dividing potential drop parts 762 can include resistance
Device R2_W to R5_W, the first to the 3rd high voltage transistor HM0_W to HM2_W and the first to the 3rd level shifter LS0_W
To LS2_W.
Resistor R2_W to R5_W can be connected in series between node NC_W and NO_W.In resistor R2_W to R5_W
Three resistors (such as, R2_W, R3_W and R4_W) can be configured to according to corresponding adjustment code TRM0_W to TRM2_W
It is shorted.But, the quantity of the resistor being configured to short circuit is not limited to this.Such as, at least one resistor can be joined
It is set to adjust code according at least one and be shorted.
First high voltage transistor HM0_W can be connected in parallel with resistor R4_W, and the second high voltage transistor HM1_W can
To be connected in parallel with resistor R3_W, and the 3rd high voltage transistor HM2_W can be connected in parallel with resistor R2_W.Permissible
There is provided for trap voltage from the main body of negative voltage pump 75 to first to the 3rd high voltage transistor HM0_W to HM2_W (or, trap)
Negative voltage NWELL.
First level shifter LS0_W can include receiving the positive input terminal In of adjustment code TRM0_W, receiving anti-phase adjustment
The negative input end nIn of code nTRM0_W, the trap voltage input end Vneg receiving trap voltage NWELL and output and adjustment code
The outfan Out of the level that TRM0_W is corresponding.The outfan Out of the first level shifter LS0_W can be with the first high voltage
The grid of transistor HM0_W connects.Second and the 3rd level shifter LS1_W and LS2_W can be configured to and the first level
Shifter LS0_W is identical.
Discharge component 763 can be configured to respond to negative voltage and enable the inversion signal electric discharge output joint of signal NV_EN
The negative voltage NWL (wordline will be supplied to) of some NO_W.Discharge component 763 can be connected to output node NO_W and earth terminal it
Between.In the present embodiment, discharge component 763 can include nmos pass transistor HNM_W.Here, nmos pass transistor HNM_W can be
High voltage transistor.The main body of nmos pass transistor HNM_W can be connected to receive trap voltage NWELL.
Comparing unit 764 can compare the reference voltage Vref _ NEG for negative voltage and the voltage of comparison node NC_W.
Comparative result can be supplied to the grid of nmos pass transistor HNM by comparing unit 764.Can be cut by nmos pass transistor HNM
Change trap voltage NWELL and word line voltage NWL.
Comparing unit 764 can include the negative input end receiving reference voltage Vref _ NEG and receive comparison node NC_W
The positive input terminal of voltage.In the present embodiment, comparing unit 764 can realize with differential amplifier.
Control parts 765 and can determine the activation of discharge component 763 in response to negative voltage enable signal NV_EN.Control portion
Part 765 can include the first phase inverter the 766, second phase inverter 767 and level shifter LS_W.First phase inverter 766 can be by
It is anti-phase that negative voltage enables signal NV_EN.Second phase inverter 767 can be by anti-phase for the output of the first phase inverter 766.Level shifter
The level conversion of the output of the second phase inverter 767 can be become high-tension level by LS_W.Can be by through the second of level conversion
The output of phase inverter 767 is applied to the grid of the nmos pass transistor HNM_W of discharge component 763.
Level shifter LS_W can include receiving the positive input terminal In of the output of the first phase inverter 766, to receive second anti-
The negative input end nIn of the output of phase device 767, receive the negative voltage NWELL for trap voltage trap voltage input end Vneg and
Outfan Out.Level shifter LS_W may be implemented as identical with the first level shifter LS0_W of dividing potential drop parts 762.
As it is shown on figure 3, can include for word according to the negative voltage generator 175 of the one exemplary embodiment of present inventive concept
The negative voltage generator 76 of line, it is configurable to generate the negative voltage NWL being applied to wordline.But, according to present inventive concept
One exemplary embodiment, negative voltage generator 76 is not required to be included in negative voltage generator 175.
Fig. 6 is the block diagram of the negative voltage generator 175_1 illustrating another one exemplary embodiment according to present inventive concept, should
Negative voltage generator 175 shown in the alternative Fig. 3 of negative voltage generator 175_1.
DC voltage maker 71, reference voltage maker 72 can be included with reference to Fig. 6, negative voltage generator 175_1, shake
Swing device 73, negative voltage detector 74 and negative voltage pump 75.In addition to eliminating for the negative voltage generator 76 of wordline, Fig. 6
In negative voltage generator 175_1 can be substantially identical with shown in Fig. 3, therefore omit descriptions thereof.In this situation
Under, the output voltage of negative voltage pump 75 can be provided jointly to trap and wordline.
Fig. 7 and Fig. 8 is the threshold voltage distribution of the multi-bit flash memory device illustrating that every unit stores 3 Bit datas
Diagram.
With reference to Fig. 7, if memory element storage K bit data, then it can be programmed with 2K threshold value electricity
One of pressure distribution (being such as, 8 in the case of K=3).Due to the trickle electrical characteristics difference of memory element, the threshold of memory element
Threshold voltage may form the threshold voltage distribution with the preset range corresponding with programming state ST0 to ST7 respectively.
In the ideal case, shown in solid as in Fig. 7, a threshold voltage distribution can be distributed with neighboring threshold voltage
Compartment of terrain is separately.This means to there is read margin between neighboring threshold voltage is distributed.The threshold voltage of each memory element
The level voltage regime higher than the programming verifying voltage of corresponding programming state can be distributed in.
The quantity of programming state (that is, the quantity of threshold voltage distribution, the distribution of described threshold voltage respectively with programming state phase
Corresponding) increase can be proportional to the increase of the bit number that can store in the memory unit.May insure that threshold voltage window
Mouthful with provide sufficient read margin and with every cell bit number corresponding threshold voltage distribution number.It is known that the use in Fig. 7
It is probably limited in threshold voltage window D1 arranging threshold voltage distribution.If to this end, every cell bit number (or, K) increase
Add, then the distance (or, allowance) between neighboring threshold voltage distribution can reduce.
As represented by the dotted line in Fig. 7, when realizing multi-bit flash memory device, data mode (or, program shape
State) threshold voltage distribution may become non-ideal shape.Along with every cell bit number increases, this phenomenon will become the tightest
Weight.Additionally, due to a variety of causes, as loss of charge, time passage, temperature increase, programming time consecutive storage unit between coupling
Close, to the reading of consecutive storage unit, the defect etc. of memory element, this phenomenon may become more serious.Threshold value electricity
The change of pressure distribution may cause read error.By as shown in Figure 8 the threshold voltage of some memory element being arranged in negative electricity
Intermediate pressure section can avoid this problem.
Threshold voltage window can be made by as shown in Figure 8 the threshold voltage of some memory element being arranged in negative voltage region
Mouth is widened to D2 (D2 ＞ D1) from D1.This have the advantage that, by threshold voltage window D2 widened, it is ensured that programming shape
Broader allowance between state.The negative voltage region of threshold voltage window D2 is the widest, and threshold voltage window D2 is the widest.Additionally, such as
When fruit extends the negative voltage region of threshold voltage window D2, then negative voltage generator 175 can be used to generate various negative electricity piezoelectricity
Flat.In such a case it is necessary to generate various negative voltage level at a high speed.
Fig. 9 is to illustrate that the threshold voltage when the threshold voltage of some memory element is distributed in negative voltage region is distributed, tests
Card voltage and the diagram of read voltage.Figure 10 is the diagram for describing the programming operation using the verifying voltage in Fig. 9.
In fig .9, transverse axis can represent the threshold voltage of memory element, and the longitudinal axis can represent the quantity of memory element.?
In Fig. 9, schematically illustrate memory element have erasing state ST0, the first programming state ST1, the second programming state ST2 and
The situation of the 3rd programming state ST3.But, present inventive concept is not limited to this.Logic state ST0 of memory element can be arrived
The quantity of ST3 and logic state carries out various change.
Owing to flash memory 100 not being written over, memory element therefore can be wiped before the programming operation.Also
That is, memory element can be configured so that have erasing state ST0 before programming.Memory element can be assigned to be had
Threshold voltage distribution in Fig. 9.This can be by erasing memory element to make it have level less than erasing verifying voltage Vvfye
Threshold voltage (or, distributed threshold voltage distribution ST0 in) realize.Be wiped free of to have erasing state ST0 it
After, memory element can be programmed to make it have one of first to the 3rd programming state ST1 to ST3.Here, there is the first volume
The level of the threshold voltage of the memory element of journey state ST1 can be higher than the first verifying voltage Vvfy1.There is the second programming state
The level of the threshold voltage of the memory element of ST2 can be higher than the second verifying voltage Vvfy2.Have the 3rd programming state ST3's
The level of the threshold voltage of memory element can be higher than the 3rd verifying voltage Vvfy3.If it is complete to the programming operation of memory element
Become, then can be read the data of data/logic/programming state ST0 to ST3 by normal read operation.As it is shown in figure 9, just
Often in read operation, it is possible to use the first to third reading power taking pressure Vrd1 to Vrd3 distinguishes data mode ST0 to ST3.
In the present embodiment, the first and second read voltage Vrd1 and Vrd2 can be negative voltages.Second read voltage
The level of Vrd2 can be higher than the first read voltage Vrd1.Third reading power taking pressure Vrd3 can be positive voltage.Third reading power taking pressure
The level of Vrd3 can be higher than the second read voltage Vrd2.Such as, third reading power taking pressure Vrd3 can be positive low-voltage.Can root
Third reading power taking pressure Vrd3 is generated from low-voltage maker 173 according to the control of the control logic 190 in Fig. 1.Can be according to control
The control of logic 190 generates the first read voltage Vrd1 and the second read voltage Vrd2 from negative voltage generator 175.
In the case of Fig. 9, negative voltage generator 175 can be configured under the control controlling logic 190, generate
The second read voltage Vrd2 is generated without delay after first read voltage Vrd1.Alternatively, negative voltage generator 175 is permissible
It is configured under the control controlling logic 190, after generating the second read voltage Vrd2, generates the first read voltage Vrd1.
Can control logic 190 control under differently determine generate by continuous read operation apply read voltage time
Sequence.
Such as, if generating the second read voltage Vrd2 without delay after generating the first read voltage Vrd1, then bear
The output of voltage generator 175, the i.e. first read voltage Vrd1 can be discharged into a certain level, then by negative charge pumping
Operation generates the second read voltage Vrd2.Can make to shorten in this way and change the time that negative voltage level is spent.
In the present embodiment, the electric discharge of negative voltage generator 175 can be realized by the discharge component 743 in negative voltage detector 74
Operation, in order to proceed negative charge pump operation.Additionally, due to by the discharge component 763 in negative voltage generator 76
Discharge operation applies negative voltage (such as, the first read voltage Vrd1), and therefore negative voltage generator 175 can eliminate wordline electricity
The impact held.
According to the one exemplary embodiment of present inventive concept, can realize rapidly from low negative voltage level to high negative electricity piezoelectricity
Flat negative voltage switching.Furthermore, it is possible to effectively eliminate the impact of the word line capacitance caused by the negative voltage applied in the past.
If generating the first read voltage Vrd1 without delay after generating the second read voltage Vrd2, then can pass through
Negative charge pump operation generate the first read voltage Vrd1 and without to the output of negative voltage generator 175, (namely second reads
Power taking pressure Vrd2) carry out discharge operation.As described above, can be according to the lever selection of the negative read voltage being sequentially generated
Ground performs discharge operation.It means that the negative voltage of varying level can be quickly generated.
With reference to Fig. 9 and Figure 10, flash memory 100 incrementally can program (incremental by step-by-step impulse
Step pulse programming, ISPP) mode performs programming operation, in order to accurately control threshold voltage distribution.Such as figure
Shown in 10, according to ISPP mode, program voltage Vpgm can increase increment Delta Vp steppingly when program cycles repeats.Often
Individual program cycles, whenever being applied with program voltage Vpgm_i (i=0～N), all use the first to the 3rd verifying voltage Vvfy1,
Vvfy2 and Vvfy3 performs three checking read operations.
Program voltage Vpgm0 to VpgmN can be positive high voltage.In the present embodiment, can be in the control controlling logic 190
Program voltage Vpgm0 to VpgmN is generated from high voltage maker 171 under system.
In the present embodiment, the first and second verifying voltage Vvfy1 and Vvfy2 can be negative voltage.Second verifying voltage
The level of Vvfy2 can be higher than the first verifying voltage Vvfy1.Can be from negative voltage generator under the control controlling logic 190
175 generate the first verifying voltage Vvfy1 and the second verifying voltage Vvfy2.3rd verifying voltage Vvfy3 can be positive low-voltage.
The level of the 3rd verifying voltage Vvfy3 can be higher than the second verifying voltage Vvfy2.Can control logic 190 control under from
Low-voltage maker 173 generates the 3rd verifying voltage Vvfy3.
In the case of the programming mode of Figure 10, negative voltage generator 175 can be configured in the control controlling logic 190
Under system, after generating the first verifying voltage Vvfy1, generate the second verifying voltage Vvfy2 without delay.Generating to reduce
The time that the second verifying voltage Vvfy2 is spent is generated after first verifying voltage Vvfy1, can be by negative voltage generator 175
Output repid discharge to a certain level, may then pass through negative charge pump operation and generate the second verifying voltage Vvfy2.With from
First verifying voltage Vvfy1 does not perform the mode of discharge operation and compares, in this case when generating the second verifying voltage Vvfy2
Negative voltage can be relatively quick to generate.The method that the negative voltage that generate varying level below be will be described more fully.
Figure 11 is the flow chart generating method for describing the negative voltage of the one exemplary embodiment according to present inventive concept.Figure
12 and Figure 13 is the diagram illustrating the waveform generating the negative voltage that method generates according to negative voltage.Figure 12 and Figure 13 exemplarily shows
Go out the first verifying voltage Vvfy1 and the waveform of the second verifying voltage Vvfy2 described in figure 9 and in figure 10.But, negative voltage
Type and level be not limited to this.
With reference to Figure 11, in step S1000, it can be determined that whether continuously generate negative voltage (such as, for the negative voltage of wordline
NWL).Can be determined whether even by the control logic 190 controlling the programming of flash memory 100, erasing and read operation
Continuous generation negative voltage (such as, for the negative voltage NWL of wordline).
If it is determined that discontinuously generate negative voltage, then method proceeds to step S1400, can carry out negative electricity in step S1400
Lotus pump operation.The discontinuous situation generating negative voltage may include that the situation, discontinuously of the negative voltage generating the first level
Generate situation of negative voltage of varying level etc..In step S1500, it can be determined that whether negative charge pumping result is equal to or low
In target negative voltage.Bear here it is possible to the value of the reference voltage Vref _ NEG by being provided as benchmark defines target
Voltage.
If negative charge pumping result is not equal to or less than target negative voltage, then can repeat negative charge pump operation until
Negative charge pumping result becomes equal to or less than till target negative voltage.If negative charge pumping result is born equal to or less than target
Voltage, the most described method proceeds to step S1600, stops negative charge pump operation in step S1600.
Returning to step S1000, if it is determined that continuously generate negative voltage, the most described method proceeds to step S1100.In step
Rapid S1100, it can be determined that whether the level of target negative voltage is higher than the previous mesh corresponding with the negative voltage previously just generated
Mark negative voltage.Continuously generate the situation of negative voltage can correspond to the most as shown in Figure 10 generating the first verifying voltage
The situation of the second verifying voltage Vvfy2 is generated without delay after Vvfy1.
If the level of target negative voltage is higher than previous target negative voltage, then in step S1200, can warp at short notice
Output by discharge component 743 and 763 electric discharge negative voltage generator 175.This can be applied to control in response to from control logic 190
The negative voltage of parts 744 and 765 processed enables signal NV_EN and performs.Such as, negative voltage detector 74 and negative voltage generator 76
Control parts 744 and 765 and can enable signal NV_EN in response to negative voltage and determine the activation of discharge component 743 and 763.
Can be the negative electricity that level is higher than the first verifying voltage Vvfy1 with reference to Figure 12 and Figure 13, the second verifying voltage Vvfy2
Pressure.In Figure 12 and Figure 13, previous target negative voltage TNV1 can correspond to the first verifying voltage Vvfy1, and new target
Negative voltage TNV2 can correspond to the second verifying voltage Vvfy2.Can be according to the reading of flash memory, programmed and erased behaviour
Target negative voltage TNV1 and TNV2 is supplied to bear by the order by the negative voltage being generated and their level needed for work
Voltage generator 175.Alternatively, it is possible to according to will be given birth to needed for the reading of flash memory, programming and erasing operation
The order of the negative voltage become and their level, arranged target negative voltage by controlling logic 190 to negative voltage generator 175
TNV1 and TNV2.
If being continuously generated the second verifying voltage Vvfy2 after generating the first verifying voltage Vvfy1, then control logic
The target negative voltage being set or providing negative voltage generator 175 can be switched to TNV2 from TNV1 by 190.When target is born
Voltage is when TNV1 is switched to TNV2, and the reference voltage Vref _ NEG arranging negative voltage generator 175 can become from TNV1
TNV2.In this case, during the period from t12 to t13, can be via negative voltage under the control controlling logic 190
The output of negative voltage generator 175 is discharged into a certain level by maker 175.
In fig. 12, schematically illustrate and the output of negative voltage generator 175 is discharged into less than ground voltage and is higher than
The situation of the level of target negative voltage TNV2.In fig. 13, schematically illustrate the output electric discharge of negative voltage generator 175
To equal to or less than ground voltage and the situation of the level higher than target negative voltage TNV2.As shown in Figure 12 and Figure 13, negative voltage is raw
Grow up to be a useful person 175 output can be discharged into the level between target negative voltage TNV2 and ground voltage or ground level.Can be by adjusting
Joint Δ t1 and Δ t2 discharge time, or by regulation electric discharge amplitude, ao V1 and Δ V2, control the defeated of negative voltage generator 175
The discharge level gone out.Can be at the voltage model from the level higher than target negative voltage TNV2 to the level equal to or less than ground voltage
Amplitude, ao V1 and Δ V2 is differently changed in enclosing.
Return to Figure 11, in step S1300, it can be determined that whether the output of the negative voltage generator 175 through discharging is higher than
Target negative voltage TNV2.If the output through the negative voltage generator 175 of electric discharge is less than target negative voltage TNV2, then can perform
Discharge operation is higher than target negative voltage TNV2 until the output of the negative voltage generator 175 through electric discharge.If through electric discharge
The output of negative voltage generator 175 is higher than target negative voltage TNV2, then can stop discharge operation, then can be in step
S1400 performs negative charge pump operation.
Can period during the period between t13 and t14 of Figure 12 or between the t13 ' and t14 ' of Figure 14
In, under the control controlling logic 190, perform the negative charge pump operation of step S1400.Such as, between t13 and t14 time
During period between section or t13 ' and t14 ', control parts 744 He of negative voltage detector 74 and negative voltage generator 76
765 can activate putting of discharge component 743 and 763 in response to from controlling the negative voltage enable signal NV_EN that logic 190 applies
Electrically operated.The output of negative voltage pump 75 and negative voltage generator 76 (specifically, can be the output electricity of negative voltage pump 75
Flat) discharge into the level less than reference voltage Vref _ NEG.Thus, from negative voltage detector 74 generate for negative voltage pump time
Clock CLK_NEGP, and negative voltage pump 75 can perform negative charge pump operation.
In step S1500, it can be determined that whether the negative charge pumping result of negative voltage pump 75 is equal to or less than target negative electricity
Pressure TNV2.If it is determined that the negative charge pumping result of negative voltage pump 75 is not equal to or less than target negative voltage TNV2, then can weigh
Multiple negative charge pump operation is until the negative charge pumping result of negative voltage pump 75 is equal to or less than target negative voltage TNV2.As
Really the negative charge pumping result of negative voltage pump 75 equals to or less than target negative voltage TNV2, then can stop negative electricity in step S1600
Lotus pump operation.
According to above-mentioned negative charge pump operation, the mesh of waveform represented by A and A ' having in Figure 12 and Figure 13 can be generated
Mark negative voltage TNV2.In such a case, it is possible to stably obtain the second verifying voltage as target negative voltage TNV2
Vvfy2。
But, present inventive concept is not limited to generate the target of waveform represented by A and A ' having in Figure 12 and Figure 13 and bears
Voltage TNV2.Such as, as the waveform B represented by dotted line in Figure 12 and Figure 13, can without negative charge pump operation reality
The now voltage conversion from TNV1 to TNV2.Negative charge pump operation can be performed to generate the negative voltage less than current voltage.Can
It is to test than the second of the first negative voltage high for verifying voltage Vvfy1 being previously generated do not carry out negative charge pumping to generate its level
Card voltage Vvfy2.Discharge path by multiple resistor R1_W to R5_W rather than the discharge component 763 by Fig. 5, can
To complete the discharge operation of relatively slow speed.
In this case, the second verifying voltage Vvfy2 rather than can have stable at t14 (or t14 ') at t15
Level.
Can optimize and generate operation for each period generating negative voltage to control negative voltage efficiently.
Hereinafter, under conditions of being sequentially generated negative verifying voltage, it is exemplarily illustrated with negative voltage generates method.But, negative electricity
Pressure generation method can apply to various negative voltage (such as, various negative wordline voltage) and various positive word line voltage, and without office
It is limited to certain negative voltage (such as, verifying voltage, read voltage etc.).Word line voltage according to present inventive concept generates method,
Level conversion can be carried out rapidly relative to negative wordline voltage and positive word line voltage.This can realize reducing programming time.This
Outward, reading and the verification operation of data mode about being distributed in negative voltage region and positive voltage region can be effectively carried out.
Figure 14 is to illustrate that the threshold voltage when the threshold voltage of some memory element is distributed in negative voltage region is distributed, tests
Card voltage and the diagram of read voltage.
In fig. 14, transverse axis can represent the threshold voltage of memory element, and the longitudinal axis can represent the quantity of memory element.?
In Figure 14, schematically illustrate memory element and there is erasing state ST0 and the first to the 7th programming state ST1 to ST7
Situation.But, present inventive concept is not limited to this.Can differently change logic state ST0 to the ST7 of memory element and patrol
The quantity of the state of collecting.
Owing to flash memory 100 is not written over, memory element therefore can be wiped before the programming operation.The most just
Being to say, memory element can be configured so that have erasing state ST0 before programming.Memory element can be assigned to have figure
Threshold voltage distribution in 14.This can be by erasing memory element to make it have level less than erasing verifying voltage Vvfye
Threshold voltage (or, distributed threshold voltage distribution ST0 in) realize.Be wiped free of to have erasing state ST0 it
After, memory element can be programmed to make it have one of first to the 7th programming state ST1 to ST7.
Flash memory 100 incrementally step-by-step impulse programming (ISPP) mode can perform programming operation, in order to essence
Really control threshold voltage distribution.Within the cycle formed by multiple program cycles, memory element can be programmed.Each
Program cycles can be divided into programming period P and programming checking period V.
During programming period P, under given bias condition, memory element can be programmed.According to ISPP mode,
The program voltage applied during programming period P can increase steppingly when program cycles repeats.Program voltage can be
Positive high voltage.In an exemplary embodiment, under the control controlling logic 190, programming can be generated from high voltage maker 171
Voltage.
During programming checking period V, can carry out verifying that read operation expires judging whether memory element is programmed
The threshold voltage (such as ST0 to ST7) hoped.Can overprogram circulate in determined number, until memory element is programmed into
Till desired threshold voltage.The first to the 7th corresponding with programming state ST0 to ST7 respectively verifying voltage can be used
Vvfy1 to Vvfy7 performs to verify read operation.In addition to data except reading do not export external equipment, behaviour is read in checking
Work can be essentially identical with normal read operation.
After completing the programming to memory element, normal read operation can be performed to read programming state ST0 to ST7
Data.When normal read operation, it is possible to use multiple read voltage Vrd1 to the Vrd7 in Figure 14 distinguish programming state
ST0 to ST7.
In an exemplary embodiment, the first read voltage Vrd1 and the second read voltage Vrd2 can be negative voltages.Second
Read voltage Vrd2 can be the negative voltage that level is higher than the first read voltage Vrd1.3rd to the 7th read voltage Vrd3 arrives
Vrd7 can be above the positive voltage of the second read voltage Vrd2.Can generate from low-voltage under the control controlling logic 190
Device 173 generates the 3rd to the 7th read voltage Vrd3 to Vrd7.Can be from negative voltage generator under the control controlling logic 190
175 generate the first read voltage Vrd1 and the second read voltage Vrd2.
In the case of the threshold voltage of Figure 14 is distributed, negative voltage generator 175 can be configured to controlling logic 190
Control under, generate the second read voltage Vrd2 without delay generating after the first read voltage Vrd1.Alternatively, negative electricity
Pressure maker 175 can be configured under the control controlling logic 190, generate the after the second read voltage Vrd2 generating
One read voltage Vrd1.Can differently determine that generation will apply in continuous read operation under the control controlling logic 190
The order of read voltage.
Such as, if generating the second read voltage Vrd2 without delay after generating the first read voltage Vrd1, then bear
The output of voltage generator 175, the i.e. first read voltage Vrd1 can be discharged into a certain level, then can pass through negative charge pump
Pu operation generates the second read voltage Vrd2.According to the one exemplary embodiment of present inventive concept, can realize rapidly from low
Negative voltage level switches to the negative voltage of high negative voltage level.
If generating the first read voltage Vrd1 without delay after generating the second read voltage Vrd2, then can pass through
Negative charge pump operation generate the first read voltage Vrd1 and without to the output of negative voltage generator 175, (namely second reads
Power taking pressure Vrd2) carry out discharge operation.As described above, can be according to the lever selection of the negative read voltage being sequentially generated
Ground performs discharge operation.It means that the negative voltage of varying level can be quickly generated.
Can control (such as to put for the period generating negative read voltage and positive read voltage according to the optimized time
Electricity period, pumping period etc.).Above-mentioned read voltage characteristic can apply to the normal read operation that will be described below and tests
Card read operation.Additionally, the method generating read voltage and checking read voltage can apply to various word line voltage.
Figure 15 be for describe generation test to the 7th with corresponding for programming state ST0 to ST7 first in Figure 14 respectively
The diagram of the method for card voltage Vvfy1 to Vvfy7.Figure 15 shows that the verifying voltage Vvfy1 according to 1 step proof scheme arrives
Vvfy7。
Utilize 1 step proof scheme, during programming checking period V, one can be performed relative to programming state ST0 to ST7
Secondary checking read operation.In an exemplary embodiment, for the first programming state ST1 and the second programming state ST2 is compiled
The first verifying voltage Vvfy1 and the second verifying voltage Vvfy2 of journey checking can be negative voltages.Second verifying voltage Vvfy2 can
To be the level negative voltage that is higher than the first verifying voltage Vvfy1.For the 3rd to the 7th programming state ST3 to ST7 is compiled
3rd to the 7th verifying voltage Vvfy3 to Vvfy7 of journey checking can have mutually different positive low-voltage.Can patrol in control
Collect and generate the 3rd to the 7th verifying voltage Vvfy3 to Vvfy7 from low-voltage maker 173 under the control of 190.Can patrol in control
Collect and generate the second verifying voltage Vvfy2 from negative voltage generator 175 under the control of 190.
In the case of 1 step proof scheme, negative voltage generator 175 can be configured to generating the first verifying voltage
The second verifying voltage Vvfy2 is generated without delay after Vvfy1.After generating the second verifying voltage Vvfy2, low-voltage generates
Device 173 can be sequentially generated the 3rd to the 7th verifying voltage without delay.
Generate, after generating the first verifying voltage Vvfy1, the time that the second verifying voltage Vvfy2 is spent to reduce,
Can be by the output of negative voltage generator 175 repid discharge during a certain preset time, and then can be via negative charge
Pump operation generates the second verifying voltage Vvfy2.Additionally, in order to reduce generation the after the second verifying voltage Vvfy2 generating
The time that three to the 7th verifying voltage Vvfy3 to Vvfy7 are spent, can generate by repid discharge negative voltage during preset time
The output of device 175, then can generate the 3rd verifying voltage Vvfy3 from low-voltage maker 173.Generating the 3rd verifying voltage
After Vvfy3, low-voltage maker 173 can be sequentially generated the 4th to the 7th verifying voltage Vvfy4 without discharge operation
To Vvfy7.
Specifically, in order to be sequentially generated negative voltage efficiently, when the period 1 and 2 can be set to optimized reference
Between Ref_DT (such as, t2_d and t3_d).Here, during the period 1, can hold after generating the first verifying voltage Vvfy1
Row discharge operation.During the period 2, discharge operation can be performed after generating the second verifying voltage Vvfy2.Can generate
Discharge before second verifying voltage Vvfy2 during reference time t2_d the first verifying voltage Vvfy1, and without verifying first
The output level of voltage Vvfy1 and the electric discharge result of the first verifying voltage Vvfy1 compare.
In an exemplary embodiment, can be based on defined in the electric discharge period 1 and 2 in the period between adjacent verifying voltage
Voltage difference, determine arrange to electric discharge the period 1 and 2 reference time t2_d and t3_d.Such as, if the first verifying voltage
Voltage difference between Vvfy1 and the second verifying voltage Vvfy2 is more than the second verifying voltage Vvfy2 and the 3rd verifying voltage Vvfy3
Between voltage difference, then the reference time t2_d of the period 1 that can would correspond to discharge was set greater than corresponding to electric discharge period 2
Reference time t3_d.
When determining for the reference time of electric discharge, can determine based on the level difference between negative voltage Vvfy2 and 0V
Discharge time t3_d.T3_d can correspond to voltage and was transformed into the time in positive voltage region from negative voltage region discharge time.This
Outward, the positive voltage pumping time can also be arranged based on target positive voltage Vvfy3 and 0V.
Phase period of the 3rd verifying voltage Vvfy3 as positive voltage is generated after the second verifying voltage Vvfy2 is provided
Between, first can then carry out positive charge pumping by negative voltage discharge to ground level.It is to say, can will be previously generated
Voltage, the i.e. second verifying voltage Vvfy2 discharges into ground level (or 0V), then performs for providing the 3rd verifying voltage Vvfy3
Positive charge pumping.
For the control mode that each electric discharge period arranges optimized reference time value can also be applied to negative electricity
The lotus pumping period.In an exemplary embodiment, the negative charge pumping period can be arranged identical reference time Ref PT or
Different values.The simulation result that can utilize maker determines and is set to negative charge pumping period and each electric discharge period
Reference time value Ref DT and Ref PT.Can program/erase cycle based on flash memory, temperature etc., predetermined
In the range of change reference time value RefDT and Ref PT.
Here it is possible to reference in test process obtain various factors determine reference time t2_d, t3_d, Ref DT and
Ref PT.Reference time t2_d, the t3_ considering various factors and determine can be set by fuse programming or primary data
D, Ref DT and Ref PT.As described above, negative verifying voltage and the period of positive verifying voltage can be sequentially generated by being used for
Control to the optimized time, thus improve programming verifying speed.
Figure 16 is the flow chart generating method for describing the negative voltage of the one exemplary embodiment according to present inventive concept.Figure
17 and Figure 18 is the diagram illustrating the waveform generating the negative voltage that method generates according to negative voltage.Figure 17 and Figure 18 exemplarily shows
Go out the first verifying voltage Vvfy1 and the waveform of the second verifying voltage Vvfy2 described in figures 14 and 15.But, negative electricity
Type and the level of pressure are not limited to this.
With reference to Figure 16, in step S2000, it can be determined that whether continuously generate negative voltage.Can be by controlling flash memory
The control logic 190 of the programming of part 100, erasing and read operation determines whether to continuously generate negative voltage.
If it is determined that be not to continuously generate negative voltage, then method proceeds to step S2400, can bear in step S2400
Charge pump operates.The discontinuous situation generating negative voltage may include that the situation of the negative voltage generating the first level, discontinuous
Ground generates situation of negative voltage of varying level etc..The negative voltage generated discontinuously can include the negative reading electricity in Figure 14
Pressure Vrd1 and Vrd2.
In step S2500, it can be determined that whether the negative charge pumping time is equal to or more than reference time RefPT.If it is negative
The charge pump time is less than reference time Ref PT, then can repeat negative charge pump operation until the negative charge pumping time reaches
Till reference time Ref PT.If the negative charge pumping time equals to or more than reference time Ref PT, then can in step S2600
To stop negative charge pump operation.
If it is determined that negative voltage will be continuously generated, then in step S2100, it can be determined that whether target negative voltage is higher than
The previous target negative voltage corresponding with the negative voltage previously just generated.The situation being continuously generated negative voltage can include example
Such as the situation generating the second verifying voltage Vvfy2 after generating the first verifying voltage Vvfy1 without delay as shown in figure 15.
If target negative voltage is higher than previous target negative voltage, then in step S2200, can be in DT phase reference time Ref
Between via discharge component 743 and 763 electric discharge negative voltage generator 175 output, the i.e. first verifying voltage Vvfy1.Can basis
Control the discharge operation of discharge component 743 and 763 from the discharge control signal DS controlling logic 190 generation, it is right thus to control
The electric discharge of the output of negative voltage generator 175.Discharge operation in step S2200 is described more fully below.
In Figure 17 and Figure 18, previous target negative voltage TNV1 can correspond to the first verifying voltage Vvfy1, and new
Target negative voltage TNV2 can correspond to the second verifying voltage Vvfy2.Here, the second verifying voltage Vvfy2 can be above
The negative voltage of one verifying voltage Vvfy1.Under the control controlling logic 190, can be according to the wiping performed at flash memory
Remove, program and the generation order of negative voltage needed for read operation and level, be negative with the form of reference voltage (Vref_NEG)
Voltage generator 175 is arranged or more fresh target negative voltage TNV1 and TNV2.
If generating the first verifying voltage Vvfy1 and being continuously generated the second verifying voltage Vvfy2, then control logic 190
The target negative voltage being set or providing negative voltage generator 175 can be changed to TNV2 from TNV1.In this case,
During reference time Ref DT, can be via discharge component 743 and 763 electric discharge negative voltage under the control controlling logic 190
The output of maker 175.
If the output of negative voltage generator 175 is not discharged during reference time Ref DT, then it is supplied first
The wordline of verifying voltage Vvfy1 can keep by the state of the first verifying voltage Vvfy1 charging as capacitor.In this feelings
Under condition, discharge operation can not be performed when from the negative voltage transition of the first verifying voltage Vvfy1 to second verifying voltage Vvfy2
With negative charge pump operation.Reason is, negative charge pump operation just performs when generation level is less than the negative voltage of current voltage.
When the second verifying voltage generating the negative voltage being higher than the voltage (the i.e. first verifying voltage Vvfy1) being previously generated as level
During Vvfy2, transfer characteristic slowly may be obtained as the curve B (shown in dotted line) in Figure 17 and Figure 18, and not
It it is negative charge pumping.In this case, during the first verifying voltage Vvfy1 is transformed into the second verifying voltage Vvfy2
May take a significant amount of time.
According to the one exemplary embodiment of present inventive concept, when carrying out from the first verifying voltage Vvfy1 to second verifying voltage
During the negative voltage transition of Vvfy2, can give birth at the negative voltage that discharge rapidly via discharge component 743 and 763 of period sometime
Grow up to be a useful person 175 output, and without carrying out waiting until that the voltage charged in wordline at the first verifying voltage Vvfy1 is put lentamente
Electricity is (with reference to solid line A, A ' and A ") in Figure 17 and Figure 18.Therefore, it can quickly realize negative voltage transition.
During discharge operation, the output of negative voltage generator 175 can be discharged into target negative voltage TNV2 and ground electricity
Level between pressure, or it is completely discharged to ground level.Can be by regulation discharge time t2_d, t2_d ' and t2_d " or
Person is by regulation electric discharge amplitude, ao V1, and Δ V2 and Δ V3 controls the discharge level of the output of negative voltage generator 175.Can be
Amplitude is differently changed in the level higher than target negative voltage TNV2 to the voltage range equal to or less than the level of ground voltage
Δ V1, Δ V2 and Δ V3.Such as, when the voltage difference between the adjacent negative voltage discharged between the period becomes bigger, can
To be arranged the longer time discharge time.Voltage difference between the adjacent negative voltage between the electric discharge period becomes relatively
Hour, discharge time can be arranged relatively short period of time.
Return to Figure 16, in step S2300, it can be determined that whether the time that execution discharge operation is spent is equal or longer than
Reference time Ref DT.If the time that execution discharge operation is spent is shorter than reference time Ref DT, then can be with reignition
The time that operation is spent until execution discharge operation is identical with reference time RefDT.If performing discharge operation to be spent
The time taken is equal or longer than reference time Ref DT, then can stop discharge operation.In step S2400, can patrol in control
Collect during reference time Ref PT, under the control of 190, perform negative charge pump operation.
In step S2500, it can be determined that whether the time that execution negative charge pump operation is spent is equal or longer than reference
Time Ref PT.If the time that execution negative charge pump operation is spent is shorter than reference time Ref PT, then can repeat to bear
Charge pump operates, until the time that execution negative charge pump operation is spent reaches reference time Ref PT.If held
The time that row negative charge pump operation is spent is equal or longer than reference time Ref PT, then can stop bearing in step S2600
Charge pump operates.
It is exemplarily illustrated with the method generating negative verifying voltage.But, present inventive concept is not limited to this.Such as, with
The optimized time controls the skill of each period (such as, electric discharge period, pumping period etc.) for generating negative verifying voltage
Art can also be applied to generate various negative wordline voltage and the operation of positive word line voltage.
Figure 19 is to illustrate that the threshold voltage when the threshold voltage of some memory element is distributed in negative voltage region is distributed, tests
Card voltage and the diagram of read voltage.Figure 20 is to illustrate the first to the 7th pre-authentication electricity being associated with programming state ST0 to ST7
The diagram of pressure main verifying voltage Vvfy1_F to the Vvfy7_F of Vvfy1_C to Vvfy7_C and first to the 7th.
In Figure 19 and Figure 20, schematically illustrate 2 step card read operations, wherein, during programming checking period V
Twice checking read operation is performed relative to each in programming state ST0 to ST7.But, it is applied to each programming state
Checking read operation quantity be not limited to this.
With reference to Figure 19 and Figure 20, according to 2 step card read operations, can be by using the pre-authentication electricity of each programming state
Pressure Vvfy_C performs the first checking read operation and uses the main verifying voltage Vvfy_F execution second of each programming state to test
Card read operation, judges whether to exist the threshold voltage of the memory element programmed in each programming state.
If producing program fail at the first checking read operation and/or the second checking read operation, then can be given
Overprogram circulation in quantity, until memory element is all by programming.In an exemplary embodiment, pre-authentication voltage
The level of Vvfy_C can be less than main verifying voltage Vvfy_F.The the first checking read operation using pre-authentication voltage Vvfy_C can
With the most rough verification operation, and the second checking read operation of main verifying voltage Vvfy_F is used to be properly termed as fine verification behaviour
Make.
When relatively big or threshold voltage the displacement of the displacement (shift) of threshold voltage is to be finely controlled threshold voltage
During distribution, 2 step verification modes can be applied to programming operation.1 step verification mode and Figure 19 in Figure 14 can be used in combination
With 2 step verification modes in 20.The verification mode that can be used for present inventive concept is not limited to particular situation.
In addition to having two verifying voltages to be associated with each in programming state ST1 to ST7, can scheme with generating
Mode identical for verifying voltage Vvfy1 to Vvfy7 in 15 generate verifying voltage Vvfy1_C to Vvfy7_C in Figure 20 with
And Vvfy1_F to Vvfy7_F.
Four electric discharge periods 11 to 14 can be at verifying voltage Vvfy1_C to Vvfy7_C and Vvfy1_F to Vvfy7_F
Terminate when being generated.
In an exemplary embodiment, can be based on the difference between the adjacent verifying voltage between the electric discharge period 11 to 14
Determine reference time t1_d, t2_d and t3_d that the electric discharge period 11 to 14 is set to.Such as, identical negative programming shape is being put on
The electric discharge period 11 and 13 between the verifying voltage of state can be configured so that have first discharge time t1_d.Putting on difference
The electric discharge period 12 between the verifying voltage of negative programming state can be configured so that have second discharge time t2_d.Putting on
The positive electric discharge period 14 between programming state and the verifying voltage of negative programming state can be configured so that had for the 3rd discharge time
t3_d。
In the present embodiment, first to the 3rd discharge time t1_d to t3_d can be different.Such as, during the first electric discharge
Between t1_d can be configured so that minima, the 3rd discharge time t3_d can be configured so that its value equal to or more than first electric discharge time
Between t1_d.Second discharge time t2_d can be configured so that its value equal to or more than the 3rd discharge time t3_d.However, it is possible to not
Determine together first to the 3rd discharge time t1_d to t3_d and be not limited to this disclosure.
Each electric discharge period is arranged the technology of optimized reference time and can also be applied to the negative charge pumping period
With the positive charge pumping period.
In an exemplary embodiment, the negative charge pumping period can be configured so that have identical reference time Ref PT,
Or can be configured so that the type according to negative verifying voltage and level have different values, as shown in Figure 20.Such as, with
The negative voltage pumping period that first negative verifying voltage Vvfy1_C is associated can be configured so that have the first pumping time t1_p.
The negative voltage pumping period being associated with fine negative verifying voltage Vvfy1_F and Vvfy2_F can be configured so that have second
Pumping time t2_p.It is associated with rough negative checking read voltage Vvfy2_C in addition to the first negative verifying voltage Vvfy1_C
The negative voltage pumping period can be configured so that there is the 3rd pumping time t3_p.With rough just checking read voltage Vvfy3_
The positive voltage pumping period that C to Vvfy7_C is associated can be configured so that have the 4th pumping time t4p.Just test with fine
The positive voltage pumping period that card read voltage Vvfy3_F to Vvfy7_F is associated can be configured so that had for the 5th pumping time
t5_p。
Positive charge pumping can be determined based on the voltage difference that the pumping period is present between adjacent verifying voltage therebetween
Period and negative charge pumping period.Therefore, the first pumping time t1_p can be maximum.In the first pumping time t1_p, phase
Voltage difference between adjacent verifying voltage can be maximum.Second pumping time t2_p or the 5th pumping time t5_p can be
Little.At the second pumping time t2_p or the 5th pumping time t5_p, the voltage difference between adjacent verifying voltage can be minimum
's.
The simulation result that can utilize maker determines and is set to each negative charge pumping period, each electric discharge period
Reference time value RefDT and RefPT with each positive charge pumping period.Can program/erase based on flash memory
Cycle, temperature etc., in preset range, change reference time value Ref DT and Ref PT.
As described above, can control with the optimized time and continuously generate negative verifying voltage and positive verifying voltage
The each period being associated, thus improve programming verifying speed.Iff according to the reference arranging the negative voltage pumping period
Time Ref PT controls the negative voltage of negative voltage generator 175 and generates the period, then can remove from negative voltage generator 175
Voltage detector 74.Therefore, it can simplify negative charge pump pump circuit and control method thereof.It means that in the optimized time
Inside it is effectively carried out negative charge pump operation.
Generate method according to above-mentioned negative voltage, optionally can be attended by according to the negative voltage level continuously generated
The negative charge pump operation of discharge operation and the negative charge pump operation being not accompanied by discharge operation.It is exemplarily illustrated with and has performed companion
Situation with the negative charge pump operation having discharge operation.Execution will be described more fully with reference to Figure 21 to Figure 23 and be not accompanied by electric discharge
The situation of the negative charge pump operation of operation.
Figure 21 is the diagram generating method for describing the word line voltage of the one exemplary embodiment according to present inventive concept.
Compared with the verifying voltage in Figure 10, except the second verifying voltage Vvfy2 and the 3rd verifying voltage Vvfy3 exchange with
Outward, the diagram of Figure 21 can be identical with Figure 10.Therefore, descriptions thereof will be omitted.
With reference to Figure 21, (generating from negative voltage generator 175) at least two or more can be applied to selected word line successively
There is negative voltage (such as, Vvfy1 and Vvfy2) and (generating from low-voltage maker 173) the lowest electricity of varying level more
Pressure (such as, Vvfy3).Such as, when programming, the first of the negative level that has generated from negative voltage generator 175 can be tested
Card voltage Vvfy1 is applied to selected word line and is programmed that memory element with checking.At this point it is possible to according to first as capacitor
Wordline is charged by verifying voltage Vvfy1.In the case of present inventive concept, can test the 3rd with positive voltage level immediately
Card voltage Vvfy3 is applied to selected word line, and without by the time charging in selected word line after applying the first verifying voltage Vvfy1
Negative voltage discharged lentamente.The 3rd verifying voltage Vvfy3 can be applied to selected word line and be programmed with the with checking
The memory element of three programming state ST3.
In such a case, it is possible to by the 3rd verifying voltage Vvfy3 with positive voltage level, will be due to the first checking
Voltage Vvfy1 and selected word line charging negative voltage discharge to ground level or be higher than the first verifying voltage Vvfy1 level.By
It is discharged into ground level or the level higher than the first verifying voltage Vvfy1 in the negative voltage charged in selected word line, is therefore giving birth to
The negative voltage pump of negative voltage generator 175 can be activated immediately when becoming the second verifying voltage Vvfy2.Therefore, it can pass through negative electricity
The negative voltage pump operation of pressure maker 175 is quickly generated the second verifying voltage Vvfy2.Second can be applied to selected word line
Verifying voltage is programmed with the memory element of the second programming state ST2 with checking.
Generate method according to above-mentioned word line voltage, (or generate word by regulation by sequentially generating negative voltage and positive voltage
The order of line voltage), without the wordline recovery operation that the electric charge charged in wordline is discharged, i.e. can obtain extensive with wordline
Operate identical effect again.Therefore, it can be continuously generated negative wordline voltage and without wordline recovery operation.It means that can
To be quickly carried out the level conversion of negative wordline voltage.
Figure 22 is for describing showing of the word line voltage of another one exemplary embodiment according to present inventive concept generation method
Figure.
Compared with the verifying voltage in Figure 10, except the first verifying voltage Vvfy1 and the second verifying voltage Vvfy2 exchange with
Outward, the diagram of Figure 22 can be identical with Figure 10.Therefore, descriptions thereof will be omitted.
With reference to Figure 22, if being continuously generated at least two or more negative voltage with varying level, then negative voltage is raw
Grow up to be a useful person 175 may determine that negative voltage generate order so that having negative voltage (such as, second verifying voltage of higher level
Vvfy2) generated before there is more low level negative voltage (such as, the first verifying voltage Vvfy1).In this case, when
Carry out, when the negative voltage transition of the second verifying voltage Vvfy2 to first verifying voltage Vvfy1, negative charge pump to be immediately performed
Pu operates without discharge operation.Therefore, it can quickly realize negative voltage transition.
Figure 23 is for describing the first verifying voltage Vvfy1 shown in Figure 22 and the diagram of the second verifying voltage Vvfy2.
Can differently determine the level of the first verifying voltage Vvfy1 and the second verifying voltage Vvfy2 and generate order.
The first verifying voltage Vvfy1 in Figure 22 and Figure 23 and the level of the second verifying voltage Vvfy2 can with Figure 10 and
Identical in Figure 21.But, generate the first verifying voltage Vvfy1 and the second verifying voltage Vvfy2 order can with Figure 10 and
Difference in Figure 21.
For example, it is possible to firstly generate the second verifying voltage Vvfy2, level then can be generated less than the second verifying voltage
The first verifying voltage Vvfy1 of Vvfy2.In this case, owing to being bearing from high negative voltage level to low negative voltage level
Voltage is changed, and therefore can activate negative charge pump operation when generation has low level negative voltage, and without discharge operation
Or wordline recovery operation.Therefore, it can be continuously generated negative wordline voltage and without discharge operation or wordline recovery operation.This meaning
Taste, and can be quickly carried out the level conversion of negative wordline voltage.
Use the first verifying voltage Vvfy1 in the middle of the negative voltage that negative voltage generator 175 generates and second checking electricity
Pressure Vvfy2 has been exemplarily illustrated with present inventive concept.But, generate according to the negative voltage of the one exemplary embodiment of present inventive concept
Method can apply to generate all operations of the negative wordline voltage with varying level, is not limited to particular case or certain negative
Voltage amount.Additionally, the situation using negative voltage to be used as word line voltage has been exemplarily illustrated with present inventive concept.But, root
The negative voltage generated according to present inventive concept can serve as various voltage, such as trap voltage, bit-line voltage etc..
As it has been described above, in order to be quickly generated negative voltage, can determine negative according to the level of the negative voltage that will generate
The negative voltage of voltage generator 175 generates order, and without discharge operation or wordline recovery operation.Raw according to described word line voltage
One-tenth method, it is not necessary to discharge operation or wordline recovery operation, can be obtained and wordline by the order of regulation generation word line voltage
The effect that recovery operation is identical.Therefore, it can be continuously generated negative wordline voltage and without discharge operation or wordline recovery operation.
It means that the level conversion of negative wordline voltage can be quickly carried out.In this case, negative voltage generator 175 is permissible
Do not include the component being associated with discharge operation or wordline recovery operation.Therefore, it can simplify negative voltage generator and bag
Include the voltage generating unit 170 of negative voltage generator.
Figure 24 is the perspective view of the memory cell array of the one exemplary embodiment according to present inventive concept.Demonstrate in fig. 24
Property show have stacking flash memory structure cell array 1101.
With reference to Figure 24, three-dimensional arrangement can be included according to the flash memory of the one exemplary embodiment of present inventive concept
Memory element.Can form memory element at multiple semiconductor layers, the plurality of semiconductor layer is used separately as forming MOS brilliant
The semiconductor base of body pipe.For the ease of describing, schematically illustrate two semiconductor layers, the i.e. first quasiconductor in fig. 24
Layer 10 ' and the second semiconductor layer 20 '.But, the quantity of semiconductor layer is not limited to this.For example, it is possible to stack three or more
Semiconductor layer.
In the present embodiment, the first semiconductor layer 10 ' can be silicon single crystal wafer, and the second semiconductor layer 20 ' can be logical
Cross the single-crystal Si epitaxial layers that epitaxy technique is formed, in described epitaxy technique, the first semiconductor layer 10 ', i.e. wafer are used as seed crystal
Layer.In the present embodiment, semiconductor layer 10 ' can have mutually isostructural cell array with each in 20 '.Memory element
May be constructed multi-level-cell array 1101.
Each in semiconductor layer 10 ' and 20 ' can include by device isolation pattern (device isolation
Pattern) 15 active area limited.Source region can be formed concurrently along a direction.Device isolation pattern 15 can be by
Insulant including silicon oxide layer is formed, to electrically insulate active area.
Can arrange, in each in semiconductor layer 10 ' and 20 ', the grid structure crossing over active area.Grid structure can
To be selected line GSL and SSL and M wordline WL to be formed by a pair.Source electrode connector 50 ' can be arranged in the side of grid structure,
And bit line plugs 40 ' can be arranged at its opposite side.Bit line plugs 40 ' can be connected with N number of bit line BL respectively, described N number of
Bit line BL crosses over wordline WL.Can be formed in uppermost semiconductor layer (such as, the second semiconductor layer 20 ' in Figure 24) top
Bit line BL, in order to cross over wordline WL.The N of the quantity of expression bit line BL can be the integer of 1 or bigger.Such as, N can be 8
One of multiple.
Wordline WL can be arranged in selection line GSL and SSL between, and one grid structure can (M be 1 by M wordline
Or bigger integer) formed.Such as, M can be one of the multiple of 8.One of line GSL and SSL is selected to can serve as controlling public
The ground of the electrical connection between source electrode line CSL and memory element selects line GSL.Another in selection line GSL and SSL can serve as
The string controlling the electrical connection between bit line and memory element selects line SSL.
Impurity range can be formed in the active area selecting line and wordline to be limited.Select line GSL side to be formed on ground
Impurity range 11S and 21S can serve as the source electrode connected by common source polar curve CSL, and selects line SSL side to be formed at string
Impurity range 11D and 21D can serve as the drain electrode that is connected via bit line plugs 40 ' with bit line BL.Both sides shape in wordline WL
Impurity range 11I and 21I become may serve as being connected in series the inside impurity range of memory element.
Source electrode connector 50 ' can be by impurity range 11S and 21S (hereinafter referred to as the first source area and the second source area)
It is connected with semiconductor layer 10 ' and 20 '.It means that the first source area 11S and the second source area 21S has and semiconductor layer 10 '
The electromotive force identical with 20 '.This electrical connection can by via the second semiconductor layer 20 ' and the second source area 21S by source electrode connector
50 ' are connected with the first source area 11S and to realize.Source electrode connector 50 ' can be with the second source area 21S and the second semiconductor layer 20 '
Contact internal walls.
The voltage generation method of the one exemplary embodiment according to present inventive concept can apply to have and figure 24 illustrates
Stacking flash memory structure flash memory.In the case of present inventive concept, negative voltage and positive voltage can be applied to
The flash memory of Figure 24 is using as word line voltage.Additionally, the negative voltage according to the one exemplary embodiment of present inventive concept is raw
One-tenth method can apply to memory element by the three-dimensional flash memory memory cell structure of three-dimensional arrangement.Three-dimensional flash memory is permissible
The method by repeating to be formed memory element in two dimension does not realizes, but by using the pattern of the active area for definition
Metallization processes forms wordline or wordline plate (word line plate) realizes.Therefore, it can reduce every bit manufacturing cost.
Figure 25 is the perspective view of the memory cell array of another one exemplary embodiment according to present inventive concept.In fig. 25
Schematically illustrate cell array 110_2 with three-dimensional flash memory structure.
With reference to Figure 25, cell array 110_2 of flash memory can include multiple wordline plate WL_PT and be arranged as
Cross over multiple active pillar (or active area) PL of multiple wordline plate WL_PT.Multiple wordline plate WL_PT can be electrically isolated from each other.Half
Conductor substrate can include well area and source area S.Source area S can have the conduction type being different from well area.Such as, trap
Region can be p-type, and source area S can be N-type.In the present embodiment, well area can have pouch-type well structure (or be referred to as
Triple well structure).For pouch-type well structure, well area can be had conduction type and be different from least another trap of this well area
Region (not shown) surrounds.
Each wordline plate WL_PT can be formed by multiple local word lines, and the plurality of local word line is coplanarly public to be electrically connected
Connect that there is identical electromotive force.Wordline plate WL_PT can be separated by interlayer dielectric (not shown) electricity respectively.Wordline plate WL_
PT can electrically connect with the Overall word line GWL of electric isolution via word line contact part WL_CT respectively.Part WL_CT is permissible for word line contact
Formed at the edge of memory cell array or array block.In the present embodiment, the width of wordline plate WL_PT can differently be changed
Position with word line contact part WL_CT.
Each active pillar PL can include main part B of neighbouring well area and neighbouring upper selection line (upper
Selection word line) the drain region D of the USLi integer of N or less (i be).Main part B can have identical with trap
Conduction type, and drain region D can have the conduction type being different from well area.Multiple active pillar PL can have and are formed
For running through the major axis of multiple wordline plate WL_PT.The cross point of wordline plate WL_PT and active pillar PL can be in distributed in three dimensions.The most just
Being to say, the memory element in three-dimensional storage can be formed by the cross point of distributed in three dimensions.Can wordline plate WL_PT with have
Gate insulating film GI is arranged between the post PL of source.In the present embodiment, gate insulating film GI can be formed by multilamellar.Such as, grid
Dielectric film GI can be formed by oxidenitride oxide (Oxide-Nitride-Oxide, ONO).Gate insulating film GI
A part may serve as the thin film (that is, charge storage film or charge storage layer) of storage information.
One end of active pillar PL can be commonly connected with well area, and the other end can be connected with bit line BL.One bit line BL
Can be with multiple, the most N number of active pillar PL connects.This means a bit line BL with multiple, the most N number of unit string CSTR is even
Connect.One active pillar PL can form a unit string CSTR.One unit string CSTR can be included in multiple wordline plate WL_PT
The multiple memory element formed.One memory element can be by active pillar PL and a local word line or a wordline plate
WL_PT limits.
One unit string CSTR (that is, one active pillar PL) can be independently selected with to the programming of each memory element or
It is read from data.Selection line USLi on multiple can be arranged between bit line BL and uppermost wordline plate WL_PT.Upper selection
Line USLi can be arranged to cross over bit line BL.Bit line BL can electrically connect with drain region D via connector.Alternatively, bit line
BL can directly electrically connect with drain region D.
Can respectively bit line BL with on select the infall of line USLi formed be used for controlling active pillar PL and bit line BL it
Between the multiple upper selection transistor of electrical connection.The gate electrode of upper selection transistor can connect with the corresponding upper line USLi of selection
Connect.Select line USLi that active pillar PL (that is, one unit string can be selected independently by a bit line BL and one are upper
CSTR)。
As shown in figure 25, source area S can be formed in well area.Source area S can form the charge path to bit line
Or from the charge path of bit line.Source area S can electrically connect with common source polar curve CSL.Can be at common source polar curve CSL and source electrode
The source contact connector S_CT of wordline plate WL_PT it is inserted through between district S.Common source polar curve CSL can pass through source line contact
Connector S_CT and be arranged in above bit line BL, and can be formed by metal material.However, it is also possible to form common source polar curve
CSL makes it have variously-shaped.
In order to control to the charge path of bit line/from the charge path of bit line, can be in well area and nethermost wordline
The multiple lower selection line for controlling the electrical connection between active pillar PL and well area is arranged between plate WL_PT.At the present embodiment
In, multiple lower selection line LSL can be formed has mutually iso-electric lower option board LS_PT.Under lower selection line can be applied to
Select the gate electrode of transistor to control the electrical connection between active pillar PL and well area.Exemplary reality according to present inventive concept
The voltage generation method executing example can apply to above-mentioned three-dimensional flash memory.One exemplary embodiment according to present inventive concept
The wordline plate of the flash memory that the negative wordline voltage generated and positive word line voltage can be applied in Figure 25.
Figure 26 is that the data storage including flash memory illustrating the one exemplary embodiment according to present inventive concept sets
Standby block diagram.
With reference to Figure 26, data storage device 1500 can be by host computer control.Such as, main frame can include that handheld electronic sets
Standby, such as individual/handheld computer, personal digital assistant (PDA), portable electronic device (PMP), MP3 player etc..Main
Machine and data storage device 1500 can pass through such as USB, SCSI, ESDI, SATA, SAS, quick PCI or the standard of ide interface
Change interface to connect.Can differently realize connecting main frame and the interface mode of data storage device 1500 and being not necessarily limited to spy
Determine mode.
Data storage device 1500 can be formed by solid-state disk or driver (SSD).But, present inventive concept is not limited to
This.Such as, data storage device 1500 can be integrated in single semiconductor device, with formed PC (PCMCIA) card, CF card,
SM (or SMC) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), safety card (SD, miniSD, microSD,
SDHC), general flash memory (UFS) equipment, etc..
Data storage device 1500 can include storage control 1200 and the flash memory as main memory section
1100.Storage control 1200 can be configured to respond to control the reading behaviour of flash memory 1100 from the request of main frame
Work, write operation and erasing operation.
Flash memory 1100 can be by multiple nonvolatile memory chips (such as, flash memory chip) 100_1
Formed to 100_4.Flash memory chip 100_1 to 100_4 can respectively according to via respective channel provide from main frame
Request and perform the operation of read/write/erasing.
Each in flash memory chip 100_1 to 100_4 can have the structure identical with Fig. 1 and behaviour
Make.Such as, each in flash memory chip 100_1 to 100_4 can use the membrane-enclosed conductive floating gates that insulated to make
For charge storage layer.Additionally, each in flash memory chip 100_1 to 100_4 can use such as Si3N4、Al2O3、
The dielectric film of HfAlO, HfSiO etc. and atypical conductive floating gates, as charge storage layer.Showing according to present inventive concept
The flash memory of exemplary embodiment can be implemented with one of the following: have multiple tier array stacking flash memory structure,
Without source-drain flash memory structure, needle-like flash memory structure and three-dimensional (or vertical-type) flash memory structure.
Each in flash memory chip 100_1 to 100_4 may be implemented as including and in Figure 10 to Figure 23
The negative voltage of the present inventive concept described generates all characteristics being associated.Such as, flash memory chip 100_1 to 100_4
In each can be configured to be continuously generated multiple negative voltage using as the voltage that will be applied to that wordline.Concrete next
Saying, each in flash memory chip 100_1 to 100_4 can be configured to change rapidly the level of negative voltage.More
In detail, when generating the first negative voltage, then generating level higher than the second negative voltage of the first negative voltage, can rapidly by
The voltage (the i.e. first negative voltage) being previously generated discharges into the most a certain level.It is then possible to perform during time Ref PT
Negative charge pump operation is to generate the second negative voltage.In such a case, it is possible to be optimized for generating in time negative voltage time
Section.It means that required negative voltage level can be generated within the quick time.
In another embodiment, each in flash memory chip 100_1 to 100_4 can be configured to according to inciting somebody to action
The generation order of the negative voltage level regulation negative voltage being generated, or regulation voltage generates order so that negative voltage and positive voltage
Sequentially generate.In such a case, it is possible to without discharge operation or wordline recovery operation, thus minimize and be pressed onto from the first negative electricity
The time delay that the conversion of the second negative voltage is caused.It means that required negative electricity can be generated within the quick time
Voltage level.
Under conditions of being sequentially generated negative verifying voltage, it is exemplarily illustrated with negative voltage generates method.But, negative voltage
Generation method can apply to various negative voltage (such as, various negative wordline voltage) and various positive word line voltage, and without limitation
In certain negative voltage (such as, verifying voltage, read voltage etc.).Word line voltage according to present inventive concept generates method, can
To be quickly carried out relative to negative wordline voltage and the level conversion of positive word line voltage.This can realize reducing programming time.This
Outward, the read operation about the data mode being distributed in negative voltage region and positive voltage region and checking behaviour can be effectively carried out
Make.
Figure 27 is the block diagram of the data storage device illustrating another one exemplary embodiment according to present inventive concept.
With reference to Figure 27, data storage device 2000 can include storage control 2200 and flash memory 2100.
Flash memory 2100 can be substantially identical with Fig. 1.Flash memory 2100 may be implemented as having with
Under one of every: have the stacking flash memory structure of multiple tier array, without source-drain flash memory structure, needle-like flash memory structure and three-dimensional (or are hung down
Straight type) flash memory structure.Flash memory 2100 may be implemented as including and the present inventive concept described in Figure 10 to Figure 23
Negative voltage generate all characteristics of being associated, therefore omit descriptions thereof.
Storage control 2200 can be configured to control flash memory 2100.Storage control 2200 can be with Fig. 1
Identical to shown in Figure 26.
SRAM 2230 can serve as working storage.HPI 2220 can include with data storage device 2000 even
The data exchange agreement of the main frame connect.ECC circuit 2240 can be configured to detection and correction reads from flash memory 2100
The mistake of data.Memory interface 2260 can be configured to and the flash memory of the one exemplary embodiment according to present inventive concept
Reservoir 2100 interface.CPU 2210 can be configured to whole control theed perform for exchanging data and operate.Although not shown, but
Being that data storage device 2000 can also include ROM, its storage is for the code data with HPI.
In the present embodiment, data storage device 2000 can apply to one of various subscriber equipment, such as computer, portable
Formula computer, super mobile PC (UMPC), work station, net book, PDA, upper web plate, radio telephone, mobile phone, smart phone,
E-book, PMP (portable media player), digital camera, digital audio recorder/player, digital picture/video note
Record device/player, portable game machine, navigation system, black box, three-dimensional television, can send in the wireless context and connect
One of one of the equipment of collection of letters breath, the various electronic equipments constituting home network, the various electronic equipments constituting computer network,
Constitute one of one of various electronic equipments of car networking, RFID or the various electronic equipments constituting calculating system (such as SSD, to deposit
Card storage etc.).
Figure 28 is the block diagram of the data storage device illustrating another one exemplary embodiment according to present inventive concept.
With reference to Figure 28, data storage device 3000 can include flash memory 3100 and flash controller 3200.Flash memory
Controller 3200 can control flash memory 3100 in response to from the control signal of data storage device 3000 external reception.Dodge
Memory controller 3200 can be substantially identical with Figure 26 and Figure 27, therefore omits descriptions thereof.
Additionally, flash memory 3100 can be identical with Fig. 1, and may be implemented as having the following it
One: there is the stacking flash memory structure of multiple tier array, without source-drain flash memory structure, needle-like flash memory structure and three-dimensional (or vertical-type) flash memory
Structure.Flash memory 3100 in Figure 28 may be implemented as including and the present inventive concept described in Figure 10 to Figure 23
Negative voltage generates all characteristics being associated, and therefore omits descriptions thereof.
Data storage device 3000 can be that memory card device, SSD equipment, multimedia card equipment, SD equipment, memory stick set
Standby, HDD equipment, hybrid drive equipment or USB flash device.Such as, data storage device 3000 can be for such as digital
The card meeting industrial standard that the subscriber equipment such as camera, personal computer uses.
Figure 29 is the calculating system including flash memory illustrating the one exemplary embodiment according to present inventive concept
Block diagram.
With reference to Figure 29, calculating system 4000 can include flash memory 4100, storage control 4200, such as base band
The modem 4300 of chipset, microprocessor 4500 and user interface 4600.Element 4200,4300,4500 and 4600 can
To electrically connect with bus 4400.Flash memory 4100 can essentially identical with Fig. 1, and may be implemented as having
One of the following: have the stacking flash memory structure of multiple tier array, without source-drain flash memory structure, needle-like flash memory structure and three-dimensional (or
Vertical-type) flash memory structure.Flash memory 4100 in Figure 29 may be implemented as including with described in Figure 10 to Figure 23
The negative voltage of present inventive concept generate all characteristics of being associated, therefore omit descriptions thereof.
If calculating system 4000 is mobile device, it could be included for the battery into calculating system 4000 power supply
4700.Although not shown, but calculating system 4000 can also include application chip group, camera images processor (camera
Image processor, CIS), removable DRAM etc..Storage control 4200 and flash memory 4100 may be constructed
Such as use the solid-state drive (SSD) of nonvolatile semiconductor memory member storage data.
In certain embodiments, nonvolatile semiconductor memory member and/or storage control can be come by various encapsulated types
Encapsulation, such as PoP (Package on Package, laminate packaging), BGA (Ball grid array, BGA), chip chi
Very little encapsulation (Chip scale package, CSP), plastic tape leaded chip carrier (Plastic Leaded Chip
Carrier, PLCC), plastics dual-in-line package (Plastic Dual In Line Package, PDIP), waffle in wafer
Die form (Die in Wafer Form), chip on board (Chip On in encapsulation (Die in Waffle Pack), wafer
Board, COB), ceramic double-row straight cutting encapsulation (Ceramic Dual In-Line Package, CERDIP), plastic quad flat
Encapsulation (Metric Quad Flat Pack, MQFP), slim quad flat package (Thin Quad Flatpack, TQFP), little
Outline integrated circuit (Small Outline IC, SOIC), the little outline packages of shrinkage type (Shrink Small Outline
Package, SSOP), slim little outline packages (Thin Small Outline, TSOP), system in package (System In
Package, SIP), multi-chip package (Multi Chip Package, MCP), wafer scale make encapsulation (Wafer-level
Fabricated Package, WFP), crystal circular piled encapsulation (Wafer-Level Processed Stack Package,
WSP), etc..
Theme disclosed above should be considered as illustrative and not restrictive, and claim is intended to cover
Fall into all that amendment in true spirit and scope, improve and other embodiments.Thus, in allowed by law maximum limit
Degree in, the scope of the present invention is allowed explanation to determine by claim and the broadest of equivalent thereof, and should not be so limited to or
It is confined to aforementioned specific descriptions.
Claims (47)
1. the word line voltage of flash memory generates a method, including:
Positive voltage maker is used to generate program voltage；
Negative voltage generator is used to generate the multiple negative programming verifying voltage corresponding with multiple negative data states；And
Positive voltage maker is used to generate at least one or more programming checking electricity corresponding with at least one or more state
Pressure,
Wherein, the step of the multiple negative programming verifying voltage of described generation includes:
Generate the first negative verifying voltage,
The output of electric discharge negative voltage generator so that it is become to be above the first negative verifying voltage, and
Perform negative charge pump operation, until the output of negative voltage generator reaches the second negative verifying voltage level.
2. word line voltage as claimed in claim 1 generates method, wherein, the level of the output of the negative voltage generator through discharging
Level higher than described first negative verifying voltage and the level equal to or less than ground voltage.
3. word line voltage as claimed in claim 1 generates method, wherein, the first negative verifying voltage checking negative less than second electricity
Pressure.
4. the word line voltage of flash memory generates a method, including:
Negative voltage generator is used to generate the multiple negative read voltage corresponding with multiple negative data states；And
Use low-voltage maker to generate at least one or more corresponding with at least one or more correction data state just to read
Power taking pressure,
Wherein, the step of the multiple negative read voltage of described generation includes:
Generate the first negative read voltage,
The output of electric discharge negative voltage generator so that it is become to be above the first negative read voltage, and
Perform negative charge pump operation, until the output of negative voltage generator reaches the second negative read voltage level.
5. word line voltage as claimed in claim 4 generates method, wherein, the level of the output of the negative voltage generator through discharging
Level higher than the first negative read voltage and the level equal to or less than ground voltage.
6. word line voltage as claimed in claim 4 generates method, and wherein, the first negative read voltage is negative less than second reads electricity
Pressure.
7. the word line voltage of flash memory generates a method, including:
The first negative voltage is generated via the negative charge pumping of negative voltage pump；
The output of electric discharge negative voltage pump；
The electric discharge output of negative voltage pump is compared with the second negative voltage as target negative voltage；And
If the electric discharge output of negative voltage pump is higher than the second negative voltage, then activation negative charge pumping is to generate the second negative voltage,
Wherein, the negative charge pumping of described negative voltage pump is activated, until the electric discharge output of negative voltage pump is equal to or less than second
Negative voltage.
8. word line voltage as claimed in claim 7 generates method, wherein, when electric discharge result or the instruction of negative charge pumping result are negative
When the output of electric charge pump is higher than target negative voltage, perform negative charge pumping.
9. word line voltage as claimed in claim 7 generates method, wherein, when electric discharge result or the instruction of negative charge pumping result are negative
When the output of electric charge pump is higher than target negative voltage and equal to or less than ground voltage, perform negative charge pumping.
10. word line voltage as claimed in claim 7 generates method, wherein, performs the electric discharge of described negative charge pump, until negative electricity
The output of lotus pump reaches predetermined negative voltage level.
11. word line voltages as claimed in claim 7 generate method, wherein, in response to controlling the control of logic, in the scheduled time
Period performs the electric discharge of described negative charge pump.
12. 1 kinds of flash memories, including:
Memory cell array, they multiple flash memory cells including being arranged in the infall of multiple wordline and multiple bit line；
Voltage generating unit, it is configurable to generate the multiple word line voltages that will be applied to that wordline；And
Controlling logic, its voltage being configured to control voltage generating unit generates operation,
Wherein, described voltage generating unit includes negative voltage generator, and it is configurable to generate the first negative voltage, discharge this first
Negative voltage, and perform negative charge pumping until generating the second negative voltage higher than the first negative voltage.
13. flash memories as claimed in claim 12, wherein, after to the first negative voltage discharge, negative voltage generates
The output of device is higher than the second negative voltage and equal to or less than ground voltage.
14. flash memories as claimed in claim 12, wherein, when generating less than first after generating the first negative voltage
During three negative voltage of negative voltage, described negative voltage generator performs negative charge pumping, until the output of this negative voltage generator
Reach the 3rd negative voltage.
15. flash memories as claimed in claim 12, wherein, described negative voltage generator includes:
DC voltage maker, it is configurable to generate DC voltage；
Reference voltage maker, it is configurable to generate the reference voltage corresponding with target negative voltage；
Agitator, it is configurable to generate the first clock；
Negative charge pump, it is configured to respond to second clock and performs negative charge pumping, and as the result of negative charge pumping
Generate target negative voltage；And
Voltage detector, it is configured to respond to described DC voltage, reference voltage and the first clock comparison object negative voltage
And reference voltage, and generate second clock according to comparative result.
16. flash memories as claimed in claim 15, wherein, described voltage detector includes:
Power supply unit, it is configured to respond to negative voltage and enables the signal power supply to comparison node offer DC voltage；
Dividing potential drop parts, it is connected between comparison node and detection node, and is configured to described DC voltage dividing potential drop, its
In, supply target negative voltage to described detection node；
Discharge component, it is connected to detect between node and earth terminal, and is configured to respond to described negative voltage enable signal
The voltage of inversion signal discharge examination node；
Comparing unit, it is configured to the voltage comparing comparison node and described reference voltage, and generates as comparative result
Second clock；And
Controlling parts, it is configured to respond to negative voltage enable signal and determines the activation to power supply unit and discharge component.
17. flash memories as claimed in claim 16, wherein, when the electric discharge according to discharge component, the electricity of detection node
When pressure is higher than reference voltage and equal to or less than ground voltage, discharge component described in described control parts deexcitation.
18. flash memories as claimed in claim 16, wherein, when performing discharge component during the scheduled time
After discharge operation, described control this discharge component of parts deexcitation.
19. flash memories as claimed in claim 15, wherein, described negative voltage generator be configured to based on described directly
Stream voltage, reference voltage and the target negative voltage generated from negative charge pump, generate corresponding with target negative voltage, for word
The negative voltage of line, and
Wherein, described negative voltage generator includes discharge component, and it is configured to respond to anti-phase negative voltage enable signal and puts
The described negative voltage of electricity.
20. flash memories as claimed in claim 12, wherein, described memory cell array includes 3-dimensional memory cell battle array
Row, it has the multiple wordline plates being electrically isolated from each other and is arranged as crossing over multiple active pillar of the plurality of wordline plate.
21. 1 kinds of flash memories, including:
Memory cell array, they multiple flash memory cells including being arranged in the infall of multiple wordline and multiple bit line；
Positive voltage maker, its be configurable to generate will be applied to that selected word line positive high voltage and with at least one or many
At least one or more positive low-voltage that individual data mode is corresponding；
Negative voltage generator, it is configurable to generate corresponding with multiple negative data states and will be applied to that selected word line
Multiple negative voltages；And
Controlling logic, it is configured to control described positive voltage maker and negative voltage generator,
Wherein, when generating the second negative voltage after generating the first negative voltage less than the second negative voltage, described negative voltage is raw
The grow up to be a useful person output of electric discharge negative voltage generator, so that it becomes to be above this second negative voltage, and performs negative charge pumping, until
The output of negative voltage generator reaches the second negative voltage.
22. flash memories as claimed in claim 21, wherein, described memory cell array includes 3-dimensional memory cell battle array
Row, it has the multiple wordline plates being electrically isolated from each other and is arranged in the multiple active pillar crossing over the plurality of wordline plate.
23. 1 kinds of data storage devices, including:
With multiple channel attached multiple flash memories；And
Controller, it is configured to control the reading of each in the plurality of flash memory, write via respective channel
Operate with erasing,
Wherein, each in the plurality of flash memory includes:
Memory cell array, they multiple flash memory cells including being arranged in the infall of multiple wordline and multiple bit line；
Voltage generating unit, it is configurable to generate the multiple word line voltages that will be applied to that wordline, and
Controlling logic, its voltage being configured to control voltage generating unit generates operation,
Wherein, described voltage generating unit includes negative voltage generator, and it is configurable to generate the first negative voltage, discharge this first
Negative voltage, and generate the second negative voltage via negative charge pumping.
24. data storage devices as claimed in claim 23, wherein, described data storage device be from solid-state drive,
In the group of pcmcia card, compact flash, smart media card, memory stick, multimedia card, SD card and USB flash memory
One selected.
25. data storage devices as claimed in claim 23, wherein, at least one in the plurality of flash memory is three
Dimension memory cell array, it has the multiple wordline plates being electrically isolated from each other and is arranged in the multiple of the plurality of wordline plate of leap
Active pillar.
The word line voltage of 26. 1 kinds of flash memories generates method, including
Positive voltage maker is used to generate program voltage；
Negative voltage generator is used to generate multiple negative programming verifying voltages；And
Use positive voltage maker to generate at least one or more and just program verifying voltage,
Wherein, the step of the multiple negative programming verifying voltage of described generation includes: have low level negative programming checking electricity in generation
The negative programming verifying voltage with high level is generated before pressure.
27. word line voltages as claimed in claim 26 generate method, wherein, generate in the plurality of negative programming verifying voltage
Each and be performed without discharge operation or the wordline recovery operation of the negative programming verifying voltage to being previously generated.
The word line voltage of 28. 1 kinds of flash memories generates method, including:
The first negative verifying voltage is generated via the negative charge pumping of negative voltage generator；
Discharge during the first discharge time the output of negative voltage generator；And
The second negative verifying voltage is generated via the negative charge pumping of negative voltage generator after the first discharge time,
Wherein, described first discharge time is determined according to the voltage difference between the first negative verifying voltage and the second negative verifying voltage.
29. word line voltages as claimed in claim 28 generate method, wherein, in described discharge process, are generated by negative voltage
The output of device discharges into higher than the second negative verifying voltage and equal to or less than the level of ground voltage.
30. word line voltages as claimed in claim 28 generate method, wherein, when the second negative verifying voltage is less than the first negative checking
Described electric discharge is skipped during voltage.
31. word line voltages as claimed in claim 28 generate method, also include:
When generating at least one after generating the second negative verifying voltage and just programming verifying voltage, shorter than the first discharge time
The second discharge time during discharge the output of negative voltage generator.
32. word line voltages as claimed in claim 31 generate method, and wherein, during described second discharge time, negative voltage is raw
The output grown up to be a useful person is discharged into ground level.
The verifying voltage of 33. 1 kinds of flash memories including negative voltage generator generates method, including:
The first negative verifying voltage is generated via negative voltage generator；
Discharge during the first discharge time the output of negative voltage generator；
The second negative verifying voltage higher than the first negative verifying voltage is generated via negative voltage generator；
Discharge during the second discharge time the output of negative voltage generator；And
The 3rd negative verifying voltage higher than the second negative verifying voltage is generated via negative voltage generator.
34. verifying voltages as claimed in claim 33 generate method, wherein, according to the first negative verifying voltage and the second negative checking
Voltage difference between voltage determined for the first discharge time, and according between the second negative verifying voltage and the 3rd negative verifying voltage
Voltage difference determined for the second discharge time.
35. verifying voltages as claimed in claim 34 generate method, wherein, when the first negative verifying voltage and the second negative checking electricity
Voltage difference between pressure increases by the first discharge time when becoming big, and when between the second negative verifying voltage and the 3rd negative verifying voltage
Voltage difference become big time increase by the second discharge time.
36. verifying voltages as claimed in claim 33 generate method, wherein, described first negative verifying voltage and the second negative checking
Voltage is the verifying voltage for identical negative data state.
The verifying voltage of 37. 1 kinds of flash memories generates method, including:
The first negative verifying voltage is generated via the negative charge pump operation of negative voltage generator；And
Generate higher than the first negative verifying voltage the second negative verifying voltage and without negative charge pump operation,
Wherein, described second negative verifying voltage is set up according to the electric discharge of negative voltage generator.
38. verifying voltages as claimed in claim 37 generate methods, wherein, via the outfan to negative voltage generator from
So electric discharge or forced electric discharge set up described second negative verifying voltage.
The verifying voltage of 39. 1 kinds of flash memories including positive voltage maker and negative voltage generator generates method, bag
Include:
Negative voltage generator is used to generate negative verifying voltage；
The output of negative voltage generator is discharged into ground level；And
Positive verifying voltage is generated via the positive charge pump operation of positive voltage maker.
40. verifying voltages as claimed in claim 39 generate method, and wherein, described negative verifying voltage and positive verifying voltage are respectively
It is distributed corresponding to neighboring threshold voltage.
41. 1 kinds of flash memories, including:
Memory cell array, they multiple flash memory cells including being arranged in the infall of multiple wordline and multiple bit line；
Voltage generating unit, it is configurable to generate the multiple word line voltages that will be applied to that wordline；And
Controlling logic, its voltage being configured to control voltage generating unit generates operation,
Wherein, described voltage generating unit was discharged the first negative voltage during discharge time, then generated higher than the first negative voltage
The second negative voltage, and
Wherein, described discharge time is determined according to the voltage difference between the first negative voltage and the second negative voltage.
42. flash memories as claimed in claim 41, wherein, when performing discharge operation during discharge time,
The output voltage of voltage generating unit is higher than the second negative voltage and equal to or less than ground voltage.
43. flash memories as claimed in claim 41, wherein, described voltage generating unit includes:
DC voltage maker, it is configurable to generate DC voltage；
Reference voltage maker, its be configurable to generate with the first and second negative voltages in the middle of the target negative voltage that will be generated
Corresponding reference voltage；
Agitator, it is configurable to generate the first clock；
Negative charge pump, it is configured to respond to second clock and performs negative charge pumping, and generates as negative charge pumping knot
The target negative voltage of fruit；And
Voltage detector, it is configured to respond to described DC voltage, reference voltage and the first clock comparison object negative voltage
And reference voltage, and generate second clock according to comparative result.
44. flash memories as claimed in claim 43, wherein, described voltage detector includes:
Power supply unit, it is configured to respond to negative voltage and enables the signal power supply to comparison node offer DC voltage；
Dividing potential drop parts, it is connected between comparison node and detection node, and is configured to described DC voltage dividing potential drop, its
In, supply target negative voltage to described detection node；
Discharge component, it is connected to detect between node and earth terminal, and is configured to respond to described negative voltage enable signal
The voltage of inversion signal discharge examination node；
Comparing unit, it is configured to the voltage comparing comparison node and described reference voltage, and generates as comparative result
Second clock；And
Controlling parts, it is configured to respond to negative voltage enable signal and determines the activation to power supply unit and discharge component.
45. flash memories as claimed in claim 44, wherein, when perform during the scheduled time discharge operation it
After, discharge component described in described control parts deexcitation.
46. 1 kinds of data storage devices, including:
With multiple channel attached multiple flash memories；And
Controller, it is configured to control the reading of each in the plurality of flash memory, write via respective channel
Operate with erasing,
Wherein, each in the plurality of flash memory includes:
Memory cell array, they multiple flash memory cells including being arranged in the infall of multiple wordline and multiple bit line；
Voltage generating unit, it is configurable to generate the multiple word line voltages that will be applied to that wordline, and
Controlling logic, its voltage being configured to control voltage generating unit generates operation,
Wherein, described voltage generating unit includes negative voltage generator, and
Wherein, when generating the second negative voltage that then the first negative voltage generates higher than the first negative voltage, negative voltage generator exists
According to discharge voltage signal generating unit defeated during the discharge time that the voltage difference between the first negative voltage and the second negative voltage determines
Go out end, then generate this second negative voltage.
47. data storage devices as claimed in claim 46, wherein, described data storage device be from solid-state drive,
In the group of pcmcia card, compact flash, smart media card, memory stick, multimedia card, SD card and USB flash memory
One selected.
Applications Claiming Priority (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2010-0095406 | 2010-09-30 | ||
| KR1020100095406A KR101785003B1 (en) | 2010-09-30 | 2010-09-30 | Flash memory device and wordline voltage generating method thereof |
| KR20100130812 | 2010-12-20 | ||
| KR10-2010-0130812 | 2010-12-20 | ||
| KR1020110000609A KR101682189B1 (en) | 2011-01-04 | 2011-01-04 | Flash memory device and wordline voltage generating method thereof |
| KR10-2011-0000609 | 2011-01-04 | ||
| KR10-2011-0001010 | 2011-01-05 | ||
| KR1020110001010A KR101736453B1 (en) | 2011-01-05 | 2011-01-05 | Flash memory device and wordline voltage generating method thereof |
| US201161447136P | 2011-02-28 | 2011-02-28 | |
| US61/447,136 | 2011-02-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102446553A CN102446553A (en) | 2012-05-09 |
| CN102446553B true CN102446553B (en) | 2016-12-14 |
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