KR20120078918A - Voltage detector - Google Patents

Abstract

An embodiment of the present invention relates to a voltage detector, and is a technique for improving the response speed and peak-to-peak of a pumping voltage VPP in an active mode of a semiconductor device. This embodiment of the present invention is a voltage divider for distributing the pumping voltage at a constant ratio and outputs the detection voltage, compares the level of the detection voltage and the reference voltage and adjusts the voltage level of the detection signal according to the comparison result, the active mode An amplifier unit increases the current consumption according to the time enable signal, and a driver unit adjusts a logic level of the output signal according to the voltage level of the detection signal.

Description

Voltage detector

An embodiment of the present invention relates to a voltage detector, and is a technique for improving the response speed and peak-to-peak of a pumping voltage VPP in an active mode of a semiconductor device.

In the case of a semiconductor memory device, as the external power supply voltage is lowered and high speed operation is required, the word line voltage is boosted to secure a low voltage margin and improve the speed of sensing data from the memory cell.

However, since the pumping voltage VPP must maintain a potential higher than the external power supply voltage VDD, the semiconductor memory device boosts and uses the external power supply voltage VDD. In most semiconductor memory devices, the pumping voltage VPP is generated by using a charge pump method.

1 is a circuit diagram illustrating in detail a pumping voltage detector of a semiconductor device according to the prior art.

The pumping voltage detector according to the prior art includes a voltage divider 10 and a voltage comparator 20.

Here, the voltage divider 10 divides the pumping voltage VPP at a predetermined ratio to generate the divided voltage DIV_VPP. The voltage comparator 20 compares the level of the reference voltage VREF corresponding to the target level of the pumping voltage VPP and the distribution voltage DIV_VPP, and outputs a detection signal VPP_DET corresponding to the comparison result.

The voltage divider 10 includes fixed resistors R1 and R2 connected in series with a predetermined resistance value between the pumping voltage VPP applying terminal and the ground voltage VSS applying terminal. The voltage divider 10 outputs the divided voltage DIV_VPP at the connection node between the fixed resistor R1 and the fixed resistor R2.

In addition, the voltage comparator 20 includes a unit amplifier 21 and a driver 22.

The unit amplifier 21 changes the level of the voltage applied to the output node OUTN in response to the level difference between the distribution voltage DIV_VPP and the reference voltage VREF. The driver 22 drives the detection signal VPP_DET corresponding to the level of the voltage applied to the output node OUTN.

Here, the unit amplifier 21 includes PMOS transistors P1 and P2 and NMOS transistors N1 to N3 as current mirror unit amplifiers.

The NMOS transistor N1 receives the division voltage DIV_VPP through the gate. The NMOS transistor N2 receives a reference voltage VREF through a gate. The NMOS transistor N3 controls the connection between the drain-source connected common node COMM and the ground voltage VSS applying terminal in response to the bias voltage Vbias input to the gate.

The PMOS transistor P1 operates as a diode by connecting a gate and a drain to an intermediate node ZN connected to a power supply voltage VDD and a drain terminal of the NMOS transistor N1. The PMOS transistor P2 has a gate connected to the intermediate node ZN, and controls the connection between the source-drain connected power supply voltage VDD and the output node OUTN. The PMOS transistor P2 adjusts the level of the voltage applied to the output node OUTN.

In addition, the driving unit 22 includes an inverter IV1 for driving the detection signal VPP_DET corresponding to the level of the voltage applied to the output node OUTN.

Based on the above-described configuration, a specific operation of the voltage detector of the semiconductor device according to the prior art will be described.

First, when the level of the pumping voltage VPP is sufficiently higher than the predetermined level, that is, when the level of the distribution voltage DIV_VPP is higher than the level of the reference voltage VREF, the word using the pumping voltage VPP in the semiconductor device is used. When the line is enabled, the level of pumping voltage (VPP) begins to fall. In other words, the level of the divided voltage DIV_VPP starts to fall.

In this manner, when the level of the distribution voltage DIV_VPP decreases, the voltage becomes lower than the level of the reference voltage VREF corresponding to the target level of the pumping voltage VPP. Therefore, the amount of current flowing through the output node OUTN and the common node COMM has a larger value than the amount of current flowing through the intermediate node ZN and the common node COMM.

As a result, the level of the voltage applied to the output node OUTN decreases more than the level of the voltage applied to the intermediate node ZN falls, and the voltage applied to the intermediate node ZN that decreases less. Is input to the gate of the PMOS transistor P2. Then, the level of the voltage applied to the output node OUTN is further reduced by reducing the amount of current flowing between the power supply voltage VDD applying end and the output node OUTN.

As such, when the level of the voltage applied to the output node OUTN decreases and falls below the logic threshold level of the inverter IV1, the detection signal VPP_DET driven by the inverter IV1 becomes logic 'high'.

When the level of the pumping voltage VPP is sufficiently lower than the predetermined level, that is, the level of the distribution voltage DIV_VPP is lower than the level of the reference voltage VREF, the pumping unit performs the charge pumping operation. The level of VPP) starts to rise. That is, the level of the divided voltage DIV_VPP starts to rise.

In this way, when the level of the divided voltage DIV_VPP rises, it becomes higher than the level of the reference voltage VREF at some point. Therefore, the amount of current flowing through the output node OUTN and the common node COMM is smaller than the amount of current flowing through the intermediate node ZN and the common node COMM.

As a result, the level of the voltage applied to the intermediate node ZN decreases more than the level of the voltage applied to the output node OUTN decreases. The voltage applied to the intermediate node ZN that descends more is input to the gate of the PMOS transistor P2 to increase the amount of current flowing between the power supply voltage VDD applying end and the output node OUTN.

Accordingly, the amount of current larger than the amount of current flowing from the output node OUTN to the common node COMM by the NMOS transistor N2 is caused to flow from the power supply voltage VDD to the output node OUTN. That is, the level of the voltage applied to the output node OUTN is raised.

As such, when the level of the voltage applied to the output node OUTN rises and rises above the logic threshold level of the inverter IV1, the detection signal VPP_DET driven by the inverter IV1 becomes a logic 'low'.

However, in the related art, the response speed or peak-to-peak of the pumping voltage VPP is fixed at a constant time in the standby mode or the active mode. Accordingly, in the active mode, the peak-to-peak characteristic of the pumping voltage VPP may deteriorate.

Embodiments of the present invention can improve the response speed and peak-to-peak of the pumping voltage (VPP) in the active mode in a device without the deep power down mode. There is a characteristic.

According to an embodiment of the present invention, a voltage detector includes: a voltage divider configured to distribute a pumping voltage at a predetermined ratio and output a detected voltage; An amplifier for comparing the level of the detected voltage with the reference voltage, adjusting a voltage level of the detected signal according to the comparison result, and increasing a current consumption according to the enable signal in the active mode; And a driver for adjusting a logic level of the output signal according to the voltage level of the detection signal.

Embodiments of the present invention provide an effect of improving the response speed and peak-to-peak of the pumping voltage VPP in the active mode in a device without the deep power down mode.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is a circuit diagram of a conventional voltage detector.
2 is a configuration diagram of a pumping voltage generation circuit to which a voltage detector according to an embodiment of the present invention is applied.
3 is a circuit diagram of a voltage detector according to an embodiment of the present invention.
FIG. 4 is a detailed circuit diagram of an enable signal generator that generates the enable signal of FIG. 3. FIG.
5 is an operation timing diagram of a voltage detector according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a pumping voltage (VPP) generation circuit of a semiconductor device including a voltage detector according to an embodiment of the present invention.

The pumping voltage generation circuit includes a voltage detector 100 and a pumping voltage (VPP) output unit 200. Here, the pumping voltage (VPP) output unit 200 includes an oscillator 210 and a pumping unit 220.

The voltage detector 100 detects the level of the pumping voltage VPP according to the reference voltage VREF and outputs a detection signal VPP_DET. The pumping voltage VPP output unit 200 outputs the pumping voltage VPP by performing a charge pumping operation in response to the detection signal VPP_DET of the voltage detector 100.

Here, the oscillator 210 outputs an oscillation signal OSC that toggles with a predetermined period in response to the detection signal VPP_DET of the pumping voltage VPP output unit 20. In addition, the pumping unit 220 increases the level of the pumping voltage VPP by performing a charge pumping operation in response to the oscillation signal OSC.

The operation of the pumping voltage (VPP) generation circuit of the semiconductor device according to the exemplary embodiment of the present invention will be described as follows.

First, the voltage detector 100 compares the level of the pumping voltage VPP and the level of the reference voltage VREF and determines the level of the detection signal VPP_DET according to the comparison result.

For example, when the level of the pumping voltage VPP input by receiving feedback from the pumping voltage VPP output unit 200 becomes higher than the level of the reference voltage VREF input to the voltage detector 100, the detection is performed. The level of the signal VPP_DET is shifted to a logic 'high' and output.

Similarly, when the level of the pumping voltage VPP received and fed back from the pumping voltage VPP output unit 200 becomes lower than the level of the reference voltage VREF input to the voltage detector 100, the detection signal VPP_DET The level of is shifted to logic 'Low' and output.

In this case, the reference voltage VREF is a voltage generated in a band gap circuit of the semiconductor device, and is a voltage that maintains a stable voltage level at all times regardless of variations in PVT (PROCESS, VOLTAGE, TEMPERATURE) of the semiconductor device.

The oscillator 210 of the components of the pumping voltage VPP output unit 200 outputs an oscillation signal OSC that toggles with a predetermined period in response to the level of the detection signal VPP_DET of the voltage detector 100.

In addition, the pumping unit 220 among the components of the pumping voltage VPP output unit 200 generates the pumping voltage VPP by performing a charge pumping operation in response to toggling of the oscillation signal OSC.

For example, when the detection signal VPP_DET level of the voltage detector 100 is logic 'low', the oscillation signal OSC output from the oscillator 210 does not oscillate at a predetermined period, but is logic 'low' or logic. Fixed to 'High'.

Therefore, the pumping unit 220 does not perform the charge pumping operation, and as a result, the level of the pumping voltage VPP decreases.

Similarly, when the level of the detection signal VPP_DET of the voltage detector 100 is logic 'high', the oscillation signal OSC output from the oscillator 210 oscillates at a predetermined period.

Therefore, the pumping unit 220 performs a charge pumping operation, and thus the level of the pumping voltage VPP rises.

3 is a detailed circuit diagram of the voltage detector 100 of FIG. 2.

The voltage detector according to the embodiment of the present invention includes a voltage divider 110, an amplifier 120, and a driver 130.

Here, the voltage divider 110 divides the pumping voltage VPP at a predetermined ratio to generate the detection voltage DET_L. The voltage divider 110 includes a plurality of NMOS transistors N4 to N7 connected in series with a predetermined resistance value between the pumping voltage VPP applying terminal and the ground voltage VSS applying terminal.

Each of the NMOS transistors N4 to N7 has a gate terminal and a drain terminal connected in common to serve as a resistor. The voltage divider 110 outputs the detection voltage DET_L at the connection node between the source terminal of the NMOS transistor N6 and the drain terminal of the NMOS transistor N7. Here, the detection voltage DET_L has a 1/4 value of the pumping voltage VPP level.

For reference, the voltage divider 110 distributes the pumping voltage VPP at a predetermined ratio through the plurality of NMOS transistors N4 to N7 serving as resistances. In the embodiment of the present invention, the plurality of NMOS transistors N4 to N7 What has the same resistance value with each other is demonstrated by the Example.

However, the plurality of NMOS transistors N4 to N7 do not have to have the same resistance value, and may have different resistance values. That is, it is possible to change the resistance value at the time of design.

It is also possible to adjust and distribute the predetermined ratio of the pumping voltage VPP by using more resistors than the plurality of NMOS transistors N4 to N7, for example three or less or five or more resistors.

Meanwhile, the amplifier 120 compares the level of the reference voltage VREF corresponding to the target level of the pumping voltage VPP and the level of the detection voltage DET_L, and outputs a detection signal DETCM corresponding to the comparison result. The amplifier 120 changes the voltage level of the detection signal DETCM in response to the level difference between the detection voltage DET_L and the reference voltage VREF.

Here, the amplifier 120 includes a current mirror type amplifier, an activation controller 121, and an active controller 122.

Current mirror amplifiers include PMOS transistors P3 and P4 and NMOS transistors N8 and N9.

The NMOS transistor N8 receives a detection voltage DET_L through a gate. The NMOS transistor N9 receives a reference voltage VREF through a gate.

The PMOS transistor P3 is connected to the source terminal of the power supply voltage VDD and the source terminal thereof, and is connected to the node DN connected to the drain terminal of the NMOS transistor N8 to operate as a diode. The PMOS transistor P4 has a gate connected to the node DN to control the connection between the supply terminal of the power supply voltage VDD and the output node of the detection signal DETCM. PMOS transistor P4 adjusts the voltage level of the detection signal DETCM.

The activation control unit 121 includes an NMOS transistor N10. The NMOS transistor N10 selectively controls the connection between the source terminal of the NMOS transistors N8 and N9 and the ground voltage VSS applying terminal in response to the bias voltage Vbias input to the gate.

The active controller 122 includes an NMOS transistor N13. The NMOS transistor N13 selectively controls the connection between the source terminal of the NMOS transistors N8 and N9 and the ground voltage (VSS) applying terminal in response to the enable signal EN input to the gate.

When the enable signal EN is applied at a high level in the active operation mode, the active control unit 122 turns on the NMOS transistor N13 to increase the current consumption of the amplifier 120.

In addition, the driver 130 drives the output signal VPP_DET corresponding to the level of the voltage of the detection signal DETCM. The driver 130 includes PMOS transistors P5 and P6, NMOS transistors N11 and N12, and an output driving element. Here, the output drive element includes an inverter IV2.

The PMOS transistors P5 and P6 and the NMOS transistors N11 and N12 are connected in series between a power supply voltage VDD application terminal and a ground voltage VSS application terminal. Here, the ground voltage VSS is applied to the PMOS transistor P5 through the gate terminal. The detection signal DETCM is applied to the PMOS transistor P6 and the NMOS transistor N11 through a common gate terminal. In addition, the NMOS transistor N12 receives a power supply voltage VDD through a gate terminal.

The PMOS transistors P5 and P6 and the NMOS transistors N11 and N12 are three-state inverters to which three control signals are applied: ground voltage (VSS), detection signal DETCM, and power supply voltage (VDD). Perform the function.

The inverter IV2 drives the detection signal VPP_DET corresponding to the output level of the common drain terminal of the PMOS transistor P6 and the NMOS transistor N11. Here, the drive of the inverter IV2 is controlled by the power supply voltage (VDD) and ground voltage (VSS) level.

Referring to the specific operation of the voltage detector 100 according to the embodiment of the present invention based on the above-described configuration as follows.

First, as in the T1 period, when the level of the pumping voltage VPP is sufficiently higher than the predetermined level, that is, when the level of the detection voltage DET_L is higher than the level of the reference voltage VREF, the pumping voltage VPP in the semiconductor device. Enabling the word line using the) causes the level of the pumping voltage (VPP) to start to fall. That is, as in the T1 section, the level of the detection voltage DET_L starts to fall.

In this manner, when the level of the detection voltage DET_L decreases, it is lower than the level of the reference voltage VREF corresponding to the target level of the pumping voltage VPP. Therefore, the amount of current flowing through the output node and the common node COMM of the detection signal DETCM has a larger value than the amount of current flowing through the node DN and the common node COMM.

As a result, the level of the voltage applied to the output node of the detection signal DETCM decreases more than the level of the voltage applied to the node DN decreases, and the voltage applied to the node DN that decreases less decreases. It is input to the gate of the PMOS transistor P4. Then, the voltage level of the detection signal DETCM is further reduced by reducing the amount of current flowing between the power supply voltage VDD applying end and the output node of the detection signal DETCM.

In this way, when the voltage level of the detection signal DETCM decreases and falls below the logic threshold level of the NMOS transistor N11, the output signal VPP_DET becomes logic 'high'.

When the level of the pumping voltage VPP is sufficiently lower than the predetermined level, that is, the level of the detection voltage DET_L is lower than the level of the reference voltage VREF, the pumping unit 220 performs the charge pumping operation. The level of the pumping voltage VPP starts to rise. That is, the level of the detection voltage DET_L starts to rise.

In this way, when the level of the detection voltage DET_L rises, it becomes higher than the level of the reference voltage VREF at any moment. Therefore, the amount of current flowing through the output node of the detection signal DETCM and the common node COMM is smaller than the amount of current flowing through the node DN and the common node COMM.

As a result, the level of the voltage applied to the node DN decreases more than the level of the voltage applied to the output node of the detection signal DETCM decreases. The voltage that is applied to the more descending node DN is input to the gate of the PMOS transistor P4 to increase the amount of current flowing between the power supply voltage VDD applying end and the output node of the detection signal DETCM.

Accordingly, the amount of current larger than the amount of current flowing from the output node of the detection signal DETCM to the common node COMM by the NMOS transistor N9 flows from the power supply voltage VDD to the output node of the detection signal DETCM. That is, the voltage level of the detection signal DETCM is raised.

As such, when the voltage level of the detection signal DETCM rises and rises above the logic threshold level of the NMOS transistor N11, the output signal VPP_DET becomes logic 'low'.

As described above, the pumping voltage detector 100 may maintain the pumping voltage VPP at a predetermined level based on the level of the reference voltage VREF generated in the band gap circuit in response to the target level of the pumping voltage VPP. To change the logic level of the output signal VPP_DET.

FIG. 4 is a detailed circuit diagram of the enable signal generator 140 generating the enable signal EN of FIG. 3.

The enable signal generator 140 includes NOR gates NOR1 and NOR2 and a NAND gate ND1.

Here, the NOR gate NOR1 performs a nil operation on the single program signal S_PGM and the buffered program signal B_PGM and outputs it.

The NOR gate NOR2 performs a NO operation on the single overwrite signal S_OW, the buffered overwrite signal B_OW, and the erase signal ERASE.

Here, the single program signal S_PGM, the buffered program signal B_PGM, the single overwrite signal S_OW, and the buffered overwrite signal B_OW correspond to the program signal.

The NAND gate ND1 performs an NAND operation on the outputs of the NOR gates NOR1 and NOR2 to output the enable signal EN.

The embodiment of the present invention having the above configuration outputs the enable signal EN to the high level through the enable signal generator 140 in the active operation mode.

When the enable signal EN is applied at a high level, the active controller 122 causes the NMOS transistor N13 to be turned on to increase the current consumption of the amplifier 120.

Then, as in the T2 section of FIG. 5, the level of the detection signal VPP_DET is more sensitively detected in the active (program) mode.

In the operation timing diagram of FIG. 5, a single program signal S_PGM, a buffered program signal B_PGM, a single overwrite signal S_OW, and a buffered overwrite which can be activated in an active mode are illustrated in FIG. 5. In the embodiment, the single program signal S_PGM is activated among the signal B_OW and the erase signal ERASE.

For example, before the active operation is performed as in the T1 section, the single program signal S_PGM, the buffered program signal B_PGM, the single overwrite signal S_OW, the buffered overwrite signal B_OW, and the erase signal ERASE all have low levels. do. As a result, the enable signal EN is output at a low level.

Then, the NMOS transistor N13 is turned off to perform a normal detection operation according to the activation state of the activation controller 121. At this time, the peak-to-peak width at which the level of the pumping voltage VPP increases and decreases has a value of + α and -α.

Subsequently, when the active operation is performed as in the T2 section, the single program signal S_PGM is at a high level. Then, the enable signal EN is output at a high level through the enable signal generator 140.

The NMOS transistor N13 is turned on when the enable signal EN is activated to a high level. Then, the current consumption in the amplifier 120 is increased to increase and decrease the level of the pumping voltage VPP. At this time, the peak-to-peak width at which the level of the pumping voltage VPP increases and decreases has a value of + β and -β. Here, the absolute value of β is smaller than the absolute value of α.

Accordingly, the embodiment of the present invention maintains the detection level of the pumping voltage VPP in the standby mode in the device having no distinction between the standby mode and the active mode.

On the other hand, in the active mode, the active control unit 122 is turned on to increase the tail current of the voltage detector 100. Accordingly, the embodiment of the present invention may reduce the peak-to-peak of the pumping voltage VPP by improving the detection response speed of the voltage detector 100.

Claims (6)

A voltage divider for dividing the pumping voltage at a predetermined ratio and outputting a detection voltage;
An amplifier configured to compare the level of the detected voltage with a reference voltage, adjust a voltage level of the detected signal according to the comparison result, and increase a current consumption according to the enable signal in the active mode; And
And a driver for adjusting a logic level of the output signal according to the voltage level of the detection signal. The voltage detector of claim 1, wherein the amplifier comprises an active controller which pulls down the amplifier to a ground voltage level when the enable signal is at a high level. The voltage detector of claim 1 or 2, further comprising an enable signal generator for controlling the enable signal in the active mode. The method of claim 3, wherein the enable signal generator
And a logic combination of a program signal and an erase signal activated in the active mode to control whether the enable signal is activated. The voltage detector of claim 4, wherein the program signal is at least one of a single program signal, a buffered program signal, a single overwrite signal, and a buffered overwrite signal. 6. The enable signal generator of claim 5, wherein the enable signal generator is high when at least one of the single program signal, the buffered program signal, the single overwrite signal, and the buffered overwrite signal is at a high level. A voltage detector, characterized in that output at the level.

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