KR20120068182A - Electrostatic discharge circuit - Google Patents

Electrostatic discharge circuit Download PDF

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Publication number
KR20120068182A
KR20120068182A KR1020100129683A KR20100129683A KR20120068182A KR 20120068182 A KR20120068182 A KR 20120068182A KR 1020100129683 A KR1020100129683 A KR 1020100129683A KR 20100129683 A KR20100129683 A KR 20100129683A KR 20120068182 A KR20120068182 A KR 20120068182A
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KR
South Korea
Prior art keywords
diffusion region
type well
region
type
electrostatic discharge
Prior art date
Application number
KR1020100129683A
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Korean (ko)
Inventor
최낙헌
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100129683A priority Critical patent/KR20120068182A/en
Publication of KR20120068182A publication Critical patent/KR20120068182A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: An electrostatic discharge circuit is provided to stably discharge high electrostatic currents by preventing currents from being concentrated on an easily damaged part of the electrostatic discharge circuit. CONSTITUTION: A first type well(210) is adjacent to a second type well(220). A first diffusion region(201) is formed on the first type well and is connected to an input and output terminal. A second diffusion region is formed in a boundary between the first type well and the second type well, includes three impurity regions, and is connected to a power voltage terminal. A third diffusion region(205) is formed on the second type well and is connected to a ground voltage terminal. A fourth diffusion region is separated from the third diffusion region in the second type well and is connected to the ground voltage terminal.

Description

Electrostatic Discharge Circuit {ELECTROSTATIC DISCHARGE CIRCUIT}

The present invention relates to a circuit for preventing damage to a semiconductor device by electrostatic discharge.

When the semiconductor device is in contact with a human body or a machine, the static electricity charged in the human body or machine is discharged to the internal circuit through the input / output pad of the semiconductor device, or the static electricity charged in the internal circuit is discharged to the outside to generate a large current. This can greatly damage the semiconductor device. Therefore, mass-produced semiconductor devices include electrostatic discharge circuits on input / output pads and power pads of semiconductor devices to protect internal circuits from static electricity.

Such an electrostatic discharge circuit includes a diode, a metal oxide silicon (MOS) device, a bipolar junction transistor (BJT) device, a silicon controlled rectifier (SCR), and the like. In particular, the SCR circuit has the advantage of having a large number of electrostatic discharge currents that can be extinguished per unit area, and a small junction capacitance and a small operating resistance, and thus are widely used in semiconductor devices operating at high voltages.

1 is a configuration diagram of a static discharge circuit according to the prior art.

Referring to FIG. 1, a conventional electrostatic discharge circuit includes an SCR circuit 100 and a diode formed between an input / output terminal I / O, a power supply voltage terminal VDD, a ground voltage terminal VSS, and an internal circuit 120. 109, the capacitor 111.

The SCR circuit 100 includes a PNP transistor 101, an NPN transistor 103, an NMOS transistor 105, and a resistor 107, and grounds an electrostatic current flowing into the input / output terminal I / O. To the VSS or the power supply voltage terminal VDD. The PNP transistor 101 and the NPN transistor correspond to bipolar junction transistors BJT.

An electrostatic discharge operation by the SCR circuit 100 will be described.

When a positive amount of static electricity flows into the input / output terminal (I / O), the electrostatic current initially in an alternating state has a fast signal rising time of 10 ns. Flows from the emitter to the capacitor 111 through the base. Here, the capacitor 111 may use a reservoir capacitor connected between the power supply voltage terminal VDD and the ground voltage terminal VSS to reduce noise of the power supply voltage.

This alternating current quickly triggers the operation of the PNP transistor 101, and the current of the collector is discharged to the ground voltage terminal VSS through the resistor 107. In addition, the alternating current causes a voltage drop corresponding to the [AC current * resistance 107] between the emitter and the base of the NPN transistor 103 to quickly turn on the NPN transistor 103.

Since the PNP transistor 101 and the NPN transistor 103 in which the collectors and the bases are coupled to each other, the operation of one side promotes the operation of the other side, can discharge a large electrostatic current even with a low operating resistance and a small area. Will be.

The diode 109 serves to discharge the negative electrostatic current to the ground voltage terminal VSS when negative static electricity flows into the input / output terminal I / O.

2 is a cross-sectional view of the SCR circuit 100 of FIG.

Referring to FIG. 2, a circuit board is divided into an N type well 210 and a P type well 220. The first diffusion region 201, which is a P-type impurity, is formed on the N-type well 210, and the second diffusion region 203, which is an N-type impurity, is formed at the boundary between the N-type well 210 and the P-type well 220. The third diffusion region 205, which is an N-type impurity, and the fourth diffusion region 207, which is a P-type impurity, are formed on the P-type well 220.

The first diffusion region 201, the N-type well 210, and the P-type well 220 constitute the PNP transistor 101, and the second diffusion region 203, the P-type well 220, and the third diffusion region Reference numeral 205 constitutes an NPN transistor 103, and the second diffusion region 203, the third diffusion region 205, and the gate 209 constitute an NMOS transistor 105. The first diffusion region 201 is connected to the input / output terminal I / O, the second diffusion region 203 is connected to the power supply voltage terminal VDD, and the gate 209 and the third diffusion region of the NMOS transistor 105 are provided. 205 and the fourth diffusion region 207 are connected to the ground voltage terminal VSS. The capacitor 111 is connected between the second diffusion region 203 and the ground voltage terminal VSS.

In the case of the first diffusion region 201 and the second diffusion region 203, a double diffusion layer is formed to surround the high concentration impurity regions N + and P + with the low concentration impurity regions N-- and P--. The junction structure which diffused the impurity into () is used. This is to make the Breakdown Voltage higher than the Operation Voltage.

However, as described above with reference to FIG. 1, when an electrostatic voltage is generated at the input / output terminal I / O, the second diffusion region 203 and the P-type well pass through the first diffusion region 201 and the N-type well 210. Primary discharge is performed by the NPN transistor 103 composed of the 220 and the third diffusion regions 205. At this time, there is a problem that the A portion is easily damaged, because a large electric field and a current is formed in the A portion, a lot of heat is generated, while the upper portion is a non-conductor, it is difficult to escape the generated heat. In particular, in the double junction structure of the high voltage device, damage occurs when static electricity is introduced.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object thereof is to provide an electrostatic discharge circuit which relieves the current concentration phenomenon of a portion which is easily damaged in the electrostatic discharge circuit, and discharges high electrostatic current more stably.

The electrostatic discharge circuit according to the present invention for achieving the above object, the first type well and the second type well, the first diffusion region formed in the first type well, connected to the input and output terminals, the first type A second diffusion region formed across an interface between the well and the second type well and including three impurity regions and connected to a power supply voltage terminal, and a third formed in the second type well and connected to a ground voltage terminal And a fourth diffusion region formed in the diffusion region and the second type well in isolation from the third diffusion region, and connected to the ground voltage terminal. The terminal may further include a capacitor having one end connected to the second diffusion region and the other end connected to the ground voltage terminal.

The second diffusion region may include a first impurity region having the highest concentration, a second impurity region having the lowest concentration, and surrounding the first impurity region, and having a lower concentration than that of the first impurity region. The concentration may be higher than or equal to the region, and may include a third impurity region formed deeper in the well direction than the second impurity region between the first impurity region and the second impurity region.

The first type well is an N type well, the second type well is a P type well, the first diffusion region and the fourth diffusion region are formed of P type impurities, and the second diffusion region and the third The diffusion region may be formed of N-type impurities.

According to the present invention, a deeper additional impurity region is formed in a junction region through which high electrostatic current flows in a semiconductor circuit board to mitigate current concentration phenomenon and easily dissipate heat generated by electrostatic current, thereby preventing damage to the circuit and further. It can discharge high electrostatic current.

1 is a block diagram of a static discharge circuit according to the prior art.
2 is a cross-sectional view of the SCR circuit 100 of FIG.
3 is a partial cross-sectional view of an electrostatic discharge circuit according to an embodiment of the present invention.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a partial cross-sectional view of an electrostatic discharge circuit according to an embodiment of the present invention.

Referring to FIG. 3, an electrostatic discharge circuit is formed in the first type well 210, the second type well 220, and the first type well 210 adjacent to each other, and is connected to the input / output terminal I / O. It is formed over the interface of the first diffusion region 201, the first type well 210 and the second type well 220, and includes three impurity regions (N +, N-, N--), The second diffusion region 303 connected to the stage VDD and the second diffusion region 205 formed in the second type well 220 and connected to the ground voltage terminal VSS are connected to the terminal VDD. And a fourth diffusion region 207 formed to be isolated from the third diffusion region 205 and connected to the ground voltage terminal VSS. The capacitor 111 may further include a capacitor 111 having one end connected to the second diffusion region 303 and the other end connected to the ground voltage terminal VSS.

Here, the first type well 210 is an N type well, and the second type well 220 is preferably a P type well. In addition, the first diffusion region 201 and the fourth diffusion region 207 may be formed of P-type impurities, and the second diffusion region 303 and the third diffusion region 205 may be formed of N-type impurities.

The first diffusion region 201, the N-type well 210, and the P-type well 220 constitute the PNP transistor 101, and the second diffusion region 303, the P-type well 220, and the third diffusion region Reference numeral 205 constitutes an NPN transistor 103, and the second diffusion region 303, the third diffusion region 205, and the gate 209 constitute an NMOS transistor 105. The first diffusion region 201 is connected to the input / output terminal I / O, the second diffusion region 203 is connected to the power supply voltage terminal VDD, and the gate 209 and the third diffusion region of the NMOS transistor 105 are provided. 205 and the fourth diffusion region 207 are connected to the ground voltage terminal VSS. The capacitor 111 is connected between the second diffusion region 303 and the ground voltage terminal VSS.

As shown, the second diffusion region 303 may include a first impurity region N + having the highest concentration and a second impurity region formed having the lowest concentration and surrounding the first impurity region N +. And a third impurity region N− formed between N−). The third impurity region N− has a concentration lower than that of the first impurity region N +, is higher than or equal to the second impurity region N−, and is well 210 and 220 than the second impurity region N−. Deeper in the) direction.

In the electrostatic discharge circuit including the second diffusion region 303 formed as described above, when an electrostatic current is applied to the input / output terminal I / O, the junction portion of the second impurity region N− and the second type well 220 ( The largest current flows in B) and the electric field is also formed the largest. This makes it easier to dissipate the heat generated by the high electrostatic current flowing deeper into the well. Therefore, it is possible to flow a higher electrostatic current than the conventional circuit, it is possible to greatly reduce the damage of the circuit elements.

As described above, the present invention forms a deeper additional impurity region in the junction region through which high electrostatic current flows in the semiconductor circuit board, thereby alleviating current concentration and dissipating heat generated by the electrostatic current, thereby preventing damage to the circuit. An electrostatic discharge circuit is proposed that can prevent and discharge higher electrostatic currents.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by.

Claims (5)

Type 1 and type 2 wells adjacent to each other;
A first diffusion region formed in the first type well and connected to an input / output terminal;
A second diffusion region formed over an interface between the first type well and the second type well and including three impurity regions and connected to a power supply voltage terminal;
A third diffusion region formed in the second type well and connected to a ground voltage terminal; And
A fourth diffusion region formed in the second well and isolated from the third diffusion region and connected to the ground voltage terminal
Electrostatic discharge circuit comprising a.
The method of claim 1,
The second diffusion region is
A first impurity region having the highest concentration;
A second impurity region having a lowest concentration and formed to surround the first impurity region; And
A concentration lower than the first impurity region and higher than or equal to the second impurity region, and formed deeper in the well direction between the first impurity region and the second impurity region than in the second impurity region; Containing 3 impurity regions
Electrostatic discharge circuit.
The method of claim 1,
The type 1 well is an N type well and the type 2 well is a P type well
Electrostatic discharge circuit.
The method of claim 1,
The first diffusion region and the fourth diffusion region are formed of P-type impurities, and the second diffusion region and the third diffusion region are formed of N-type impurities.
Electrostatic discharge circuit.
The method of claim 1,
One end is connected to the second diffusion region, the other end is connected to the ground voltage terminal
Electrostatic discharge circuit further comprising.
KR1020100129683A 2010-12-17 2010-12-17 Electrostatic discharge circuit KR20120068182A (en)

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Application Number Priority Date Filing Date Title
KR1020100129683A KR20120068182A (en) 2010-12-17 2010-12-17 Electrostatic discharge circuit

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Application Number Priority Date Filing Date Title
KR1020100129683A KR20120068182A (en) 2010-12-17 2010-12-17 Electrostatic discharge circuit

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KR20120068182A true KR20120068182A (en) 2012-06-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109166539A (en) * 2013-12-31 2019-01-08 乐金显示有限公司 Memory protection circuit and liquid crystal display including the memory protection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109166539A (en) * 2013-12-31 2019-01-08 乐金显示有限公司 Memory protection circuit and liquid crystal display including the memory protection circuit

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