KR20120063393A - Anti fuse circuit - Google Patents

Anti fuse circuit Download PDF

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Publication number
KR20120063393A
KR20120063393A KR1020100124531A KR20100124531A KR20120063393A KR 20120063393 A KR20120063393 A KR 20120063393A KR 1020100124531 A KR1020100124531 A KR 1020100124531A KR 20100124531 A KR20100124531 A KR 20100124531A KR 20120063393 A KR20120063393 A KR 20120063393A
Authority
KR
South Korea
Prior art keywords
fuse
rupture
signal
high voltage
antifuse
Prior art date
Application number
KR1020100124531A
Other languages
Korean (ko)
Inventor
정회권
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100124531A priority Critical patent/KR20120063393A/en
Publication of KR20120063393A publication Critical patent/KR20120063393A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2229/00—Indexing scheme relating to checking stores for correct operation, subsequent repair or testing stores during standby or offline operation
    • G11C2229/70—Indexing scheme relating to G11C29/70, for implementation aspects of redundancy repair
    • G11C2229/76—Storage technology used for the repair
    • G11C2229/763—E-fuses, e.g. electric fuses or antifuses, floating gate transistors

Abstract

PURPOSE: An anti-fuse circuit is provided to improve the rupture reliability of an anti-fuse by including the remaining anti-fuse which is normally operated in case of a rupture fail. CONSTITUTION: A rupture control unit(200) generates a selection signal for controlling a rupture operation. An anti fuse unit(300,310) performs a rupture operation according to a selection signal and outputs a fuse signal corresponding to the rupture result. A combination unit(400) activates an operation signal by combining the output of the anti fuse unit if any one fuse signal is activated and outputs the activated operation signal.

Description

Anti fuse circuit

An embodiment of the present invention relates to an anti-fuse circuit, and more particularly, to a technique for improving the structure of the anti-fuse to improve rupture (Rupture) reliability.

As the integration technology of semiconductor memory devices has advanced, the number of memory cells (CELLs) and signal lines in one semiconductor memory device is rapidly increasing. Since the integrated circuits are integrated in a limited space, the line width of internal circuits is narrowed and the size of memory cells is also increased. It's getting smaller.

For this reason, the possibility of a defective memory cell CELL of a semiconductor memory device increases. In spite of a defect in a cell, a memory having a expected capacity can be shipped with a high yield because a redundancy circuit is provided to rescue defective memory cells inside a semiconductor memory device.

The redundancy circuit includes a fuse for programming a repair address corresponding to the redundant memory cell and the defective memory cell.

When the wafer process is completed, various tests are performed. When repair is possible among the memory cells read as defective, the defects are repaired by replacing them with redundant memory cells.

That is, the internal circuit performs programming to replace the address corresponding to the bad memory cell with the address of the redundancy memory cell. Accordingly, when an address corresponding to a bad memory cell is input, the memory is replaced with a redundant memory cell to perform a normal operation.

In order to program the address information corresponding to the defective memory cell, a fuse programming method is used, which is generally a laser blowing type in which a fuse is disconnected using a laser beam. ). This is generally referred to as a physical fuse type.

However, the physical fuse programming method using the laser can be implemented only in a wafer state, in which the semiconductor memory device is manufactured in a package.

Therefore, in order to replace a defective memory cell in a packaged state, an electrical method, rather than a physical method using a conventional laser, is used. Programmable fuses in a package are commonly referred to as electrical fuses.

This means that programming can be done by electrically changing the connection of the fuses. These electrical fuses are in the form of anti-type fuses that change the open state to a short state and blowing-type fuses that change the short state to an open state. You can reclassify.

The electrical fuses above are intended for programming after packaging, so they are very useful in a packaged state.

However, since the electric fuses are packaged, unlike the physical fuses in the wafer state, the fuses that are programmed with the naked eye cannot be checked.

In the prior art, it was necessary to remove the package and check the connection of the fuse in order to check the connection of the fuse programmed electrically. However, removing the finished package again for testing undermines the value of the finished product and lowers the efficiency of the test.

Therefore, the anti-fuse method was developed to compensate for this. Basic antifuse devices are typically resistive fuse devices that have a very high resistance (eg, 100 Mohms) initially unprogrammed and very low resistance (eg, <10 Kohms) after proper programming operation. do.

Antifuse is programmed by applying a high voltage through both terminals of the antifuse for a sufficient time, breaking and shorting the dielectric between both terminals. Currently, anti-fuse is used to perform a repair process using laser irradiation at the wafer level using a fuse that occupies a small area and to repair only a few bit failings generated in a package state.

An embodiment of the present invention is characterized by having an extra anti-fuse that can operate normally even if a rupture failure occurs in the anti-fuse to improve the rupture reliability of the anti-fuse.

An anti-fuse circuit according to an embodiment of the present invention, the rupture control unit for generating a selection signal for controlling the rupture operation; At least two anti-fuse units performing a rupture operation according to the selection signal and outputting a fuse signal corresponding to the rupture result; And a combination unit that combines the outputs of two or more anti-fuse units to activate and output an operation signal when at least one fuse signal is activated.

The embodiment of the present invention provides an effect of improving the reliability of anti-fuse by providing an extra anti-fuse capable of operating normally even if a rupture failure occurs in the anti-fuse.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is a circuit diagram of an anti-fuse circuit according to an embodiment of the present invention.
2 is a timing diagram for explaining the operation of the anti-fuse circuit of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of an anti-fuse circuit according to an embodiment of the present invention.

The anti-fuse circuit according to the exemplary embodiment of the present invention includes a high voltage generator 100, a rupture controller 200, anti-fuse units 300 and 310, and a combination unit 400.

Here, the high voltage generator 100 supplies the anti-fuse units 300 and 310 with the high voltage VHIGH required for the rupture operation. The rupture control unit 200 generates a selection signal SEL for selectively controlling the rupture operation of the anti-fuse unit 300 or 310 in which the program is performed.

The anti-fuse unit 300 includes PMOS transistors P1 and P2, an antifuse N1, and an inverter IV1.

Here, the PMOS transistor P1 corresponds to a supply for supplying a high voltage VHIGH, the PMOS transistor P2 corresponds to a pull-up device for supplying a supply voltage VDD to the node A, and the inverter IV1 corresponds to a driving device for driving the output of the node A. .

The PMOS transistor P1 is connected between the high voltage VHIGH applying terminal and the node A, and the selection signal SEL is applied through the gate terminal. The antifuse N1 is connected between the node A and the ground voltage VSS applying terminal.

The antifuse N1 may include an NMOS transistor having a MOS capacitor structure, and may be configured as a gate oxide antifuse.

The antifuse N1 is a capacitor in which a dielectric such as silicon dioxide (SiO2), silicon nitride, tantalum oxide or silicon dioxide (silicondioxide-silicon nitride-silicon dioxide) is sandwiched between two conductors. It consists of.

In addition, the PMOS transistor P2 is connected between the supply voltage VDD applying terminal and the node A, and the rupture signal RUP1_B is applied through the gate terminal.

The inverter IV1 inverts the rupture signal RUP1 applied to the node A and outputs the fuse signal RUP1_B.

The anti-fuse unit 310 includes PMOS transistors P3 and P4, an antifuse N2, and an inverter IV2.

Here, the PMOS transistor P3 corresponds to a supply for supplying a high voltage VHIGH, the PMOS transistor P4 corresponds to a pull-up device for supplying a supply voltage VDD to the node B, and the inverter IV2 corresponds to a driving device for driving the output of the node B. .

The PMOS transistor P3 is connected between the high voltage VHIGH applying terminal and the node B so that the selection signal SEL is applied through the gate terminal. The antifuse N2 is connected between the node B and the ground voltage VSS applying terminal.

Here, the anti-fuse N2 includes an NMOS transistor of a MOS capacitor structure, it may be composed of a gate oxide anti-fuse.

In addition, the PMOS transistor P4 is connected between the power supply voltage VDD applying terminal and the node B so that the rupture signal RUP2_B is applied through the gate terminal.

The inverter IV2 inverts the rupture signal RUP2 applied to the node B and outputs the fuse signal RUP2_B.

The combination unit 400 includes a NOA gate NOR1 and an inverter IV3.

Here, the NOA gate NOR1 performs a NO operation on the fuse signals RUP1_B and RUP2_B applied from the anti-fuse units 300 and 310 and outputs them. Inverter IV3 inverts the output of NOR gate NOR1 and outputs an operation signal RUPON.

The combination unit 400 outputs the operation signal RUPON to a high level when the rupture operation is normally performed in any one of the anti-fuse units 300 and 310.

When the gate oxide rupture is performed on the antifuse N1, N2, the gates of the antifuse N1, N2 are destroyed. That is, when high voltages (assuming 5V in the embodiment of the present invention) are applied to the gates and sources (or drains) of the antifuse N1, N2, the gates of the antifuse N1, N2 are destroyed. As a result, the antifuse N1 and N2 lose the semiconductor properties of the transistor and have a conductor property, and a current flows between the gate and the source (or drain).

The operation of the anti-fuse circuit according to the embodiment of the present invention having such a configuration will be described with reference to the operation timing diagram of FIG. 2.

First, when the selection signal SEL output from the rupture controller 200 has a high voltage level as in the rupture section T1, both PMOS transistors P1 and P3 are turned off, and thus the rupture operation is not performed.

At this time, when the fuse signals RUP1_B and RUP2_B are all at the low level, all of the PMOS transistors P2 and P4 are turned on to keep the rupture signals RUP1 and RUP2 at the high level.

In an embodiment of the present invention, the high voltage level may be set to a level of about 5V. In an embodiment of the present invention, the high level may be about 3V, and the low level may be set to a level of about 0V.

The rupture signals RUP1 and RUP2 are inverted by the inverters IV1 and IV2 so that the fuse signals RUP1_B and RUP2_B maintain low levels.

When the fuse signals RUP1_B and RUP2_B are both at the low level, the operation signal RUPON, which is the output of the combination unit 400, is output at the low level.

Subsequently, when the selection signal SEL output from the rupture controller 200 transitions to a low level when the rupture section T2 enters, the rupture operation is performed.

In this case, the PMOS transistors P1 and P3 are all turned on according to the selection signal SEL. Then, the voltage levels of the rupture signals RUP1 and RUP2 temporarily rise, and the levels of the rupture signals RUP1 and RUP2 become high voltage levels.

At this time, when the rupture signals RUP1 and RUP2 are at the high voltage level, the rupture signals RUP1 and RUP2 are inverted by the inverters IV1 and IV2 so that the fuse signals RUP1_B and RUP2_B are kept at the low level.

When the rupture signals RUP1 and RUP2 become high voltage levels, the rupture operation is performed on the antifuse N1 and N2.

That is, when the rupture operation is performed on the antifuse N1, the antifuse N1 is ruptured, so that the rupture signal RUP1 gradually transitions to a low level as in (C).

When a high voltage is applied to the gate of the antifuse N1 and a low level (ground voltage) is applied to the commonly connected source and drain terminals, the oxide in the gate region is ruptured due to the high potential difference between the gate and the source (or drain). This will occur. As a result, the ground voltage VSS flows from the source (or drain) of the antifuse N1 to the node A serving as the gate.

As in (C), when the rupture signal RUP1 gradually transitions to the low level, the rupture operation is successfully performed.

On the other hand, when a rupture operation is performed on the antifuse N2, a rupture fail may occur in the antifuse N2 as shown in (D).

If a rupper fail occurs, the breakdown level of the antifuse N2 is reduced and the ground voltage VSS is not supplied to the node B. That is, even if a high voltage is applied to the gate of the anti-fuse N2 and a low level (ground voltage) is applied to the source and drain terminals connected to each other, the potential difference between the oxide and the source (or drain) in the gate region becomes 0V. This does not happen.

Here, the cause of the rupture failure in the anti-fuse N2 may be various. That is, a process issue may include a reason why the gate oxide is not uniform and thicker, or the supply current of the PMOS transistor P3 carrying the high voltage VHIGH is insufficient.

Accordingly, as shown in (D), when the rupture fail occurs in the antifuse N2, the breakdown signal of the antifuse N2 is not properly performed, so that the rupture signal RUP2 maintains the high voltage level as it is.

In this state, when the fuse signals RUP1_B and RUP2_B are all at the low level, the operation signal RUPON, which is the output of the combination unit 400, is output at the low level.

Next, upon entering the section T3 after the rupture, the selection signal SEL output from the rupture control unit 200 transitions to a high level.

In this case, the PMOS transistors P1 and P3 are all turned off according to the selection signal SEL. Then, the rupture signal RUP of the antifuse N1 which has been successfully ruptured becomes a low level, and the rupture signal RUP2 of the antifuse N2, which has failed in the rupture operation, becomes a high level.

At this time, if the rupture signal RUP1 is at a low level, the fuse signal RUP1_B is transitioned to a high level by the inverter IV1. However, when the rupture signal RUP2 is at the high level, the fuse signal RUP2_B is transitioned to the low level by the inverter IV2.

When the fuse signal RUP1_B is at a high level and the fuse signal RUP2_B is at a low level, the operation signal RUPON, which is an output of the combination unit 400, is output by the NOA gate NOR1 and the inverter IV3 at a high level. By judging whether the operation signal RUPON has a high level potential, it is possible to know whether the rupture is normally operated.

In the embodiment of the present invention, not only one anti-fuse unit is provided but also at least two or more anti-fuse units 300 and 310.

In the prior art, there is no method of providing a single anti-fuse part to relieve the rupture fail when the rupture fail occurs in the anti-fuse.

However, in the exemplary embodiment of the present invention, when a rupture fail occurs in one anti-fuse unit 310 as shown in FIG. 1, the extra anti-fuse unit 300 is normally operated and the operation signal RUPON finally outputted is high. Level.

In addition, in the embodiment of the present invention has been described as an example that the number of two anti-fuse unit (300,310) is provided as an example, the present invention is not limited to this may be provided with two or more anti-fuse unit.

Claims (6)

A rupture controller for generating a selection signal for controlling the rupture operation;
At least two anti-fuse units performing the rupture operation according to the selection signal and outputting a fuse signal corresponding to the rupture result; And
And a combination unit configured to combine the outputs of the two or more anti-fuse units to activate and output an operation signal when at least one of the fuse signals is activated. The anti-fuse circuit of claim 1, further comprising a high voltage generator configured to supply a high voltage to the anti-fuse part. The anti-fuse circuit of claim 1, wherein the two or more anti-fuse portions comprise a gate oxide anti-fuse. The method of claim 1, wherein each of the two or more anti-fuse unit
A supply unit supplying a high voltage according to the selection signal;
An anti-fuse in which the rupture operation is performed according to the high voltage;
A pull-up device for supplying a power voltage to the anti-fuse; And
And a driving unit for driving the output of the antifuse. The anti-fuse circuit of claim 4, wherein the anti-fuse comprises an NMOS transistor of a MOS capacitor type. The method of claim 1, wherein the combination portion
And a logic combination element for calculating an output of the two or more anti-fuse parts.
KR1020100124531A 2010-12-07 2010-12-07 Anti fuse circuit KR20120063393A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100124531A KR20120063393A (en) 2010-12-07 2010-12-07 Anti fuse circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100124531A KR20120063393A (en) 2010-12-07 2010-12-07 Anti fuse circuit

Publications (1)

Publication Number Publication Date
KR20120063393A true KR20120063393A (en) 2012-06-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100124531A KR20120063393A (en) 2010-12-07 2010-12-07 Anti fuse circuit

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