KR20120055769A - Voltage controlled oscillator and method for improvement of phase noise - Google Patents

Abstract

PURPOSE: A voltage controlled oscillator and a method for eliminating phase noise are provided to eliminate phase noise by blocking currents flowing into a variable frequency transistor in a voltage level conversion section. CONSTITUTION: A voltage controlled oscillator(10) comprises a first delay cell(110), a second delay cell(120), a third delay cell(130), and a fourth delay cell(140) consisting of a plurality of stages. The voltage controlled oscillator is composed of four stages. A first stage includes the first delay cell. A second stage includes the second delay cell. A third stage includes the third delay cell. A fourth stage includes the fourth delay cell. The first delay cell to the fourth delay cell can be formed into a ring shape.

Description

VOLTAGE CONTROLLED OSCILLATOR AND METHOD FOR IMPROVEMENT OF PHASE NOISE

The present invention relates to a voltage controlled oscillator, and more particularly, to a voltage controlled oscillator having improved phase noise and a method of improving phase noise thereof.

In general, a voltage controlled oscillator (VCO) is an oscillator circuit that obtains an output of a desired frequency by adjusting an output frequency through voltage regulation. Such voltage controlled oscillators are commonly used LC-resonant voltage controlled oscillators and ring voltage controlled oscillators. The dual ring oscillator connects a plurality of inverters or delay cells in a ring shape to oscillate using a delay time in each inverter.

The ring voltage controlled oscillator occupies a small area, has a high degree of integration, and has a wide frequency variable displacement. In addition, the ring voltage controlled oscillator can easily generate multi-phase. Notwithstanding the advantages described above, the ring voltage controlled oscillator is not used because it has poor phase noise characteristics compared to the LC-resonant voltage controlled oscillator. This is because a ring voltage controlled oscillator has a relatively large number of active devices, and thus a large number of sources generate noise. Therefore, the ring voltage controlled oscillator has a problem that the phase noise characteristics are poor compared to the LC-resonant voltage controlled oscillator.

It is an object of the present invention to provide a voltage controlled oscillator with improved phase noise and a method for improving phase noise thereof.

It is another object of the present invention to provide a voltage controlled oscillator which improves phase noise at a low supply voltage and a method of improving phase noise thereof.

The voltage controlled oscillator of the present invention corresponds to each of a plurality of stages connected in a ring form, and includes delay cells generating a voltage controlled oscillation signal, wherein the n (n is an integer greater than 1) stages of the delay cells. The delay cell receives first differential outputs from the delay cell of the n-1 th stage and pre-inputs the second differential outputs having a phase different from the first differential outputs from the delay cell of the n-2 th stage. Receive.

In this embodiment, the delay cell of the n-th stage is a differential amplifier for amplifying and outputting a voltage difference between the input voltage received through the first input terminals, the line input received through one of the second input terminals A first cascode section for removing a noise current generated by a transistor for frequency variation in a voltage level switching section using a voltage, and

A second cascode unit for removing a noise current generated by a control transistor for frequency variation in a voltage level switching period by using a line input voltage received through the other one of the second input terminals,

And the first input terminals receive the first differential outputs and the second input terminals are pre-input of the second differential outputs.

In this embodiment, the delay cell of the first stage of the plurality of stages receives the delay cell differential outputs of the last stage through the first input terminals and the delay cell differential outputs of the last previous stage the second input. Receive through the terminals.

In this embodiment, a delay cell of a second stage of the plurality of stages receives the delay cell differential outputs of the first stage through the first input terminals and the delay cell differential outputs of the last stage. Receives via 2 input terminals.

In this embodiment, the differential amplifier is a first transistor, a source is connected to the power supply terminal, a drain is connected to the ground terminal through a third transistor, the gate is connected to the drain of the second transistor, the source is the power supply terminal A second transistor connected to the ground terminal through a fourth transistor, a gate connected to a drain of the first transistor, a source connected to a ground terminal, and a drain connected to a drain of the first transistor A third transistor connected to one of the first input terminals, a source connected to a ground terminal, a drain connected to a drain of the second transistor, and a gate connected to one of the first input terminals. And a fourth transistor connected to the other.

In this embodiment, the differential amplifier is located at the first output terminal located at the contact between the drain of the first transistor and the drain of the third transistor, and the contact between the drain of the second transistor and the drain of the fourth transistor. It further includes a second output terminal.

In this embodiment, the first cascode portion is connected to the source of the power supply voltage and the contact of the first transistor, the drain is connected to the source of the first control transistor, the gate of the second input terminal A fifth transistor connected to one, and a source is connected to a drain of the fifth transistor, a drain is connected to a contact between the first transistor and the third transistor, and a gate is connected to a control voltage input terminal to receive a control voltage It includes a first control transistor for controlling to vary the frequency by.

In this embodiment, the fifth transistor is turned off to turn off the operation of the first control transistor in the voltage level transition period by the line input voltage.

In this embodiment, the second cascode portion is connected to the source of the power supply voltage and the contact of the second transistor, the drain is connected to the source of the second control transistor, the gate is the other of the second input terminals A sixth transistor connected to one, a source connected to a drain of the sixth transistor, a drain connected to a contact between the second transistor and the fourth transistor, and a gate connected to a control voltage input terminal to receive a control voltage It includes a second control transistor for controlling to vary the frequency by.

In this embodiment, the sixth transistor is turned off to turn off the operation of the second control transistor in the voltage level transition period by the line input voltage.

In the present invention, a method of improving phase noise of a voltage controlled oscillator corresponding to each of a plurality of stages and including delay cells configured in a ring form is different from each of at least two delay cells in one of the delay cells. Receiving an output, and removing a noise current generated in a control transistor for frequency variation in a period in which an output voltage level is switched by using some of the received differential outputs, the two delay cells Each of the differential outputs has a different phase from each other.

In this embodiment, removing the noise current includes turning off the operation of the control transistor using some of the received differential outputs in the output level transition period.

In this embodiment, the step of receiving the differential output is the first differential from the delay cell of the n-2 stage if the one delay cell is a delay cell of the n (n is an integer greater than 1) stage. And receiving second differential outputs having a phase different from that of the outputs, and receiving the first differential outputs from the delay cell of the n-th stage.

In this embodiment, some of the received differential outputs are the second differential outputs.

In this embodiment, the step of receiving the differential output includes pre- inputting delay cell differential outputs of the last previous stage when the one delay cell is a delay cell of the first stage, and delay cell differential output of the last stage. And receiving the input.

In this embodiment, the step of receiving the differential output is the step of receiving the delay cell differential outputs of the last stage, if the one delay cell is a delay cell of the second stage, and the delay cell of the first stage Receiving differential outputs.

In this embodiment, some of the received differential outputs are the pre-input differential outputs.

According to the present invention, the phase noise can be improved by blocking the current flowing in the frequency variable transistor in the voltage level switching section included in the voltage controlled oscillator. In addition, the voltage controlled oscillator can improve the frequency variable performance by not reducing the operating range of the control voltage for frequency variable at a low supply voltage.

1 illustrates the structure of a voltage controlled oscillator according to an embodiment of the present invention;
2 is a diagram illustrating one of a plurality of stage delay cells included in the voltage controlled oscillator illustrated in FIG. 1;
3 is a diagram illustrating another delay cell structure for performance comparison with the delay cell shown in FIG. 2;
4 is a graph illustrating noise cancellation through performance comparison between delay cells illustrated in FIGS. 2 and 3;
5 is a performance comparison graph between delay cells shown in FIGS. 2 and 3;
FIG. 6 is a diagram illustrating another delay cell structure for performance comparison with the delay cell shown in FIG. 2; FIG.
FIG. 7 is a graph comparing performance between delay cells of FIGS. 2, 3, and 6.

Advantages and features of the present invention, and methods for achieving the same will be described with reference to embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. In addition, parts denoted by the same reference numerals throughout the specification represent the same components.

The expression "and / or" is used herein to mean including at least one of the components listed before and after. In addition, the expression “connected / combined” is used in the sense including including directly connected to or indirectly connected to other components. In this specification, the singular forms also include the plural unless specifically stated otherwise in the phrases. Also, as used herein, components, steps, operations, and elements referred to as "comprising" or "comprising" refer to the presence or addition of one or more other components, steps, operations, elements, and devices.

The present invention provides a voltage controlled oscillator with improved phase noise. The voltage controlled oscillator (VCO) of the present invention will be described as a ring voltage controlled oscillator (VCO) as an example. Further, the present invention can be applied to voltage controlled oscillators having a ring shape.

1 is a diagram illustrating a structure of a voltage controlled oscillator according to an embodiment of the present invention.

Referring to FIG. 1, the voltage controlled oscillator 10 includes a first delay cell 110, a second delay cell 120, a third delay cell 130, and a fourth delay including a plurality of stages. Cell 140.

The voltage controlled oscillator 10 is composed of four stages, for example. The first stage includes a first delay cell 110. The second stage includes a second delay cell 120. The third stage includes a third delay cell 130. The fourth stage includes a fourth delay cell 140.

In addition, the first delay cell 110 to the fourth delay cell 140 may be configured in a ring shape. Each of the first delay cell 110 to the fourth delay cell 140 may be referred to as an amplifier.

,

)을 차동 입력들(

,

)로 수신한다. 제 1 지연셀(110)은 제 3 지연셀(130)의 차동 출력들(

,

)을 차동 입력들(

,

)로 수신한다.The first delay cell 110 is the differential outputs of the fourth delay cell 140 (

,

) To the differential inputs

,

To receive. The first delay cell 110 is a differential output of the third delay cell 130 (

,

) To the differential inputs

,

To receive.

,

)을 차동 입력들(

,

)로 수신한다. 제 2 지연셀(120)은 제 4 지연셀(140)의 차동 출력들(

,

)을 차동 입력들(

,

)로 수신한다.The second delay cell 120 is the differential outputs of the first delay cell 110 (

,

) To the differential inputs

,

To receive. The second delay cell 120 is the differential outputs of the fourth delay cell 140 (

,

) To the differential inputs

,

To receive.

,

)을 차동 입력들(

,

)로 수신한다. 제 3 지연셀(130)은 제 1 지연셀(110)의 차동 출력들(

,

)을 차동 입력들(

,

)로 수신한다.The third delay cell 130 is the differential outputs of the second delay cell 120 (

,

) To the differential inputs

,

To receive. The third delay cell 130 is the differential outputs of the first delay cell 110 (

,

) To the differential inputs

,

To receive.

,

)을 차동 입력들(

,

)로 수신한다. 제 4 지연셀(140)은 제 2 지연셀(120)의 차동 출력들(

,

)을 차동 입력들(

,

)로 수신한다.In addition, the fourth delay cell 140 is the differential outputs of the third delay cell 130 (

,

) To the differential inputs

,

To receive. The fourth delay cell 140 is the differential outputs of the second delay cell 120 (

,

) To the differential inputs

,

To receive.

The positive polarity differential output from the first delay cell 110 to the fourth delay cell 140 is provided as a negative polarity input and the polarity differential output is provided as a positive polarity differential input. However, the differential outputs of the third delay cell 130 and the fourth delay cell 140 input to the first delay cell 110 and the second delay cell 120 are fed back to the differential inputs having the same polarity.

Delay cells 110, 120, 130, 140 of the present invention receive the differential outputs of at least two delay cells as differential inputs. In addition, since the delay cells 110, 120, 130, and 140 of the present invention are configured in a ring shape, the first delay cell 110 may be differential from the fourth delay cell 140 (the fourth stage (the last stage)). The outputs are provided as differential inputs, and the differential outputs of the third delay cell 130 of the third stage are provided as differential inputs.

That is, the nth delay cell of the nth stage receives as inputs the n-1 delay cell outputs of the n−1 th stage and the n-2 delay cell outputs of the n−2 th stage. However, as the delay cells are implemented in a ring shape, the delay cells of the first stage may be provided as inputs to the delay cell outputs of the last stage and the delay cell outputs of the last previous stage, as described. The delay cell of the second stage may receive inputs of delay cell outputs of the first stage and delay cell outputs of the last stage.

,

)에 대응)는 n-1 번째 스테이지의 지연셀 출력 단자들과 연결되고, 나머지 두 개의 입력 단자(차동 입력(

,

)에 대응)는 n-2 번째 스테이지의 지연셀 출력 단자들과 연결된다. 여기서, 입력 단자(

)와 입력 단자(

)는 위상 잡음 제거를 위해 서로 다른 위상을 갖고, 입력 단자(

)와 입력단자(

)는 위상 잡음 제거를 위해 서로 다른 위상을 갖는다.Each of the delay cells 110, 120, 130, and 140 has four input terminals and two output terminals. Two input terminals (differential inputs) of each of the delay cells 110, 120, 130, and 140.

,

) Is connected to the delay cell output terminals of the n-1th stage, and the other two input terminals (differential input (

,

) Is connected to the delay cell output terminals of the n-2th stage. Here, the input terminal (

) And input terminals (

) Have different phases for phase noise rejection and the input terminals (

) And input terminal (

) Have different phases for phase noise rejection.

To this end, for example, a phase difference of 45 degrees may be provided between voltages provided through the delay cell output terminal of the n-1 th stage and the delay cell output terminal of the n-2 th stage. The delay cell output terminal of the n-second stage has a phase that is 45 degrees faster than the delay cell output terminal of the n-1th stage. The phase differences between the voltages provided to the input terminals of each stage are shown in the figures at 0, 225, 90, 315, 180, 45, 270 and 135 degrees, respectively.

Each of the delay cells 110, 120, 130, and 140 amplifies and outputs a difference between voltages input through the delay cell output terminal of the n-th stage, and is input through the n-second stage delay cell output terminal. Voltages eliminate noise currents that occur as a result of voltage level shifts during frequency-variable operation.

Each of the delay cells 110, 120, 130, and 140 of the present invention uses the input voltage of which the phase advances in phase when the voltage level is switched using the delay cell output voltage of at least two stages having different phase differences. Turn off the variable frequency transistor operation that generates. Thus, the voltage controlled oscillator 10 of the present invention can eliminate the noise current generated by the variable frequency transistor.

Delay cells 110, 120, 130, and 140 use, for example, a line input voltage 45 degrees ahead of phase.

Hereinafter, the first delay cell 110 among the delay cells 110, 120, 130, and 140 of the voltage controlled oscillator 10 of the present invention will be described. The remaining delay cells 120, 130, and 140 may have a structure similar to that of the first delay cell 110.

FIG. 2 is a diagram illustrating one of delay cells of a plurality of stages included in the voltage controlled oscillator illustrated in FIG. 1.

,

,

,

,

,

), 제 1 제어 트랜지스터(

), 및 제 2 제어 트랜지스터(

)를 포함한다.Referring to FIG. 2, the first delay cell 110 includes first to sixth transistors (

,

,

,

,

,

), The first control transistor (

) And a second control transistor (

).

In addition, the first delay cell includes a differential amplifier 111, a first cascode unit 112, and a second cascode unit 113.

The first differential amplifier 111 includes input terminals and output terminals and amplifies a voltage difference between voltages input through the input terminals.

,

,

,

)를 포함한다.The differential amplifier 111 may include first to fourth transistors (

,

,

,

).

)와 제 3 트랜지스터(

)는 전원 단자(

)와 접지 단자(GND) 사이에 접속되고, 제 1 트랜지스터(

)와 제 3 트랜지스터(

) 사이의 노드에 출력 단자(

)가 위치한다. 제 2 트랜지스터(

)와 제 4 트랜지스터(

)는 전원 단자(

)와 접지 단자(GND) 사이에 접속되고, 제 2 트랜지스터(

)와 제 4 트랜지스터(

) 사이의 노드에 출력 단자(

)가 위치한다.First transistor (

) And the third transistor (

) Is the power terminal (

) Is connected between the ground terminal GND and the first transistor (

) And the third transistor (

At the node between the output terminals (

) Is located. Second transistor (

) And the fourth transistor (

) Is the power terminal (

) Is connected between the ground terminal GND and the second transistor (

) And the fourth transistor (

At the node between the output terminals (

) Is located.

), 제 3 트랜지스터(

))과 트랜지스터들(제 2 트랜지스터(

), 제 4 트랜지스터(

))은 전원 전압(

)과 접지 단자(GND)를 기준으로 병렬 연결된다.Transistors (first transistor (

), The third transistor (

) And transistors (second transistor (

), The fourth transistor (

)) Is the supply voltage (

) And ground terminal (GND) are connected in parallel.

)의 소스는 전원 단자(

)에 연결된다. 제 1 트랜지스터(

)의 드레인이 제 3 트랜지스터(

)를 통해 접지 단자(GND)에 연결된다. 제 1 트랜지스터(

)의 게이트는 제 2 트랜지스터(

)의 드레인에 연결된다.First transistor (

) Source is the power terminal (

) First transistor (

Drain of the third transistor (

Is connected to the ground terminal (GND). First transistor (

Gate of the second transistor (

Is connected to the drain.

)의 소스는 전원 단자(

)에 연결된다. 제 2 트랜지스터(

)의 드레인이 제 4 트랜지스터(

)를 통해 접지 단자(GND)에 연결된다. 제 2 트랜지스터(

)의 게이트는 제 1 트랜지스터(

)의 드레인에 연결된다.Second transistor (

) Source is the power terminal (

) Second transistor (

Drain of the fourth transistor (

Is connected to the ground terminal (GND). Second transistor (

) Gate of the first transistor (

Is connected to the drain.

)의 소스는 접지 단자(GND)에 연결된다. 제 3 트랜지스터(

)의 드레인은 제 1 트랜지스터(

)의 드레인에 연결된다. 제 3 트랜지스터(

)의 게이트는 n-1 번째 스테이지의 지연셀(일예로, 제 4 지연셀(140)) 출력 단자에 연결되고, 출력 단자의 차동 출력(

)을 차동 입력(

)으로 제공받는다.Third transistor (

) Is connected to the ground terminal (GND). Third transistor (

) Is the drain of the first transistor (

Is connected to the drain. Third transistor (

) Is connected to the output terminal of the delay cell (for example, the fourth delay cell 140) of the n-th stage, and the differential output (

) To the differential input (

) Is provided.

)의 소스는 접지 단자(GND)에 연결된다. 제 4 트랜지스터(

)의 드레인은 제 2 트랜지스터(

)의 드레인에 연결된다. 제 4 트랜지스터(

)의 게이트는 n-1 번째 스테이지의 지연셀(일예로, 제 4 지연셀(140)) 출력 단자에 연결되고, 출력 단자의 차동 출력(

)을 차동 입력(

)으로 제공받는다.Fourth transistor (

) Is connected to the ground terminal (GND). Fourth transistor (

) Drain of the second transistor (

Is connected to the drain. Fourth transistor (

) Is connected to the output terminal of the delay cell (for example, the fourth delay cell 140) of the n-th stage, and the differential output (

) To the differential input (

) Is provided.

)에 의해 발생되는 잡음 전류를 제거한다. 제 1 캐스코드부(112)는 잡음 전류 제거를 위해 차동 증폭부에 입력되는 차동 입력(

)에 앞서는 위상을 갖는 차동 입력(

)(일예로, 선 입력 전압)을 수신할 수 있다.The first cascode section 112 removes the noise current causing the phase noise. A first control transistor provided with a control voltage for varying the frequency of the first cascode unit 112 (

Remove the noise current caused by). The first cascode unit 112 is a differential input (input to the differential amplifier for noise current removal)

Differential input with phase prior to

(Eg, line input voltage).

)와 제 1 제어 트랜지스터(

)를 포함한다.The first cascode part 112 includes a fifth transistor (

) And the first control transistor (

).

)와 제 1 제어 트랜지스터(

)는 전원 단자(

)와 출력 단자(

) 사이에 제 1 트랜지스터(

)와 병렬로 연결된다. 즉, 제 5 트랜지스터(

)와 제 1 제어 트랜지스터(

)는 캐스코드(cascode)로 구성된다.Fifth transistor (

) And the first control transistor (

) Is the power terminal (

) And output terminals (

Between the first transistor (

) In parallel. That is, the fifth transistor (

) And the first control transistor (

) Consists of a cascode.

)의 소스는 제 1 트랜지스터(

)의 소스와 전원 단자(

) 간의 접점에 연결된다. 제 5 트랜지스터(

)의 드레인은 제 1 제어 트랜지스터(

)를 통해 제 1 트랜지스터(

)의 드레인과 출력 단자(

) 간의 접점에 연결된다. 제 5 트랜지스터(

)의 게이트는 n-2 번째 스테이지의 지연셀(일예로, 제 3 지연셀(130))의 출력 전압(

)을 입력 전압(

)으로 제공받는다.Fifth transistor (

Source of the first transistor (

Source and power terminals ()

) Is connected to the contact point. Fifth transistor (

) Drain of the first control transistor (

Through the first transistor (

) Drain and output terminals (

) Is connected to the contact point. Fifth transistor (

) Is the output voltage of the delay cell (for example, the third delay cell 130) of the n-2 th stage

) The input voltage (

) Is provided.

)의 소스는 제 5 트랜지스터(

)의 드레인에 연결된다. 제 1 제어 트랜지스터(

)의 드레인은 제 1 트랜지스터(

)의 드레인과 출력 단자(

) 간의 접점에 연결된다. 제 1 제어 트랜지스터(

)의 게이트는 제어 전압(

)을 입력받는다.First control transistor (

) Source of the fifth transistor (

Is connected to the drain. First control transistor (

) Is the drain of the first transistor (

) Drain and output terminals (

) Is connected to the contact point. First control transistor (

) Is the control voltage (

) Is inputted.

)에 의해 발생되는 잡음 전류를 제거한다. 제 2 캐스코드부(113)는 잡음 전류 제거를 위해 차동 증폭부에 입력되는 차동 입력(

)에 앞서는 위상을 갖는 차동 입력(

)(일예로, 선 입력 전압)를 수신할 수 있다. 제 2 캐스코드부(113)는 전원 단자(

)와 접지 단자(GND)를 기준으로 제 1 캐스코드부의 반대편에 위치할 수 있다.In addition, the second cascode unit 113 removes the noise current causing the phase noise. A second control transistor provided with a control voltage for changing the frequency of the second cascode unit 113 (

Remove the noise current caused by). The second cascode unit 113 is a differential input (input to the differential amplifier for noise current removal)

Differential input with phase prior to

(Eg, line input voltage). The second cascode unit 113 is a power supply terminal (

) And the ground terminal GND may be opposite to the first cascode part.

)와 제 2 제어 트랜지스터(

)를 포함한다. The second cascode part 113 includes the sixth transistor (

) And the second control transistor (

).

)와 제 2 제어 트랜지스터(

)는 전원 단자(

)와 출력 단자(

) 사이에 제 2 트랜지스터(

)와 병렬로 연결된다. 즉, 제 6 트랜지스터(

)와 제 2 제어 트랜지스터(

)는 캐스코드(cascode)로 구성된다.Sixth transistor (

) And the second control transistor (

) Is the power terminal (

) And output terminals (

Between the second transistor (

) In parallel. That is, the sixth transistor (

) And the second control transistor (

) Consists of a cascode.

)의 소스는 제 2 트랜지스터(

)의 소스와 전원 단자(

) 간의 접점에 연결된다. 제 6 트랜지스터(

)의 드레인은 제 2 제어 트랜지스터(

)를 통해 제 2 트랜지스터(

)의 드레인과 출력 단자(

) 간의 접점에 연결된다. 제 6 트랜지스터(

)의 게이트는 n-2 번째 스테이지의 지연셀(일예로, 제 3 지연셀(130))의 출력 전압(

)을 입력 전압(

)으로 제공받는다.Sixth transistor (

Source of the second transistor (

Source and power terminals ()

) Is connected to the contact point. Sixth transistor (

) Drain of the second control transistor (

Through the second transistor (

) Drain and output terminals (

) Is connected to the contact point. Sixth transistor (

) Is the output voltage of the delay cell (for example, the third delay cell 130) of the n-2 th stage

) The input voltage (

) Is provided.

)의 소스는 제 6 트랜지스터(

)의 드레인에 연결된다. 제 2 제어 트랜지스터(

)의 드레인은 제 2 트랜지스터(

)의 드레인과 출력 단자(

) 간의 접점에 연결된다. 제 2 제어 트랜지스터(

)의 게이트는 제어 전압(

)을 입력받는다.Second control transistor (

) Source of the sixth transistor (

Is connected to the drain. Second control transistor (

) Drain of the second transistor (

) Drain and output terminals (

) Is connected to the contact point. Second control transistor (

) Is the control voltage (

) Is inputted.

), 제 2 트랜지스터(

), 제 5 트랜지스터(

), 제 6 트랜지스터(

), 제 1 제어 트랜지스터(

), 및 제 2 제어 트랜지스터(

) 각각은 피모스(PMOS) 트랜지스터일 수 있다. 또한, 제 3 트랜지스터(

)와 제 4 PMOS 트랜지스터(

)는 엔모스(NMOS) 트랜지스터일 수 있다.For example, the first transistor (

), The second transistor (

), The fifth transistor (

), The sixth transistor (

), The first control transistor (

) And a second control transistor (

Each may be a PMOS transistor. In addition, the third transistor (

) And the fourth PMOS transistor (

) May be an NMOS transistor.

)와 제 2 트랜지스터(

)는 래치 구조를 가질 수 있다. 제 3 트랜지스터(

)와 제 4 트랜지스터(

) 각각은 입력 트랜지스터이다. 제 1 제어 트랜지스터(

)와 제 2 제어 트랜지스터(

)는 주파수 가변을 위한 주파수 가변 트랜지스터들이다.Meanwhile, the first transistor (

) And the second transistor (

) May have a latch structure. Third transistor (

) And the fourth transistor (

Are each input transistors. First control transistor (

) And the second control transistor (

) Are frequency variable transistors for variable frequency.

)와 제 6 트랜지스터(

)는 게이트를 통해 위상이 앞선 전압을 선 입력받는다. 따라서, 제 5 트랜지스터(

)와 제 6 트랜지스터(

)는 선 입력 트랜지스터들이다.Fifth transistor (

) And the sixth transistor (

) Is pre-populated with a voltage through the gate. Thus, the fifth transistor (

) And the sixth transistor (

Are the line input transistors.

Next, an operation of removing phase noise in the first delay cell 110 will be described.

)에 흐르는 전류(

)과 제 2 제어 트랜지스터(

)에 흐르는 전류(

)는 위상 잡음을 발생시키는 원인이 된다. 전류(

,

)는 입력 전압들(

,

)의 전압 레벨이 하이(High)에서 로우(Low)로 전환되거나, 로우(Low)에서 하이(High)로 전환되는 전압 레벨 전환 구간에서 존재한다.In the first delay cell 110, the first control transistor (

Current in

) And the second control transistor (

Current in

) Causes phase noise. electric current(

,

) Is the input voltage (

,

) Is present in the voltage level switching period in which the voltage level of the high voltage is switched from high to low or from low to high.

)와 제 2 전류(

)가 발생되지 않도록 제어해야 한다. 이를 위해, 제 5 트랜지스터(

)와 제 6 트랜지스터(

)는 제 3 트랜지스터(

)와 제 4 트랜지스터(

)의 입력 전압(

,

)들 보다 위상이 앞선 선 입력 전압(

,

)을 인가받는다.Therefore, to improve phase noise The delay cell 110 is a first current in the voltage level switching period (

) And the second current (

) Should be controlled so that it does not occur. For this purpose, the fifth transistor (

) And the sixth transistor (

) Is the third transistor (

) And the fourth transistor (

Input voltage of

,

Input voltage ahead of phases

,

) Is authorized.

)와 제 6 트랜지스터(

)는 제 3 트랜지스터(

)와 제 4 트랜지스터(

)의 입력 전압들(

,

) 보다 위상이 45도 빠른(앞선) 전압을 입력받는다. 제 1 스테이지의 제 1 지연셀(110)에서 제 5 트랜지스터(

)와 제 3 트랜지스터(

)의 입력 전압들(

(-45도(315도)),

(0도)) 간의 위상을 비교(도 1 참조)하면, 입력 전압(

)의 위상이 입력 전압(

)의 위상보다 45도 더 빠른 것을 확인할 수 있다. 제 6 트랜지스터(

)와 제 4 트랜지스터(

)에서도 입력 전압(

)의 위상(135도)이 입력 전압(

)의 위상(180)보다 45도만큼 더 빠른 것을 확인(도 1 참조)할 수 있다.For example, the fifth transistor (

) And the sixth transistor (

) Is the third transistor (

) And the fourth transistor (

Input voltages of

,

The input voltage is 45 degrees out of phase. The fifth transistor (in the first delay cell 110 of the first stage)

) And the third transistor (

Input voltages of

(-45 degrees (315 degrees)),

Comparing the phases between (0 degrees) (see FIG. 1), the input voltage (

) Phase is equal to the input voltage (

We can see that the phase is 45 degrees faster than). Sixth transistor (

) And the fourth transistor (

At the input voltage (

) Phase (135 degrees)

It can be seen that the phase is faster by 45 degrees than the phase 180 (see FIG. 1).

,

)에 의해 전압 레벨 전환 구간에서 제 5 트랜지스터(

)와 제 6 트랜지스터(

)는 오프 동작한다. 제 5 트랜지스터(

)의 오프 동작에 의해 제 1 제어 트랜지스터(

)는 오프 동작하고, 제 6 트랜지스터(

)의 오프 동작에 의해 제 2 제어 트랜지스터(

)는 오프 동작한다.Line input voltage (

,

In the voltage level switching period by the fifth transistor (

) And the sixth transistor (

) Is off. Fifth transistor (

By the off operation of the first control transistor (

) Is off and the sixth transistor (

By the off operation of the second control transistor (

) Is off.

)와 제 6 트랜지스터(

)로의 선 입력 전압의 제공에 의해 제 1 제어 트랜지스터(

)와 제 2 제어 트랜지스터(

)를 오프시켜, 전류(

,

)가 흐르지 않도록 제어할 수 있다.According to the present invention, the fifth transistor (

) And the sixth transistor (

By providing the line input voltage to the first control transistor (

) And the second control transistor (

) Off, the current (

,

) Can be controlled so as not to flow.

,

)의 전압 레벨이 하이(High)에서 로우(Low)로 전환되거나, 로우(Low)에서 하이(High)로 전환되는 전압 레벨 전환 구간에서 주파수 가변 트랜지스터들(

,

전압이 흐르지 않도록 제어할 수 있다.In particular, the input voltages (

,

In the voltage level switching period in which the voltage level of the high / low transitions from high to low or from low to high,

,

The voltage can be controlled so as not to flow.

,

)과 위상차를 갖는 전압들(

,

)를 선 입력 트랜지스터(

,

)로 제공함으로서 주파수 가변 트랜지스터들에 의해 발생되는 위상 잡음을 제거할 수 있다.Therefore, the first delay cell 110 of the present invention is the voltage (

,

) And the phase difference voltages (

,

Wire input transistor (

,

Phase noise caused by the frequency variable transistors can be eliminated.

)와 제 4 트랜지스터(

)의 입력 전압(

,

)들 보다 위상이 45도 빠른(앞선) 전압을 제 5 트랜지스터(

)와 제 6 트랜지스터(

)로 인가함으로서 고속 동작을 가능하게 할 수 있다.In addition, the first delay cell 110 may include a third transistor (

) And the fourth transistor (

Input voltage of

,

Voltages that are 45 degrees out of phase with the fifth transistor (

) And the sixth transistor (

), High speed operation can be enabled.

Not only the first stage (including the first delay cell 110) but also the remaining stages (including the remaining delay cells 120, 130, and 140) may have a structure of pre-inputting a voltage in advance of phase.

FIG. 3 is a diagram illustrating another delay cell structure for performance comparison with the delay cell shown in FIG. 2.

,

,

,

), 제 3 제어 트랜지스터(

), 및 제 4 제어 트랜지스터(

)를 포함한다.Referring to FIG. 3, the delay cell 200 includes seventh to tenth transistors (

,

,

,

), The third control transistor (

), And a fourth control transistor (

).

) 내지 제 8 트랜지스터(

)는 래치 구조를 갖는다. 제 9 트랜지스터()와 제 10 트랜지스터(

)는 입력 트랜지스터이다. 제 3 제어 트랜지스터(

)와 제 4 제어 트랜지스터(

)는 주파수 가변 트랜지스터이다.7th transistor (

) To eighth transistors (

) Has a latch structure. Ninth transistor ( ) And the tenth transistor (

Is an input transistor. Third control transistor (

) And the fourth control transistor (

) Is a frequency variable transistor.

)와 제 9 트랜지스터(

)는 전원 단자(

)와 접지 단자(GND) 사이에 접속되고, 제 7 트랜지스터(

)와 제 9 트랜지스터(

) 사이의 노드에 출력 단자(

)가 위치한다. 제 8 트랜지스터(

)와 제 10 트랜지스터(

) 전원 단자(

)와 접지 단자(GND) 사이에 접속되고, 제 8 트랜지스터(

)와 제 10 트랜지스터(

) 사이의 노드에 출력 단자(

)가 위치한다.7th transistor (

) And the ninth transistor (

) Is the power terminal (

) Is connected between the ground terminal GND and the seventh transistor (

) And the ninth transistor (

At the node between the output terminals (

) Is located. Eighth transistor (

) And the tenth transistor (

Power terminal

) Is connected between the ground terminal GND and the eighth transistor (

) And the tenth transistor (

At the node between the output terminals (

) Is located.

), 제 9 트랜지스터(

))과 트랜지스터들(제 8 트랜지스터(

), 제 10 트랜지스터(

))은 전원 단자(

)와 접지 단자(GND)를 기준으로 병렬 연결된다.Transistors (seventh transistor)

), The ninth transistor (

) And transistors (the eighth transistor (

), The tenth transistor (

)) Is the power terminal (

) And ground terminal (GND) are connected in parallel.

)는 전원 단자(

)와 출력 단자(

) 사이에 제 7 트랜지스터(

)와 병렬로 연결된다. 제 4 제어 트랜지스터(

)는 전원 단자(

)와 출력 단자(

) 사이에 제 8 트랜지스터(

)와 병렬로 연결된다.Third control transistor (

) Is the power terminal (

) And output terminals (

Between the seventh transistors (

) In parallel. Fourth control transistor (

) Is the power terminal (

) And output terminals (

Between the eighth transistor (

) In parallel.

,

,

,

), 제 3 제어 트랜지스터(

), 및 제 4 제어 트랜지스터(

)의 상세 구성은 도 2의 지연셀 구조를 참조하기로 한다.Seventh to tenth transistors (

,

,

,

), The third control transistor (

), And a fourth control transistor (

) Will be referred to the delay cell structure of FIG. 2.

), 제 2 트랜지스터(

), 제 5 트랜지스터(

), 제 6 트랜지스터(

), 제 1 제어 트랜지스터(

), 및 제 2 제어 트랜지스터(

) 각각은 피모스(PMOS) 트랜지스터일 수 있다. 또한, 제 3 트랜지스터(

)와 제 4 PMOS 트랜지스터(

)는 엔모스(NMOS) 트랜지스터일 수 있다.For example, the first transistor (

), The second transistor (

), The fifth transistor (

), The sixth transistor (

), The first control transistor (

) And a second control transistor (

Each may be a PMOS transistor. In addition, the third transistor (

) And the fourth PMOS transistor (

) May be an NMOS transistor.

,

)에서 발생되는 전류들의 흐름을 제어할 수 없다.On the other hand, the delay cell 200 may be included in the n-th stage, and may be included in one of the stages of the ring voltage controlled oscillator provided with the output voltages of the previous stage delay cell output terminals. That is, the delay cell 200 uses output voltages of the n−1 th stage delay cell output terminals. The delay cell 200 does not use output voltages of the delay cell output terminals of the n-th stage. Therefore, the delay cell 200 is a frequency variable transistor (

,

It is not possible to control the flow of currents generated at

,

)에 발생되는 전류들(

,

)로 인해 위상 잡음이 발생될 수 있다.In the voltage level transition period, the delay cell 200 includes frequency variable transistors (

,

Currents generated by

,

Phase noise may occur.

FIG. 4 is a graph illustrating noise cancellation through performance comparison between delay cells illustrated in FIGS. 2 and 3.

Referring to FIG. 4, in (a) and (b), the horizontal axis represents time and the vertical axis represents the magnitude of voltage. In (c), the horizontal axis represents time and the vertical axis represents the magnitude of the noise current.

)와 지연셀(200)의 입력 전압(

)이 나타나있다. (b)에서, 입력 전압(

)과 입력 전압(

)에 대응되는 출력 전압(

)이 나타나 있다. 또한, 제 1 지연셀(110)의 선 입력 트랜지스터인 제 5 트랜지스터(

)로 제공되는 선 입력 전압(

)가 나타나있다.In (a), the input voltage of the first delay cell 110 (

) And the input voltage of the delay cell 200 (

) Is shown. (b), the input voltage (

) And input voltage (

Corresponding to the output voltage (

) Is shown. In addition, the fifth transistor that is a line input transistor of the first delay cell 110 (

Line input voltage in

) Is shown.

,

), 출력 전압(

)에 따른 주파수 가변 트랜지스터에 흐르는 전류(

)의 변화가 나타나있다.In (c), the input voltage shown in (a), (b) (

,

), Output voltage (

Current flowing through the frequency variable transistor

) Is shown.

또는

)을 사용하지 않는다.Delay cell 200 is a line input voltage (

or

Do not use).

)이 전원 전압(

)의 크기를 갖는 경우, 주파수 가변 트랜지스터(

)에 전류가 흐르지 않는다. 하지만, 출력 전압(

)이 전원 전압(

)보다 작은 값을 갖는 경우, 주파수 가변 트랜지스터(

)에 전류가 흐르게 되어 잡음 전류(

)가 발생된다.Delay cell 200 is the output voltage (

) Is the power supply voltage (

Has a size of the frequency variable transistor (

), No current flows. However, the output voltage (

) Is the power supply voltage (

If the value is smaller than), the frequency variable transistor (

Current flows through the

) Is generated.

또는

)을 사용한다. 일예로, 제 1 지연셀(110)의 선 입력 전압(

)에 대응되는 구성을 중심으로 설명하기로 한다. (b)를 살펴보면, 제 1 지연셀(110)의 출력 전압(

)은 선 입력 전압(

)보다 270도만큼 위상이 빠르다.On the other hand, the first delay cell 110 is a line input voltage (

or

). For example, the line input voltage of the first delay cell 110 (

The configuration corresponding to) will be described below. Referring to (b), the output voltage of the first delay cell 110 (

) Is the line input voltage (

Phase is 270 degrees faster than

), 출력 전압(

), 및 선 입력 전압(

)는 모두 0V와 전원 전압(

) 사이에서 스윙한다. (b)에서 '

'는 선 입력 트랜지스터(

)가 동작할 수 있는 한계 전압을 나타낸다. '

'보다 높은 전압이 선 입력 트랜지스터(

)의 게이트로 제공된다. 이때, 선 입력 트랜지스터(

)의 게이트-소스 간 전압(VGS)은 '

'보다 작아지므로 선 입력 트랜지스터(

)는 오프 동작한다.Where the input voltage (

), Output voltage (

), And the line input voltage (

) Are both 0V and the supply voltage (

Swing between). in (b)

Is a line input transistor (

) Represents the limit voltage at which it can operate. '

Voltage higher than the line input transistor (

Is provided as a gate. At this time, the line input transistor (

), The gate-to-source voltage (VGS) is

Less than ', so the line input transistor (

) Is off.

)의 게이트에 '

'보다 높은 전압이 인가되면, 선 입력 트랜지스터(

)에 의해 주파수 가변 트랜지스터들(

)이 동작하지 않는다. 주파수 가변 트랜지스터들(

)가 동작하지 않으면, 주파수 가변 트랜지스터(

)에 전류(

)가 흐르지 않는다.Line input transistor (

) At the gate of '

When a higher voltage is applied, the line input transistor (

Frequency variable transistors

Does not work. Frequency-variable transistors (

) Does not work, the frequency variable transistor (

Current ()

) Does not flow.

)의 전압 레벨이 변화되는 동안 주파수 가변 트랜지스터(

)에 흐르는 전류(

)는 제거된다. 한 주기 동안 두 개의 전압 레벨 변환 구간(하이(High)에서 로우(Low)로, 로우(Low)에서 하이(High)로)이 존재한다고 가정하면, 도 3의 지연셀 구조에 비해 잡음 전류가 감소하는 것을 (c)에서 확인할 수 있다.Therefore, the output voltage (from high to low)

While the voltage level of the

Current in

) Is removed. Assuming that there are two voltage level transition periods (High to Low and Low to High) during one period, the noise current is reduced compared to the delay cell structure of FIG. It can be confirmed in (c).

In FIG. 3C, the dotted line indicates the noise current when the delay cell 200 of FIG. 3 is used, and the solid line indicates the noise current when the first delay cell 110 of FIG. 2 is used. Therefore, the first delay cell 110 may confirm that the noise current is reduced compared to the delay cell 200.

)에 흐르는 전류(

)를 일예로 설명하였다. 하지만, 선 입력 트랜지스터(

)로 입력되는 선 입력 전압(

)에 의해 주파수 가변 트랜지스터(

)에 의해 발생되는 잡음 전류를 도 4와 유사하게 감소시킬 수 있다.In Figure 4 the frequency variable transistor (

Current in

) As an example. However, the line input transistor (

Line input voltage ()

Frequency variable transistor

Can be reduced similarly to FIG. 4.

In addition, since the noise current may be removed in the remaining delay cells 120, 130, and 140 of FIG. 1, the phase noise performance of the voltage controlled oscillator 10 may be improved.

FIG. 5 is a performance comparison graph between delay cells illustrated in FIGS. 2 and 3.

,

)를 제외한 나머지 소자들은 유사한 성능을 갖는다. 또한, 지연셀(110)과 지연셀(200)에 동일한 동작 조건(일예로, 공급 전압, 주파수 가변 범위, 전력 소모)을 갖는 경우, 위상 잡음을 도시하였다. 일예로, 발진 주파수는 400MHz라 한다.Referring to FIG. 5, line input transistors between the first delay cell 110 of FIG. 2 and the delay cell 200 of FIG.

,

Except for), the other devices have similar performance. In addition, when the delay cell 110 and the delay cell 200 have the same operating conditions (eg, supply voltage, frequency variable range, power consumption), phase noise is illustrated. In one example, the oscillation frequency is 400MHz.

The horizontal axis of the graph represents the offset frequency (Hz) and the vertical axis represents the phase noise (dBc / Hz).

The solid line represents the phase noise of the first delay cell 110 of FIG. 2, and the dotted line represents the phase noise of the delay cell 200 of FIG. 3.

The phase noise of the delay cell 200 of FIG. 3 at a 1 MHz offset frequency is -100.9 dBc / Hz. The phase noise of the first delay cell 110 of FIG. 2 at a 1 MHz offset frequency is -107.4 dBc / Hz. Accordingly, the first delay cell 110 of FIG. 2 may confirm an improvement of 6.5 dBc compared to the delay cell 200 of FIG. 3.

As described above, the first delay cell 110 proposed in the present invention may improve the phase noise characteristic by removing the noise current in the voltage level transition period.

FIG. 6 is a diagram illustrating another delay cell structure for performance comparison with the delay cell shown in FIG. 2.

,

,

,

,

,

), 제 5 제어 트랜지스터(

), 및 제 6 제어 트랜지스터(

)을 포함한다.Referring to FIG. 6, the delay cell 300 includes eleventh through sixteenth transistors (

,

,

,

,

,

), The fifth control transistor (

), And the sixth control transistor (

).

)와 제 13 트랜지스터(

)는 전원 단자(

)와 접지 단자(GND) 사이에 접속되고, 제 11 트랜지스터(

)와 제 13 트랜지스터(

) 사이의 노드에 출력 단자(

)가 위치한다. 제 12 트랜지스터(

)와 제 14 트랜지스터(

)는 전원 단자(

)와 접지 단자(GND) 사이에 접속되고, 제 12 트랜지스터(

)와 제 14 트랜지스터(

) 사이의 노드에 출력 단자(

)가 위치한다.Eleventh transistor (

) And the thirteenth transistor (

) Is the power terminal (

) Is connected between the ground terminal GND and the eleventh transistor (

) And the thirteenth transistor (

At the node between the output terminals (

) Is located. 12th transistor (

) And the fourteenth transistor (

) Is the power terminal (

) Is connected between the ground terminal GND and the twelfth transistor (

) And the fourteenth transistor (

At the node between the output terminals (

) Is located.

), 제 13 트랜지스터(

))과 트랜지스터들(제 12 트랜지스터(

), 제 14 트랜지스터(

))은 전원 전압(

)과 접지 단자(GND)를 기준으로 병렬 연결된다.Transistors (the eleventh transistor)

), The thirteenth transistor (

) And transistors (the twelfth transistor (

), The fourteenth transistor (

)) Is the supply voltage (

) And ground terminal (GND) are connected in parallel.

)의 소스는 전원 단자(

)에 연결된다. 제 11 트랜지스터(

)의 드레인이 제 13 트랜지스터(

)를 통해 접지 단자(GND)에 연결된다. 제 11 트랜지스터(

)의 게이트는 제 6 제어 트랜지스터(

)의 드레인에 연결된다.Eleventh transistor (

) Source is the power terminal (

) Eleventh transistor (

Drain of the thirteenth transistor (

Is connected to the ground terminal (GND). Eleventh transistor (

) Gate of the sixth control transistor (

Is connected to the drain.

)의 소스는 전원 단자(

)에 연결된다. 제 12 트랜지스터(

)의 드레인이 제 14 트랜지스터(

)를 통해 접지 단자(GND)에 연결된다. 제 12 트랜지스터(

)의 게이트는 제 5 제어 트랜지스터(

)의 드레인에 연결된다.12th transistor (

) Source is the power terminal (

) 12th transistor (

Drain of the fourteenth transistor (

Is connected to the ground terminal (GND). 12th transistor (

) Gate of the fifth control transistor (

Is connected to the drain.

)의 소스는 접지 단자(GND)에 연결된다. 제 13 트랜지스터(

)의 드레인은 제 11 트랜지스터(

)의 드레인에 연결된다. 제 13 트랜지스터(

)의 게이트는 n-1 번째 스테이지의 지연셀 출력 단자에 연결되고, 출력 단자의 차동 출력(

)을 차동 입력(

)으로 제공받는다.Thirteenth transistor (

) Is connected to the ground terminal (GND). Thirteenth transistor (

) Drain is the eleventh transistor (

Is connected to the drain. Thirteenth transistor (

) Is connected to the delay cell output terminal of the n-1th stage, and the differential output (

) To the differential input (

) Is provided.

)의 소스는 접지 단자(GND)에 연결된다. 제 14 트랜지스터(

)의 드레인은 제 12 트랜지스터(

)의 드레인에 연결된다. 제 14 트랜지스터(

)의 게이트는 n-1 번째 스테이지의 지연셀 출력 단자에 연결되고, 출력 단자의 차동 출력(

)을 차동 입력(

)으로 제공받는다.Fourteenth transistor

) Is connected to the ground terminal (GND). Fourteenth transistor

) Is the drain of the twelfth transistor (

Is connected to the drain. Fourteenth transistor

) Is connected to the delay cell output terminal of the n-1th stage, and the differential output (

) To the differential input (

) Is provided.

)의 소스는 출력 단자(

)에 연결된다. 제 5 제어 트랜지스터(

)의 드레인은 제 12 트랜지스터(

)의 게이트에 연결된다. 제 5 제어 트랜지스터(

)의 게이트는 제어 전압(

)을 입력받는다.Fifth control transistor (

) Is the output terminal (

) Fifth control transistor (

) Is the drain of the twelfth transistor (

Is connected to the gate. Fifth control transistor (

) Is the control voltage (

) Is inputted.

)의 소스는 출력 단자(

)에 연결된다. 제 6 제어 트랜지스터(

)의 드레인은 제 11 트랜지스터(

)의 게이트에 연결된다. 제 6 제어 트랜지스터(

)의 게이트는 제어 전압(

)을 입력받는다.Sixth control transistor (

) Is the output terminal (

) Sixth control transistor (

) Drain is the eleventh transistor (

Is connected to the gate. Sixth control transistor (

) Is the control voltage (

) Is inputted.

)는 전원 단자(

)와 출력 단자(

) 사이에 제 11 트랜지스터(

)와 병렬로 연결된다. 제 15 트랜지스터(

)의 소스는 제 11 트랜지스터(

)의 소스와 전원 단자(

) 간의 접점에 연결된다. 제 15 트랜지스터(

)의 드레인은 제 11 트랜지스터(

)의 드레인과 출력 단자(

) 간의 접점에 연결된다. 제 15 트랜지스터(

)의 게이트는 n-2 번째 스테이지의 지연셀의 출력 전압(

)을 입력 전압(

)으로 제공받는다.15th transistor

) Is the power terminal (

) And output terminals (

Between the eleventh transistor (

) In parallel. 15th transistor

) Source of the eleventh transistor (

Source and power terminals ()

) Is connected to the contact point. 15th transistor

) Drain is the eleventh transistor (

) Drain and output terminals (

) Is connected to the contact point. 15th transistor

) Is the output voltage of the delay cell of the n-th stage

) The input voltage (

) Is provided.

)는 전원 단자(

)와 출력 단자(

) 사이에 제 12 트랜지스터(

)와 병렬로 연결된다. 제 16 트랜지스터(

)의 소스는 제 12 트랜지스터(

)의 소스와 전원 단자(

) 간의 접점에 연결된다. 제 16 트랜지스터(

)의 드레인은 제 12 트랜지스터(

)의 드레인과 출력 단자(

) 간의 접점에 연결된다. 제 16 트랜지스터(

)의 게이트는 n-2 번째 스테이지의 지연셀의 출력 전압(

)을 입력 전압(

)으로 제공받는다.16th transistor

) Is the power terminal (

) And output terminals (

Between the 12th transistor (

) In parallel. 16th transistor

Source of the twelfth transistor (

Source and power terminals ()

) Is connected to the contact point. 16th transistor

) Is the drain of the twelfth transistor (

) Drain and output terminals (

) Is connected to the contact point. 16th transistor

) Is the output voltage of the delay cell of the n-th stage

) The input voltage (

) Is provided.

), 제 12 트랜지스터(

), 제 15 트랜지스터(

), 및 제 16 트랜지스터(

)는 PMOS 트랜지스터일 수 있다. 제 13 트랜지스터(

), 제 14 트랜지스터(

), 제 5 제어 트랜지스터(

), 및 제 6 제어 트랜지스터(

)는 NMOS 트랜지스터일 수 있다.Eleventh transistor (

), The twelfth transistor (

), The fifteenth transistor (

), And the sixteenth transistor (

) May be a PMOS transistor. Thirteenth transistor (

), The fourteenth transistor (

), The fifth control transistor (

), And the sixth control transistor (

) May be an NMOS transistor.

)와 제 12 트랜지스터(

)는 래치 구조를 갖는다. 이때, 제 5 제어 트랜지스터(

)와 제 6 제어 트랜지스터(

)는 지연 셀의 래치 강도를 조절한다.Here, the eleventh transistor (

) And the 12th transistor (

) Has a latch structure. At this time, the fifth control transistor (

) And the sixth control transistor (

) Adjusts the latch strength of the delay cell.

,

)는 0V와 전원 전압(

) 사이를 스윙(swing)한다. 제 5 제어 트랜지스터(

)는 제 11 트랜지스터(

)의 게이트로 출력 전압(

)을 제공하는 스위치 역할을 한다. 제 6 제어 트랜지스터(

)는 제 12 트랜지스터(

)의 게이트로 출력 전압(

또는

)을 제공하는 스위치 역할을 한다.Output voltage (

,

) Is 0V and the supply voltage (

Swing between). Fifth control transistor (

) Is the eleventh transistor (

To the gate of the output voltage (

It acts as a switch that provides Sixth control transistor (

) Is the twelfth transistor (

To the gate of the output voltage (

or

It acts as a switch that provides

또는

)이 0V일 때, 제어 전압(

)이 임계 전압 이상(

>

)이면 제 5 제어 트랜지스터(

) 또는 제 6 제어 트랜지스터(

)은 온 동작한다. 제 5 제어 트랜지스터(

) 또는 제 6 제어 트랜지스터(

)의 동작에 의해 0V의 제어 전압을 제 11 트랜지스터() 또는 제 12 트랜지스터(

) 각각의 게이트로 제공한다.For example, the output voltage (

or

) Is 0V, the control voltage (

) Is above the threshold voltage (

>

), The fifth control transistor (

) Or the sixth control transistor (

) Is on. Fifth control transistor (

) Or the sixth control transistor (

The control voltage of 0 V is changed by the operation of the eleventh transistor ( ) Or the twelfth transistor (

) To each gate.

또는

)이

일 때, 제어 전압(

)이 임계 전압 이상(

>

)이면 제 5 제어 트랜지스터(

) 또는 제 6 제어 트랜지스터(

)는 온 동작한다. 제 5 제어 트랜지스터(

) 또는 제 6 제어 트랜지스터(

)의 동작에 의해 제 11 트랜지스터(

)와 제 12 트랜지스터(

) 각각의 게이트로 전원 전압(

)을 제공할 수 없다. 이때, 제 5 제어 트랜지스터(

)와 제 6 제어 트랜지스터(

)는 제 11 트랜지스터(

)와 제 12 트랜지스터(

) 각각의 게이트로 음의 임계 전압 값(-threshod voltage(

-

))까지 제공할 수 있다.However, the output voltage (

or

)this

, The control voltage (

) Is above the threshold voltage (

>

), The fifth control transistor (

) Or the sixth control transistor (

) Is on. Fifth control transistor (

) Or the sixth control transistor (

Operation of the eleventh transistor (

) And the 12th transistor (

Each gate has a supply voltage (

) Cannot be provided. At this time, the fifth control transistor (

) And the sixth control transistor (

) Is the eleventh transistor (

) And the 12th transistor (

Each gate has a negative threshold voltage (-threshod voltage)

-

Up to)).

이고, 제어 전압이 낮으면(일예로,

에 가까운 값을 가지면), 제 11트랜지스터(

)와 제 12 트랜지스터(

)의 게이트에 0V의 전압이 인가된다. 따라서, 지연셀(300)의 동작 성능이 저하되고, 지연셀(300)을 사용하여 구성된 전압 제어 발진기는 성능이 감소한다. 그러므로

보다는 큰 제어 전압이 요구되기 때문에 지연셀(300)은 낮은 공급 전압에서 주파수 가변을 위한 제어 전압의 동작 범위가 감소한다.Therefore, when the supply voltage decreases, the control voltage also decreases at the same time. In addition, the output voltage

If the control voltage is low (e.g.,

If it has a value close to), the 11th transistor (

) And the 12th transistor (

A voltage of 0 V is applied to the gate. Therefore, the operation performance of the delay cell 300 is degraded, and the voltage controlled oscillator configured using the delay cell 300 decreases in performance. therefore

Since a larger control voltage is required, the delay cell 300 reduces the operating range of the control voltage for frequency variation at a low supply voltage.

Therefore, since the control voltage range available at the low supply voltage is reduced, the delay cell 300 may cause performance degradation due to frequency variation.

FIG. 7 is a graph comparing performance between delay cells of FIGS. 2, 3, and 6.

Referring to FIG. 7, the horizontal axis represents the control voltage (mV) and the vertical axis represents the frequency (MHz).

Each of the delay cells 110, 200, and 300 of FIGS. 2, 3, and 6 may have the same device and the same operating condition (eg, same supply voltage and same power consumption). In this case, the frequency variable performance is shown in FIG. 7.

As an example, the delay cell 200 of FIG. 3 has a frequency of 401.5 MHz to 812.1 MHz in a control voltage range of 0.2 V to 0.8 V. FIG. The frequency variable range of the delay cell 200 is 410.6 MHz.

For example, the delay cell 300 of FIG. 6 changes the frequency from 401.8 MHz to 731.5 MHz in the control voltage range of 0.4 V to 0.7 V. FIG. At this time, the range of the control voltage is also relatively small compared to the remaining delay cells (110, 200). The frequency variable range of the delay cell 300 is 329.7 MHz.

In the first delay cell 110 of FIG. 2, the frequency varies from 401.7 MHz to 883.6 MHz in the control voltage range of 0.2V to 0.8V. The variable range of the frequency of the first delay cell 110 is 480.9 MHz.

As a result, the first delay cell 110 has a frequency variable range as wide as 70.3 MHz compared to the delay cell 200. In addition, the first delay cell 110 has a frequency variable range as wide as 151.2MHz relative to the delay cell 300. Accordingly, the first delay cell 110 is relatively superior in frequency variable performance to other delay cells 200 and 300.

As a result, the voltage controlled oscillator 10 of the present invention can eliminate phase noise by removing the noise current in each of the delay cells as the proposed delay cell (for example, 110). In addition, the voltage controlled oscillator proposed in the present invention can improve the frequency variable performance.

10: voltage controlled oscillator
110, 120, 130, 140, 150, 160: delay cell
111: differential amplifier 112: first cascode section
113: second cascode part 200, 300: delay cell

Claims (17)

A delay cell corresponding to each of the plurality of stages connected in a ring shape and generating a voltage controlled oscillation signal,
The delay cell of the nth stage (n is an integer greater than 1) of the delay cells receives the first differential outputs from the delay cell of the n-1st stage and the first from the delay cell of the n-2nd stage. A voltage controlled oscillator pre-input of second differential outputs having a phase different from the one of the differential outputs. The method of claim 1,
The delay cell of the n th stage is
A differential amplifier for amplifying and outputting a voltage difference between input voltages received through the first input terminals;
A first cascode unit for removing a noise current generated by a transistor for frequency variation in a voltage level switching period by using a line input voltage received through one of the second input terminals; And
A second cascode unit for removing a noise current generated by a control transistor for frequency variation in a voltage level switching period by using a line input voltage received through the other one of the second input terminals,
And the first input terminals receive the first differential outputs and the second input terminals are pre-input of the second differential outputs. The method of claim 2,
The delay cell of the first stage of the plurality of stages receives the delay cell differential outputs of the last stage through the first input terminals and the delay cell differential outputs of the last previous stage through the second input terminals. Controlled oscillator. The method of claim 2,
The delay cell of the second stage of the plurality of stages receives the delay cell differential outputs of the first stage through the first input terminals and the delay cell differential outputs of the last stage through the second input terminals. Voltage controlled oscillator. The method of claim 2,
The differential amplifier is
A first transistor connected at a source to a power supply terminal, at a drain to a ground terminal through a third transistor, and at a gate to a drain of the second transistor;
A second transistor having a source connected to the power supply terminal, a drain connected to the ground terminal through a fourth transistor, and a gate connected to the drain of the first transistor;
A third transistor having a source connected to a ground terminal, a drain connected to a drain of the first transistor, and a gate connected to one of the first input terminals; And
And a fourth transistor connected at a source to a ground terminal, a drain connected to a drain of the second transistor, and a gate connected to the other one of the first input terminals. The method of claim 5, wherein
The differential amplifier is
A first output terminal positioned at a contact between the drain of the first transistor and the drain of the third transistor; And
And a second output terminal positioned at a contact between the drain of the second transistor and the drain of the fourth transistor. The method of claim 5, wherein
The first cascode unit
A fifth transistor connected at a source thereof to a contact point of the power supply voltage and the first transistor, at a drain thereof to a source of the first control transistor, and at a gate thereof connected to one of the second input terminals; And
A source is connected to the drain of the fifth transistor, a drain is connected to a contact between the first transistor and the third transistor, and a gate is connected to a control voltage input terminal to control the frequency to vary by reception of a control voltage. A voltage controlled oscillator comprising a first control transistor. The method of claim 7, wherein
And the fifth transistor is turned off to turn off the operation of the first control transistor in a voltage level transition period by the line input voltage. The method of claim 5, wherein
The second cascode part
A sixth transistor having a source connected to a contact point of the power supply voltage and the second transistor, a drain connected to a source of a second control transistor, and a gate connected to another one of the second input terminals; And
A source is connected to the drain of the sixth transistor, a drain is connected to a contact between the second transistor and the fourth transistor, and a gate is connected to a control voltage input terminal to control the frequency to vary by reception of a control voltage. A voltage controlled oscillator comprising a second control transistor. The method of claim 9,
And the sixth transistor is turned off to turn off the operation of the second control transistor in a voltage level transition period by the line input voltage. A voltage controlled oscillation method of a voltage controlled oscillator corresponding to each of a plurality of stages and including delay cells configured in a ring shape,
Receiving a differential output from each of at least two delay cells in one of the delay cells; And
Removing a noise current generated in a control transistor for frequency variation in a period in which an output voltage level is switched using some of the received differential outputs,
And the differential outputs of each of the two delay cells have mutually different phases. The method of claim 11,
Removing the noise current
Turning off the operation of the control transistor using some of the received differential outputs in the output level transition period. The method of claim 11,
Receiving the differential output
If the one delay cell is a delay cell of n (n is an integer greater than 1) stage, the second differential outputs having a phase different from the first differential outputs from the delay cell of the n-2 stage are selected. Receiving an input; And
and receiving first differential outputs from the delay cell of the n-th stage. The method of claim 13,
And wherein some of the received differential outputs are the second differential outputs. The method of claim 11,
Receiving the differential output
If the one delay cell is the delay cell of the first stage, receiving the delay cell differential outputs of the last previous stage; And
A method of controlling voltage oscillation comprising receiving delay cell differential outputs of a last stage. The method of claim 15,
Receiving the differential output
Receiving delay cell differential outputs of the last stage when the one delay cell is a delay cell of a second stage; And
And receiving the delay cell differential outputs of the first stage. 17. The method of claim 16,
And some of said received differential outputs are said pre-input differential outputs.

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