KR20120049616A - Printed circuit board and via hole filling method thereof - Google Patents

Abstract

PURPOSE: A printed circuit board and a method for filling a via hole thereof are provided to fill various via holes to have a small dimple or without a dimple. CONSTITUTION: A via hole(220) is formed on a base substrate(210). The via hole is divided into a first division via(220a) and a second division via(220b). A metal paste layer(230) is interposed to the first division via. A fill plating layer(240) is interposed to the second division via.

Description

Printed Circuit Board and Via Hole Filling Method {PRINTED CIRCUIT BOARD AND VIA HOLE FILLING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board and a method for filling via holes thereof, and more particularly, after dividing a via hole to be formed into a plurality of divided vias, a part of the divided vias are processed and filled primarily, and the remainder of the divided vias is processed. The present invention relates to a printed circuit board and secondary via-hole filling method.

Recently, the miniaturization and technology integration of electronic devices and products due to the advancement of electronic devices and products has been steadily developing, along with the miniaturization and technology of manufacturing process of printed circuit boards (PCBs) used in electronic devices. In response to integration, various changes are required.

The technical direction of the method of manufacturing the printed circuit board was initially developed from a single-sided board to a double-sided board, and then back to a multi-layered board. In particular, in manufacturing a multi-layered board, a manufacturing method called a build-up method has recently been developed. This is in development.

In the process of manufacturing the multilayer substrate, an inner via hole (IVH), a blind via hole (BVH), or a plated through hole (PUT) is used to electrically connect the circuit pattern and the electronic device of each layer. Various via holes such as PTH) are formed.

In the process of forming a via hole according to the prior art, first, a via hole is formed using a drill in a substrate, and a desmearing operation is performed on the surface of the substrate and the inner circumferential surface of the via hole, and then the inner space of the via hole is filled with metal.

In this case, a fill plating method is used to fill the inner space of the via hole with metal, and the fill plating method is difficult to apply to a via hole having a predetermined size or more.

That is, in the case of a large via hole, dimples are greatly generated, and even if the thickness of the plating becomes thick, it is difficult to properly plate the via hole.

The idea of the present invention is to divide the via hole to be formed into a plurality of divided vias, and then process a portion of the divided vias firstly and fill them, and then process and fill the remaining portions of the divided vias to easily fill the via holes. The present invention provides a printed circuit board and a via hole filling method thereof.

To this end, a printed circuit board according to an embodiment of the present invention includes a base substrate on which a via hole is formed; And a first and second divided vias formed by dividing the via holes, wherein the first divided vias are interposed with a metal paste layer, and the second divided vias are interposed with a peel plating layer.

Here, the first and second divided vias are alternately disposed in the via hole.

The fill plating layer may include a filling plating layer filled in the second divided via; And a separation plating layer interposed between the first and second divided vias to separate the first and second divided vias.

In this case, the filling plating layer is an electrolytic plating layer, the separation plating layer is an electroless plating layer.

In addition, the separation plating layer is interposed in a sawtooth shape.

A via hole filling method of a printed circuit board according to an embodiment of the present invention includes a division step of dividing a via hole to be formed in a base substrate into a predetermined number; Forming a first via by first processing a part of the divided via hole to form a first via; A first filling step of filling the formed first divided vias with a metal paste; A second via forming step of second processing the remainder of the divided via hole to form a second divided via; And filling the via hole by peeling the formed second divided via.

Here, the second filling step includes an electroless plating layer forming step of forming an electroless plating layer on the formed second divided via.

In addition, the second filling step includes an electroplating layer forming step of forming an electroplating layer on the second divided via where the electroless plating layer is formed after the electroless plating layer forming step.

As described above, according to the printed circuit board and the via hole filling method according to the embodiment of the present invention, there is an advantage in that the via holes of various shapes having a large size may be filled to have no dimples or dimples having a small thickness.

In addition, there is an advantage that can be filled in a thin thickness via holes of various shapes having a large size.

1 is a cross-sectional view illustrating a printed circuit board according to an exemplary embodiment of the present invention.
2 to 7 are cross-sectional views illustrating a via hole filling process of a printed circuit board according to an exemplary embodiment of the present invention.
8 and 9 illustrate an example of dividing into a plurality of divided vias according to the shape of a via hole.

The terms or words used in this specification and claims are not to be construed as being limited to their ordinary or dictionary meanings, and the inventors may appropriately define the concept of terms in order to best describe their invention. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that the present invention.

Therefore, the embodiments described in this specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention and do not represent all the technical ideas of the present invention. Therefore, It is to be understood that equivalents and modifications are possible.

1 is a cross-sectional view showing a printed circuit board according to an embodiment of the present invention.

As shown in FIG. 1, the printed circuit board 200 includes a base substrate 210, first and second divided vias 220a and 220b.

The base substrate 210 is a raw material of the printed circuit board 200, and via holes 220 are formed.

The base substrate 210 may be made of a copper clad laminate (CCL) or a glass fiber substrate (glass fiber reinforced preflag impregnated with a thermosetting resin composition) impregnated with a thermosetting resin composition. Among them, the copper foil laminate includes a single-sided copper foil laminate formed by sequentially depositing an insulating layer and a copper film, and a double-sided copper foil laminate formed by sequentially depositing a lower copper film, an insulation layer, and an upper copper film.

In addition, the via hole 220 is a through-hole (PTH) passing through the base substrate 210. After processing the reference hole as a reference using an X-ray drill or a sensor drill, the reference hole is referred to. By using a Computer Numerical Control (CNC) drill, the via hole 220 may be formed at a desired position on the substrate.

In addition, the via hole 220 may be formed using a UV (Ultraviolet) laser or a CO ₂ (Carbon dioxide) laser. Here, the laser is not limited thereto, and the via hole 220 may be formed using various laser means.

The first and second divided vias 220a and 220b are formed by dividing the via holes 220 and are alternately disposed in the via holes 220.

For example, when the inside of the via hole 220 is divided into five, the via hole corresponding to 220a ₁ , 220a ₂ , and 220a ₃ is the first divided via 220a and the 220b ₁ , 220b ₂ corresponds to the divided via holes. The via hole is the second split via 220b. That is, the plurality of divided vias 220a and 220b may be formed by dividing one via hole 220.

The metal paste layer 230 is interposed in the first divided via 220a. In the filling of the metal paste, a first operation of filling the first divided via 220a and pressing of the filled metal paste by moving the metal paste into the first divided via 220a by using a squeeze. This is done by alternately performing the second operation.

As described above, the first divided via 220a may be filled with the metal paste using various methods, in addition to the method of filling the first divided via 220a with the metal paste using a squeeze.

The fill plating layer 240 is interposed between the surface of the base substrate 210 and the inside of the second divided via 220b, and the fill plating layer 240 has the surface of the base substrate 210 and the second divided via 220b. It is made of a metal material such as copper, nickel, tin, and the like, and is configured to include the filling plating layers 244a and 244b, the separation plating layer 242a, and the plating layer 242b.

The filling plating layers 244a and 244b are metal layers interposed between the surface of the base substrate 210 and the inside of the second divided via 220b and may be formed of an electroplating layer.

The separation plating layer 242a is a metal layer interposed between the first and second divided vias 220a and 220b to separate the first and second divided vias 220a and 220b and may be configured as an electroless plating layer. It is sawtooth-shaped.

The plating layer 242b is a metal layer interposed on the surface 210b of the printed circuit board 210 and may be configured as an electroless plating layer.

The fill plating layer 240 including the above-described filling plating layers 244a and 244b, the separation plating layer 242a, and the plating layer 242b is filled by a fill plating method.

To this end, the surface of the base substrate 210 and the via hole 220, that is, the inside of the second divided via 220b are deposited on the separation plating layer 242a and the plating layer 242b which are the electroless plating layers by electroless plating, and then the base. Since the filling plating layers 244a and 244b, which are electroplating layers, are formed on the surface of the substrate 210 and the inside of the second divided via 220b by electroplating, the fill plating layer 240 is formed of an electroless plating layer (separated plating layer 242a and The electrolytic plating layer (charge plating layer 244a, 244b) is laminated | stacked on the plating layer 242b.

In summary, the structure of the printed circuit board described above will be described. First and second divided vias 220a and 220b are formed in the via hole 220 of the base substrate 210, and the first and second divided vias ( Since the insides of the 220a and 220b are filled with the paste filling method and the peel plating method, respectively, the filling plating layer 244a, that is, the electrolytic plating layer is formed inside the second divided vias 220a and 220b, respectively. An isolation plating layer 242a, ie, an electroless plating layer, is formed between the divided vias 220a and 220b to separate the via holes 220 into the first and second divided vias 220a and 220b.

Hereinafter, a via hole filling process of a printed circuit board according to an embodiment of the present invention will be described.

2 to 7 are cross-sectional views illustrating a via hole filling process of a printed circuit board according to an exemplary embodiment of the present invention.

2 to 7, a base substrate 210 is provided to manufacture a printed circuit board 200. In an embodiment of the present invention, a thin film of copper is formed on both surfaces through an insulating layer 210a. A copper clad laminate (CCL) having films 210b and 210c formed thereon is provided.

Here, the copper foil laminated plate 210 is a disk made of a printed circuit board generally is a structure in which a thin copper coated on the insulating layer, the thickness of the copper foil is usually 18 ~ 70㎛ about 5㎛, 7㎛ depending on the miniaturization of the wiring pattern 15 µm may also be used.

Next, the via holes 220 to be formed are divided into a predetermined number, which means that the via holes 220 are virtually divided in order to adjust the number of divisions according to the shape and size of the via holes 220.

8 and 9 illustrate an example of dividing into a plurality of divided vias according to the shape of the via hole, and show an example of dividing the via holes into a predetermined number.

FIG. 8 illustrates an example of dividing the via hole 220 when the via hole 220 is circular. As shown in FIGS. 8A and 8B, one of two divided vias is divided in a horizontal direction so that two divided vias are formed in the via hole. The split vias are configured to be primary processed, and the remaining split vias of the two divided vias are configured to be secondary processed.

FIG. 9 illustrates an example in which the via hole 920 is divided when the via hole 120 has a quadrangular shape. As shown in FIG. 9A, two divided vias are divided among four divided vias by vertically splitting four vias in the via hole. Allows for primary processing and the remaining two split vias for secondary processing. At this time, the split via to be processed first and the split via to be processed second are alternately arranged.

As shown in FIG. 9B, by dividing in the horizontal direction so that two divided vias are formed in the via hole, one divided via of the two divided vias is first processed, and the other divided via is second processed.

In addition, as shown in FIG. 9C, four divided vias of the eight divided vias are processed first, and the remaining four divided vias are processed second by dividing in the horizontal and vertical directions so that eight divided vias are formed in the via holes. The alternate arrangement of the divided vias for primary processing and the divided vias for secondary processing is alternately arranged.

Meanwhile, referring back to FIG. 3, a portion of the divided via hole 220 is first processed to form first divided vias 220a (220a ₁ to 220a ₃ ).

That is, the first divided vias 220a (220a ₁ to 220a ₃ ) are formed by using a drill in the direction of the lower copper film 210c from the upper copper film 210b which is the lower surface to the lower surface of the copper foil laminate 210.

Here, the process of forming the first divided vias 220a: 220a ₁ to 220a ₃ may be performed by using a mechanical drill or a UV, YAG, and CO ₂ laser drill. Form split vias.

As described above, after the first divided vias 220a (220a ₁ to 220a ₃ ) are formed, the first divided vias 220a: 220a ₁ to 220a ₃ are filled with the metal paste 230.

In this case, the metal paste 230 may be formed of a conductive paste, and the filling of the metal paste may be performed by moving the metal paste into the first divided via 220a by using a squeeze. The first operation of filling 220a and the second operation of pressing the filled metal paste are alternately performed.

As described above, the first divided via 220a may be filled with the metal paste using various methods, in addition to the method of filling the first divided via 220a with the metal paste using a squeeze.

Next, as shown in FIG. 5, the remaining portions of the divided via holes 220 are second processed to form second divided vias 220b (220b ₁ to 220b ₃ ).

That is, the second divided vias 220b (220b ₁ to 220b ₃ ) are formed by using a drill from the lower copper film 210c which is the upper surface to the upper copper film 210b in the lower surface of the copper foil laminate 210.

Here, the process of forming the second divided vias 220b: 220b ₁ to 220b ₃ may be performed using a mechanical drill or a UV, YAG, and CO ₂ laser drill. It is preferable to perform deburring and desmear to form divided vias and to remove various contaminants and foreign substances.

Deburring enhances the cohesion of copper in subsequent filling processes by removing roughness of copper foil, dust particles on the inner wall of vias, dust, fingerprints, etc. on the surface of copper foil, and at the same time, roughening the surface of copper foil.

Desmear melts the resin constituting the substrate by the heat generated during drilling and attaches to the inner wall of the via. Molten resin attached to the inner wall of the via plays a decisive role in degrading the quality of copper plating.

As described above, after forming the second divided vias 220b: 220b ₁ to 220b ₃ , performing deburring and desmearing, the surfaces 210b and 210c and the second divided vias 220b of the copper clad laminate 210. : Peel plate 220b ₁ ~ 220b ₃ ).

As shown in FIG. 6, the peel plating method is a separation plating layer 242a which is an electroless plating layer inside the surfaces 210b and 210c and the second divided vias 220b: 220b ₁ to 220b ₃ of the copper clad laminate 210. ) And the plating layer 242b. That is, in order to impart electrical conductivity to the surfaces 210b and 210c and the second divided vias 220b (220b ₁ to 220b ₃ ) of the copper-clad laminate 210, electroless plating is performed to give the electroless plating layer 242a ( 242b).

In this case, the electroless plating process is a process of forming a seed layer for electroplating the second divided vias 220b: 220b ₁ to 220b ₃ , and may be performed by electroless plating + electroplating.

Then, the surfaces 210b and 210c and the second divided vias 220b (220b ₁ to 220b ₃ ) of the electroless copper plated copper foil laminate 210 are electroplated to charge the plating layers 244a and 244b which are electrolytic metal layers. By forming, the whole copper foil laminated board 210 is peel-plated.

Electrolytic plating the inside _{of: (120b 1 ~ 120b 3 120b} ) wherein the electroless plating is the second partition via the already electroless copper plating because it is not possible to laminate the plated layer as obtained reliability demanding the process takes a long time Plated thicker once more.

In the above process, in order to form a circuit later, after the plating is completed on both surfaces of the substrate, the etching resist (the same material as the plating resist) is selectively applied only to the portion where the circuit should remain, that is, the circuit pattern portion, and the etching process is performed. After that, the etching resist can be removed to form a circuit.

In this case, the method of selectively applying the etching or plating resist may be performed by applying the etching or plating resist as a whole and then selectively etching or selectively leaving the plating resist through an exposure and developing process.

In another method of forming a circuit, if the plating resist is selectively applied only to a portion that should not be plated before performing electroplating, the circuit can be formed because the electroplating layer is formed in a circuit shape.

In addition, various methods may be used to form the circuit.

In summary, the thickness of the plating is increased to fill the large via hole, and the etching amount is increased to form a pattern, so it is difficult to apply a fine pattern or to remove unnecessary thickness. There was a problem to remove a certain thickness in the way. In addition, in the case of a large via hole, a dimple, which is a concave portion, was formed large on the surface, so that plating could not be completely performed by plating.

In order to solve this problem, in one embodiment of the present invention, a via hole is virtually divided into a plurality of divided vias, and a part of the divided vias are processed by a method such as a drill to fill only the processed space with a metal paste. Subsequently, after the remainder of the divided vias are processed on the opposite side of the base substrate by a method such as a drill, the inside of the via holes can be effectively filled without dimples by peel plating.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, Various changes and modifications will be possible.

210. Base substrate 220. Via hole
220a. First Split Via 220b. 2nd split via
230. Metal paste layer 240. Peel plating layer
242a. Separation plating layer 244a, 244b. Fill plating layer
242b. Plating layer

Claims (8)

A base substrate on which via holes are formed;
First and second divided vias formed by dividing the via holes;
The first divided via is interposed with a metal paste layer,
A printed circuit board having a fill plating layer interposed therebetween.
The method of claim 1,
The first and second divided vias,
Printed circuit boards are arranged alternately in the via hole.
The method of claim 1,
The peel plating layer,
A fill plating layer filled in the second divided via;
And a separation plating layer interposed between the first and second divided vias to separate the first and second divided vias.
The method of claim 3, wherein
The filling plating layer,
An electrolytic plating layer,
The separation plating layer,
Printed circuit board with an electroless plating layer.
The method of claim 3, wherein
The separation plating layer,
Printed circuit board with tooth shape.
A dividing step of dividing the via holes to be formed in the base substrate by a predetermined number;
Forming a first via by first processing a part of the divided via hole to form a first via;
A first filling step of filling the formed first divided vias with a metal paste;
A second via forming step of second processing the remainder of the divided via hole to form a second divided via;
And a second filling step of filling the formed second divided via to fill the via hole.
The method of claim 1,
The second charging step,
And a process of forming an electroless plating layer on the formed second divided vias.
The method of claim 7, wherein
The second charging step,
After the electroless plating layer forming step, forming an electroplating layer on the second divided via in which the electroless plating layer is formed.

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