KR20120045310A - Method for forming fine pattern for semiconductor device - Google Patents

Method for forming fine pattern for semiconductor device Download PDF

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Publication number
KR20120045310A
KR20120045310A KR1020100106770A KR20100106770A KR20120045310A KR 20120045310 A KR20120045310 A KR 20120045310A KR 1020100106770 A KR1020100106770 A KR 1020100106770A KR 20100106770 A KR20100106770 A KR 20100106770A KR 20120045310 A KR20120045310 A KR 20120045310A
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KR
South Korea
Prior art keywords
pattern
etching
sacrificial layer
forming
film
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KR1020100106770A
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Korean (ko)
Inventor
김희정
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100106770A priority Critical patent/KR20120045310A/en
Publication of KR20120045310A publication Critical patent/KR20120045310A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/70516—Calibration of components of the microlithographic apparatus, e.g. light sources, addressable masks or detectors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7023—Aligning or positioning in direction perpendicular to substrate surface
    • G03F9/703—Gap setting, e.g. in proximity printer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of forming a fine pattern of a semiconductor device. According to another aspect of the present invention, there is provided a method of forming a fine pattern of a semiconductor device, the method comprising: forming a sacrificial film in which a first sacrificial film and a second sacrificial film are sequentially stacked on a substrate on which a hard mask film is formed; Patterning the sacrificial layer to form a sacrificial layer pattern having a line width greater than that of the first sacrificial layer pattern; Forming a spacer along an entire surface of the substrate including the sacrificial layer pattern; Etching the spacers to form a spacer pattern; Removing the sacrificial layer pattern; And etching the hard mask layer using the spacer pattern as an etching barrier. According to the method for forming a fine pattern of a semiconductor device according to the present invention, the fine pattern of the semiconductor device can be formed to have a uniform fine pattern interval while forming a fine pattern exceeding the limit resolution of a conventional exposure apparatus. Thereby, the reliability of the semiconductor device manufacturing technology can be improved.

Description

Method of forming fine pattern of semiconductor device {METHOD FOR FORMING FINE PATTERN FOR SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a fine pattern of a semiconductor device.

As the degree of integration of semiconductor devices increases, the size of the semiconductor devices formed inside the cell is gradually decreasing as the design rules decrease drastically. Accordingly, in order to form a fine photoresist pattern, high resolution of photo-lithography exposure equipment is required, and thus, many difficulties arise in manufacturing a semiconductor device forming a cell.

In order to overcome the optical limitations of photolithography for the fine patterns beyond the limit resolution of the exposure equipment, a photoresist pattern is formed and then the photoresist pattern is heated to a temperature higher than the glass transition temperature of the photoresist and reflowed to form a photoresist pattern. And a process using a RELACS (Resist Enhancement Lithography Assisted by Chemical Shrink) material were used.

However, in the case of photoresist reflow or RELACS process, it is almost impossible to form a fine pattern of 30 nm level due to resolution limitation and photoresist volume reduction.

Accordingly, SPT (Spacer Patterning Technology) processes have been developed to form fine patterns that exceed the limit resolution of current exposure equipment.

The SPT process is a process of forming a fine pattern using a spacer pattern as an etch barrier after forming a spacer pattern serving as a side wall, in which a space dimension (CD) of the fine pattern is unevenly formed. There is a problem. It will be described below in detail through the drawings.

1A to 1E are diagrams for explaining a conventional SPT process.

As shown in Fig. 1A, an amorphous carbon film 13 and a SiON film 14 are formed on a substrate 11 on which a polysilicon film 12 to be used as a hard mask film is formed. The amorphous carbon film 13 and the SiON film 14 are films for forming a spacer pattern. Next, the photosensitive film pattern 15 is formed through the photosensitive film application | coating, exposure, and image development process.

As shown in FIG. 1B, the SiON film 14 is etched using the photosensitive film pattern 15 as an etching barrier to form a SiON pattern 14A. Subsequently, the amorphous carbon film 13 is etched using the SiON pattern 14A as an etching barrier to form the amorphous carbon pattern 13A. At this time, there is the etching process of the amorphous carbon film 13 is performed on etching conditions including the Ar and CH 4 as an etching gas, Ar and CH 4 etching gas is substantially the SiON pattern (14A) and the amorphous carbon film 13 The SiON pattern 14A is also etched by etching with the same etching rate.

Therefore, the SiON pattern 14A, which is an etching barrier, is also etched, so that the CD of the remaining SiON pattern 14A has a narrower profile than the amorphous carbon pattern 13A.

As shown in FIG. 1C, an oxide film 16 is formed along the entire surface of the SiON pattern 14A and the amorphous carbon pattern 13A. The oxide film 16 is a film that becomes the spacer pattern 16A through a subsequent entire etching process.

As shown in FIG. 1D, the oxide layer 16 is etched entirely to form the spacer pattern 16A. At this time, the SiON pattern 14A is also etched and removed. At this time, the spacer pattern 16A has a horn profile. The horn profile is formed because the support for the spacer pattern has a narrow profile at the top. That is, since the CD of the SiON pattern 14A is narrower than the CD of the amorphous carbon pattern 13A, the etching area of the spacer 16 formed on the sidewall of the amorphous carbon pattern 13A during the entire etching of the oxide film 16 increases. Accordingly, the horn-shaped spacer pattern 16A is formed.

As illustrated in FIG. 1E, the polysilicon layer 12 is etched using the horn-shaped spacer pattern 16A as an etch barrier to form the polysilicon pattern 12A. At this time, the space between the polysilicon patterns 12A is unevenly formed as " S1, S2 " as shown in Fig. 1E. This is because when the polysilicon layer 12 is etched, the profile of the spacer pattern 16A, which is a horn-type etch barrier, is transferred together while being etched. As such, when a micropattern is manufactured by etching an etched layer (not shown) using the polysilicon pattern 12A having a non-uniform pattern spacing, the micropattern is formed nonuniformly, thereby ensuring reliability as a semiconductor manufacturing technology. There is no problem.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a method of forming a fine pattern of a semiconductor device having a uniform fine pattern interval while forming a fine pattern exceeding the limit resolution of a conventional exposure apparatus. It is done.

According to an aspect of the present invention, there is provided a method of forming a fine pattern of a semiconductor device, the method including: forming a sacrificial film in which a first sacrificial film and a second sacrificial film are sequentially stacked on a substrate on which an etched layer is formed; Patterning the sacrificial layer to form a sacrificial layer pattern having a line width greater than that of the first sacrificial layer pattern; Forming a spacer along an entire surface of the substrate including the sacrificial layer pattern; Etching the spacers to form a spacer pattern; Removing the sacrificial layer pattern; And etching the etching target layer using the spacer pattern as an etching barrier.

According to the method for forming a fine pattern of a semiconductor device according to the present invention, the fine pattern of the semiconductor device can be formed to have a uniform fine pattern interval while forming a fine pattern exceeding the limit resolution of a conventional exposure apparatus. Thereby, the reliability of the semiconductor device manufacturing technology can be improved.

1A to 1E are diagrams for explaining a conventional SPT process.
2A to 2F are diagrams for describing a method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

In the following, the most preferred embodiment of the present invention is described. In the drawings, the thickness and spacing are expressed for convenience of description and may be exaggerated compared to the actual physical thickness. In the present specification, the expression 'after step' or 'following step' means not only performing another step directly after performing one step, but also meaning that a third step may be further performed after performing one step. Included.

2A to 2F are diagrams for describing a micropattern forming method of a semiconductor device according to an embodiment of the present invention. In particular, FIG. 2A to FIG. 2F illustrate a micropattern forming method using SPT (Spacer Pattern Technology).

Referring to FIG. 2A, the first and second sacrificial layers 23 and 24 are formed as a sacrificial layer for forming a spacer pattern on a substrate 21 on which a hard mask layer 22 for forming a fine pattern is formed. It is formed by laminating. The hard mask layer 22 is patterned to become an etching barrier for etching an etched layer (not shown), and a polysilicon layer is preferable. The first sacrificial film 23 and the second sacrificial film 24 are structures for forming a spacer pattern in a subsequent process, and are sacrificial films removed in a subsequent process.

As an example of the first sacrificial film 23, an amorphous carbon film or a spin on carbon (SOC) film is exemplified as a carbon-based film, and a SiON film may be used as an example of the second sacrificial film 24.

Subsequently, after the antireflection film (not shown) and the photosensitive film are applied, the photosensitive film pattern 25 is formed by exposing and developing the mask (not shown) as a barrier.

Referring to FIG. 2B, the second sacrificial layer 24 is etched using the photoresist pattern 25 as an etching barrier. While the second sacrificial layer 24 is etched, the photoresist pattern 25 serving as an etching barrier may also be removed, and the photoresist pattern 25 may be partially removed until the etching process of the second sacrificial layer 24 is completed. It can either remain or be removed. FIG. 2B illustrates an example in which a portion of the photoresist pattern 25 remains after the etching process of the second sacrificial layer 24. As illustrated in FIG. 2B, the etched photoresist pattern is indicated by reference numeral 25A. The etched second sacrificial layer is shown by reference numeral 24A.

Referring to FIG. 2C, the first sacrificial layer 23 is etched using the photoresist pattern 25A and the second sacrificial layer 24A as an etching barrier. An etching condition of the first sacrificial layer 23 is performed under an etching condition in which the etching rate of the first sacrificial layer 23 is higher than that of the second sacrificial layer 24A serving as an etching barrier.

The etching condition may be performed by a dry etching process. In this case, the etching condition may be controlled through an etching control factor such as an etching gas, an internal pressure of the etching vessel, or an upper and lower voltage of the etching vessel.

For example, when the first sacrificial film 23 is an amorphous carbon film and the second sacrificial film 24 is a SiON film, the etching gas of the first sacrificial film 23 is selected from the group including HBr and Cl 2 . It is carried out using an etching gas containing at least one. In this case, the etching gas has a faster etching reaction to the amorphous carbon film than the SiON film. That is, the second sacrificial layer 24A, which serves as an etch barrier during the etching process of the first sacrificial layer 23, is also etched. Therefore, the edge of the second sacrificial film 24A is etched with a relatively small area where the etched area is relatively small. On the contrary, the etching process is performed under an etching condition where the etching rate of the first sacrificial layer 23 is relatively high. In this case, the upper edge of the first sacrificial layer 23 is further etched into the first sacrificial layer 23. In addition, as the etching process proceeds further, the profile of the first sacrificial layer 23 is formed with the upper portion etched more than the lower portion. When the etching process of the first sacrificial layer 23 is completed, the CD (Critical Dimension) of the second sacrificial layer pattern 24B may be wider than the CD of the first sacrificial layer pattern 23A. Preferably, the second sacrificial film pattern 24B has a round shape, and the first and second sacrificial film patterns 23A and 24B may be formed in a matched (or mushroom) profile.

Referring to FIG. 2D, spacers 26 are formed on the front surface of the structure including the first and second sacrificial film patterns 23A and 24B. The spacer 26 is a material that is formed to form a spacer pattern. The spacer 26 may be formed of an oxide film or, preferably, Ultra Low Temp Oxide (ULTO). In particular, ULTO has an advantage of forming a spacer 26 that has excellent step coverage and thus reflects the profiles of the first and second sacrificial film patterns 23A and 24B.

Referring to FIG. 2E, the spacer 26 is etched to form a spacer pattern 26A. In this case, a portion of the sacrificial layer patterns 23A and 24B may also be removed. For example, when the second sacrificial film 24B is SiON and the spacer 26 is ULTO, since the second sacrificial film 24B and the spacer 26 do not have high etching selectivity, the front etching of the spacer 26 is performed. The second sacrificial film 24B is also removed.

When the entire surface of the spacer 26 is etched, a spacer portion having a wide CD (that is, a portion formed surrounding the second sacrificial film pattern 24B) has a wide CD, thereby increasing the etching area. As a result, the first sacrificial film pattern ( The upper edge portion of the spacer formed on the sidewall of 23A) becomes less etched. That is, the spacer portion formed on the sidewall of the first sacrificial layer pattern 23A may be formed to be close to the vertical profile. That is, since the upper spacer 26 has a large etching area, the inclination of the upper spacer 26 is gradually gradual as the etching progresses. As a result, the spacer pattern 26A on which the entire surface etching process is completed is formed close to the vertical profile.

Referring to FIG. 2F, the remaining sacrificial film pattern 23A is removed by a strip process. As a result, the spacer pattern 26A having the open portion 203 as the region where the fine pattern is to be formed is formed. The spacer pattern 26A is used as an etching barrier for etching the hard mask layer 22.

Subsequently, the hard mask layer 22 is etched using the spacer pattern 26A as an etching barrier to form the hard mask pattern 22A. At this time, since the spacer pattern 26A is formed close to the vertical profile, the spacer pattern 26A is uniformly transferred to the hard mask film 22 so that the space S between the hard mask patterns 22A is uniformly formed.

As described above, an etched layer (not shown) formed at the lower portion of the hard mask layer 22 having the uniform space S as an etch barrier may be etched to form a fine pattern having a uniform spacing.

In this way, the object of the present invention can be achieved.

The present invention is not limited to the above-described embodiments, but can be implemented in various forms, and the above-described embodiments make the disclosure of the present invention complete so that those skilled in the art can fully understand the scope of the invention. It is provided to give. Therefore, it should be noted that the scope of the present invention should be understood by the claims of the present application.

21 substrate 22 visual layer 23 first sacrificial film
24 second sacrificial film 25 photosensitive film pattern 26 spacer

Claims (6)

Forming a sacrificial film in which a first sacrificial film and a second sacrificial film are sequentially stacked on a substrate on which a hard mask film is formed;
Patterning the sacrificial layer to form a sacrificial layer pattern having a line width greater than that of the first sacrificial layer pattern;
Forming a spacer along an entire surface of the substrate including the sacrificial layer pattern;
Etching the spacers to form a spacer pattern;
Removing the sacrificial layer pattern; And
Etching the hard mask layer using the spacer pattern as an etching barrier
Method of forming a fine pattern of a semiconductor device comprising a.
The method of claim 1,
Forming the sacrificial layer pattern is
Forming a photoresist pattern on the sacrificial layer;
Etching the second sacrificial layer using the photoresist pattern as an etching barrier; And
Etching the first sacrificial layer using the second sacrificial layer as an etching barrier,
The etching of the first sacrificial layer may be performed under an etching condition in which the etching rate of the first sacrificial layer is higher than that of the second sacrificial layer.
Method of forming a fine pattern of a semiconductor device.
The method of claim 2,
The etching of the first sacrificial layer may be performed by using an etching gas having a higher etching rate on the second sacrificial layer than the first sacrificial layer.
Method of forming a fine pattern of a semiconductor device.
The method of claim 1,
The first sacrificial film includes an amorphous carbon film or a spin on carbon (SOC) film,
The second sacrificial film includes a SiON film
Method of forming a fine pattern of a semiconductor device.
The method of claim 4, wherein
The etching condition of the first sacrificial layer is
Carried out using an etching gas comprising at least one of a set comprising HBr and Cl 2
Method of forming a fine pattern of a semiconductor device.
The method of claim 1,
The spacer includes ULTO (Ultra Low Temp Oxide)
Method of forming a fine pattern of a semiconductor device.
KR1020100106770A 2010-10-29 2010-10-29 Method for forming fine pattern for semiconductor device KR20120045310A (en)

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KR1020100106770A KR20120045310A (en) 2010-10-29 2010-10-29 Method for forming fine pattern for semiconductor device

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KR20120045310A true KR20120045310A (en) 2012-05-09

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