KR20120043278A - Liquid crystal display and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display and a driving method thereof, wherein when the current data is larger than previous data, the impulse data is selected as white gray data, and when the current data is smaller than the previous data, the impulse data is selected as black gray data. Subsequently, during the allotted impulse driving period within one frame period, the data voltage of the impulse data is written into the pixel of the liquid crystal display panel.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

The present invention relates to a liquid crystal display and a driving method thereof.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. Liquid crystal displays can be miniaturized compared to cathode ray tubes (CRTs), which are applied to displays in portable information devices, office equipment, computers, etc., as well as televisions, and are rapidly replacing cathode ray tubes.

As in Equations 1 and 2, the liquid crystal has a slow response time due to the inherent viscosity and elasticity of the liquid crystal.

Where τr is the rising time when voltage is applied to the liquid crystal, Va is the applied voltage, V _F is the Freederick Transition Voltage at which the liquid crystal molecules start the tilt motion, and d is The cell gap of the liquid crystal cell,

(gamma) means rotational viscosity of liquid crystal molecules, respectively.

Here, τf denotes a falling time when the liquid crystal is restored to its original position by the elastic restoring force after the voltage applied to the liquid crystal is turned off, and K denotes an elastic modulus inherent to the liquid crystal.

The liquid crystal response speed of TN mode (Twisted Nematic mode), which has been the most commonly used liquid crystal display device, can vary depending on the physical properties of the liquid crystal material and the cell gap, but the rise time is about 20ms to 80ms and the polling time is It's about 20ms ~ 30ms long. The response speed of the liquid crystal is longer than one frame period (NTSC: 16.67ms). In FIG. 1, when the data voltage VD changes due to the slow response speed of the liquid crystal, the display luminance BL corresponding to the display voltage BL does not reach the desired luminance and thus cannot express the desired color and luminance. As a result, the liquid crystal display device exhibits motion blur in a moving image, and thus deteriorates image quality.

In order to improve the slow response speed of the liquid crystal, an overdriving compensation method (hereinafter, referred to as an "ODC") compensation method has been proposed in which a response voltage is increased by modulating a data voltage according to a change in data. The ODC compensation method modulates the input data voltage VD to a higher modulation data voltage MVD as shown in FIGS. Makes it possible to reach the target luminance MBL. In FIG. 3, 'FRn' means n (n is a natural number frame period, 'FRn + 1' means n + 1 frame period, and 'FRn + 2' means n + 2 frame period. Equation 1 is based on the change of data to obtain a desired luminance (MBL) within one frame period.

Increase Accordingly, the liquid crystal display device to which the ODC compensation method is applied may improve the image quality in the video by compensating for the late response speed of the liquid crystal by modulation of the data voltage as shown in FIGS. 2 and 3. The ODC compensation method compares data between a previous frame and a current frame and sets modulation data in consideration of changes between the data.

4 is a block diagram schematically illustrating an ODC compensation circuit.

Referring to FIG. 4, the ODC compensation circuit includes a frame memory 41 and a lookup table 42.

The frame memory 41 stores the current frame data Fn and supplies the previous frame data Fn-1 to the lookup table 42. The lookup table 42 stores preset modulation data MRGB as shown in Table 1 below. The lookup table 42 modulates the data by selecting the preset modulation data MRGB with the current frame data Fn and the previous frame data Fn-1 as addresses. The lookup table 42 includes a read only memory (ROM) and a memory control circuit.

division 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 2 3 4 5 6 7 9 10 12 13 14 15 15 15 15 One 0 One 3 4 5 6 7 8 10 12 13 14 15 15 15 15 2 0 0 2 4 5 6 7 8 10 12 13 14 15 15 15 15 3 0 0 One 3 5 6 7 8 10 11 13 14 15 15 15 15 4 0 0 One 3 4 6 7 8 9 11 12 13 14 15 15 15 5 0 0 One 2 3 5 7 8 9 11 12 13 14 15 15 15 6 0 0 One 2 3 4 6 8 9 10 12 13 14 15 15 15 7 0 0 One 2 3 4 5 7 9 10 11 13 14 15 15 15 8 0 0 One 2 3 4 5 6 8 10 11 12 14 15 15 15 9 0 0 One 2 3 4 5 6 7 9 11 12 13 14 15 15 10 0 0 One 2 3 4 5 6 7 8 10 12 13 14 15 15 11 0 0 One 2 3 4 5 6 7 8 9 11 13 14 15 15 12 0 0 One 2 3 4 5 6 7 8 9 10 12 14 15 15 13 0 0 One 2 3 3 4 5 6 7 8 10 11 13 15 15 14 0 0 One 2 3 3 4 5 6 7 8 9 11 12 14 15 15 0 0 0 One 2 3 3 4 5 6 7 8 9 11 13 15

In Table 1, the leftmost column is data of the previous frame Fn-1, and the uppermost row is data of the current frame Fn.

Since the conventional ODC compensation method includes a look-up table requiring a large memory capacity, the circuit cost is high, and the response speed improvement effect is not sufficient when gray to gray is changed.

The present invention provides a liquid crystal display device and a method of driving the same, which reduce circuit cost and improve the response speed improvement effect when changing between gray levels.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes: a liquid crystal display panel in which data lines and gate lines intersect and pixels in a matrix form are arranged by an intersection structure of the lines; Compare the current data with the previous data to be written in the same pixel and select the impulse data as the white gray data if the current data is larger than the previous data. Responsive characteristic improvement unit selected by; A timing controller for time-dividing one frame period into an impulse driving period and an original data driving period, outputting the impulse data during the impulse driving period, and outputting the current data during the original data driving period; A data driving circuit converting the digital video data including the impulse data and the current data into a data voltage and supplying the data voltage to the data lines; And a gate pulse synchronized with the data voltage of the current data during the original data driving period after sequentially supplying gate gates synchronized with the data voltage of the impulse data during the impulse driving period to the gate lines under the control of the timing controller. And a gate driving circuit which sequentially supplies pulses to the gate lines.

The response characteristic improvement unit selects the current data as the impulse data and the current data as the impulse data when the current data and the previous data are the same.

The response characteristic improving unit may include: a frame memory configured to output the previous data by delaying input data by one frame period; A comparator for comparing the current data with the previous data and outputting a comparison result; And a data selector which selects one of the white gray data, the black gray data, and the current data in response to a comparison result from the comparator.

The timing controller controls operation timings of the data driving circuit and the gate driving circuit. The gate timing control signal for controlling the operation timing of the gate driving circuit includes a gate start pulse for controlling the shift operation start timing of the gate driving circuit.

The timing controller supplies a first gate start pulse at a start point of the impulse driving period and then supplies a second gate start pulse at a start point of the original data driving period.

The impulse driving period is a time between 1 msec and 3 msec.

The driving method of the liquid crystal display device may include comparing current data with previous data to be written to the same pixel in a liquid crystal display panel; Selecting impulse data as white gray data if the current data is larger than the previous data; Selecting the impulse data as black gray data if the current data is smaller than the previous data; And time-dividing one frame period into an impulse driving period and an original data driving period, writing a data voltage of the impulse data into a pixel of the liquid crystal display panel during the impulse driving period, and writing the current data during the original data driving period. And writing to pixels of the liquid crystal display panel.

The present invention time-divids one frame period into an impulse driving period and an original data driving period, and writes a data voltage of the impulse data into a pixel of the liquid crystal display panel during the impulse driving period. As a result, the present invention can reduce the circuit cost by eliminating the look-up table required for the conventional ODC compensation circuit, and can also improve the response speed improvement effect when the gray scale changes.

1 is a view showing a change in luminance according to data in a conventional liquid crystal display device.
2 is a diagram illustrating an overdrive compensation method.
3 is a waveform diagram illustrating an example of a data voltage modulated by an overdrive compensation method.
4 is a circuit diagram illustrating an overdrive compensation circuit.
5 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
6 to 8 are views showing various examples of the TFT array applicable to the present invention.
9 is a view illustrating in detail the gate driving circuit shown in FIG. 5.
10 is a waveform diagram illustrating a gate timing control signal for controlling a gate driving circuit.
11 is a waveform diagram showing output waveforms of a data driving circuit and a gate driving circuit.
FIG. 12 is a block diagram illustrating in detail the response characteristic improvement unit illustrated in FIG. 5.
13A and 13B are waveform diagrams showing data voltages of impulse data.
14 is a waveform diagram showing an overshoot of the liquid crystal cell voltage generated when the impulse driving period is long.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 5, the liquid crystal display according to the exemplary embodiment of the present invention is connected to the liquid crystal display panel 10, the response characteristic improving unit 17, and the data lines D1 to Dm of the liquid crystal display panel 10. Timing for controlling the data driving circuit 12, the gate driving circuit 13 connected to the gate lines G1 to Gn of the liquid crystal display panel 10, the data driving circuit 12 and the gate driving circuit 13. The controller 11 and the module power supply unit 15 for generating a driving voltage of the liquid crystal display panel 10 are provided.

The liquid crystal display panel 10 includes a TFT array substrate and a color filter array substrate facing each other with a liquid crystal layer interposed therebetween. The TFT array substrate includes data lines D1 to Dm, gate lines G1 to Gn intersecting the data lines D1 to Dm, data lines D1 to Dm, and gate lines G1 to Gn. TFTs formed at intersections of the pixels, and the pixel electrode 1 connected to the TFTs. The TFT array formed on the TFT array substrate may be implemented in various forms as shown in FIGS. 6 to 8. Each of the liquid crystal cells Clc is driven by the voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied and is incident from the backlight unit 16. The amount of light transmitted is adjusted to display an image of video data. A black matrix, a color filter, and a common electrode are formed on the color filter array substrate. The common electrode 2 is formed on the color filter glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and is in the in plane switching (IPS) mode and the fringe field switching (FFS) mode. In the horizontal electric field driving method as described above, the pixel electrode 1 is formed on the TFT array substrate. A polarizing plate is attached to each of the TFT array substrate and the color filter array of the liquid crystal display panel 10 and an alignment film for setting the pre-tilt angle of the liquid crystal is formed.

The liquid crystal mode of the liquid crystal display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, the backlight unit 16 is required. The backlight unit 16 may be implemented as a direct type backlight unit or an edge type backlight unit.

The impulse data W / B is preset in the response characteristic improving unit 17 regardless of the digital video data of the input image. The impulse data W / B is selected by the response characteristic improving unit 17 as either white gray data or black gray data. The white gray data and the black gray data are preset in the response characteristic improving unit 17 irrespective of the digital video data of the input image. The white gradation data is set to data which can be converted into the highest gamma compensation voltage by the data driving circuit 12. The black gradation data is set to data which can be converted into the lowest gamma compensation voltage by the data driving circuit 12. For example, the white gray data may be set to 11111111 ₂ , and the black gray data may be set to 00000000 ₂ .

The response characteristic improving unit 17 compares the previous frame data with the current frame data every frame period. If the current data is larger than the previously input data as shown in FIG. The impulse data (W / B) is selected as the white gradation data (White) as follows. On the other hand, if the current data (Current data) is smaller than the previous data (Previous data), the response characteristic improving unit 17 selects the impulse data (W / B) as black gray data (Black) as shown in FIG. The response characteristic improving unit 17 supplies the current data to the timing controller 11 as it is if the current data and the previous data are the same. The response characteristic improving unit 17 may be built in the timing controller 11.

Previous data <Current data, then Impulse = White

Previous data> Current data, then Impulse = Black

Previous data = Current data, then Impulse = Current data

The data driver circuit 12 includes a plurality of source drive ICs. Each of the source drive ICs latches after sampling the impulse data W / B and the digital video data RGB 'input from the timing controller 11 in response to the data control signal SDC from the timing controller 11. Convert to data in parallel data system. Each of the source drive ICs converts the impulse data (W / B) and the digital video data (RGB ') converted from the parallel data transmission scheme to the positive / negative gamma reference voltages V _GMAO1 to V from the module power supply unit 15. _GMAO10 ) to convert into analog gamma compensation voltage. Each of the source drive ICs outputs a positive / negative analog video data voltage to be charged in the liquid crystal cells to the data lines D1 to Dm. Each of the source drive ICs supplies the data voltages to the data lines D1 to Dm while inverting the polarity of the positive / negative analog video data voltage under the control of the timing controller 11. The source drive ICs may be bonded onto the TFT array substrate of the liquid crystal display panel 10 by a chip on glass (COG) process. In addition, the source drive ICs may be mounted on a tape carrier package (TCP) and adhered to a printed circuit board (PCB) and a TFT array substrate of the liquid crystal display panel 10 by a tape automated bonding (TAB) process.

The gate driving circuit 13 includes a plurality of gate drive ICs. The gate drive IC sequentially supplies gate pulses (or scan pulses) to the gate lines, including a shift register that sequentially shifts the gate driving voltage in response to the gate control signal GDC from the timing controller 11. The gate drive ICs may be mounted on TCP and adhered to the TFT array substrate of the liquid crystal display panel 10 by a TAB process. The gate driving circuit 13 may be implemented as a GIP circuit formed directly on the TFT array substrate together with the TFT array by a gate in panel (GIP) process.

The timing controller 11 time-divides one frame period into an impulse driving period x and an original data driving period y as shown in FIGS. 13A and 13B. Control the drive timing. The timing controller 11 transmits the impulse data W / B input from the response characteristic improving unit 17 to the data driving circuit 12 during the impulse driving period x every frame period, and then drives the original data. During the period, the current data RGB 'input from the response characteristic improving unit 17 is transmitted to the data driving circuit 12. As described above, if the previous data and the current data are the same, the timing controller 11 transmits the current data RGB 'input from the response characteristic improving unit 17 to the data driving circuit 12 during the impulse driving period x. send. The impulse driving period x is independent of the input data and can be experimentally predetermined. According to the experimental results conducted by the inventors of the present invention, the optimum time of the impulse driving period x is a time between 1 msec and 3 msec. If the impulse driving period x is less than 1 msec, the effect of improving the response characteristics of the liquid crystal is small, and if it is 3 msec or more, overshoot occurs in the data voltage charged in the liquid crystal cell as shown in FIG. 14. The original data driving period y is the remaining time after subtracting the impulse driving period x from one frame period.

The timing controller 11 converts the impulse data W / B and the digital video data RGB 'input from the response characteristic improvement unit 17 during the impulse driving period x into a mini LVDS interface. Transfer to the data drive circuit 12. In addition, the timing controller 11 supplies the digital video data RGB inputted in the current frame to the response characteristic improving unit 17 during the original data driving period y.

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable DE, a dot clock CLK, and the like from the host system 14. The timing controller 11 uses the timing signals Vsync, Hsync, DE, and CLK to control the data timing control signal SDC for controlling the operation timing of the data driving circuit 12 and the operation of the gate driving circuit 13. A gate timing control signal GDC is generated to control timing.

The data timing control signal SDC includes a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, and a polarity control signal POL. And the like. The source start pulse SSP controls the data sampling start time of the data driving circuit 12. The source sampling clock SSC is a clock signal that controls the data sampling operation of the data driving circuit 12. If the digital video data RGB 'is transmitted to the data driver circuit 12 using the mini LVDS interface standard, it is not necessary to input the source start pulse SSP and the source sampling clock SSC. The polarity control signal POL controls the polarity of the data voltage output from the data driving circuit 12. The source output enable signal SOE controls the charge sharing timing and the data output timing of the data driving circuit 12.

The gate timing control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP controls the shift operation start timing of the gate driving circuit 13. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driving circuit 13.

The timing controller 11 generates the gate pulse twice in one frame period as shown in FIG. Accordingly, the gate driving circuit 13 sequentially applies the gate pulses to the gate lines G1 to Gn during the impulse driving period x in response to the first gate start pulse generated at the beginning of the impulse driving period x. After that, the gate pulses are sequentially applied to the gate lines G1 to Gn during the original data driving period y in response to the second gate pulse generated at the beginning of the original data driving period y.

The host system 14 transmits digital video data input from a broadcast receiving circuit or an external video source to the timing controller 11 through a low voltage differential signaling (LVDS) interface or a transition minimized differential signaling (TMDS) interface transmission circuit. The host system 14 transmits timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a dot clock CLK, and the like to the timing controller 11. The host system 14 includes a graphics processing circuit such as a scaler that interpolates the resolution of video data RGB input from a broadcast receiving circuit or an external video source to match the resolution of a liquid crystal display panel and performs signal interpolation, and a module power supply unit 15. It includes a power supply circuit for generating a voltage Vin to be supplied to.

The module power supply unit 15 adjusts the voltage Vin input from the power supply circuit of the host system 14 to generate driving voltages of the liquid crystal display panel 10. The driving voltages of the liquid crystal display panel 10 include a high potential power supply voltage Vdd of 8 V or less, a logic power supply voltage Vcc of about 3.3 V, a gate high voltage V _{GH of} 15 V or more, and a gate low voltage of -3 V or less. V _GL), and generates a common voltage such as (Vcom), the positive / negative gamma reference voltage (V _GMA1? V _GMA10) of 7V ~ 8V. Module power supply 15 using the voltage dividing circuit including a resistor string by dividing the high-potential power supply voltage (Vdd) and generates the positive polarity / negative polarity gamma reference voltage (V _GMA1? V _GMA10).

6-8 are equivalent circuits showing some of various examples of TFT arrays.

Referring to FIG. 6, in the first embodiment of the TFT array, each of the TFTs receives the data voltages from the data lines D1 to D6 in response to the gate pulses from the gate lines G1 to G4. The pixel electrode 1 is supplied to the pixel electrode 1 of the liquid crystal cell Clc disposed on the left side (or the right side) of the pixel. In this TFT array, neighboring red subpixels R, green subpixels G, and blue subpixels B are disposed along a row direction (or line direction) orthogonal to the column direction. When the resolution is m × n, m × 3 (where 3 is RGB) data lines and n gate lines are required.

Referring to FIG. 7, the second embodiment of the TFT array can reduce the number of data lines required at the same resolution to 1/2 compared to the TFT array shown in FIG. 6, and the number of required source drive ICs is 1/2. Can be reduced to In this TFT array, each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the column direction. One pixel in this TFT array includes neighboring red subpixels R, green subpixels G, and blue subpixels G along a line direction orthogonal to the column direction. The first and second liquid crystal cells Clc neighboring left and right with one data line interposed continuously charge the data voltage supplied in a time division manner through the data line. The first TFT T1 supplies the data voltage from the data lines D1 to D4 to the pixel electrode of the first liquid crystal cell in response to the gate pulses from the odd gate lines G1, G3, G5, and G7. The gate electrode of the first TFT T1 is connected to the odd gate lines G1, G3, G5, and G7, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the first TFT T1 is connected to the pixel electrode of the first liquid crystal cell. The second TFT T2 supplies the data voltage from the data lines D1 to D4 to the pixel electrode of the second liquid crystal cell in response to the gate pulses from the even gate lines G2, G4, G6, and G8. The gate electrode of the second TFT T2 is connected to the even gate lines G2, G4, G6, and G8, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the second TFT T2 is connected to the pixel electrode of the second liquid crystal cell.

Referring to FIG. 8, the third embodiment of the TFT array can reduce the number of data lines required at the same resolution by one third compared to the TFT array shown in FIG. 6, and the number of source drive ICs required is 1/3. Can be reduced to In this TFT array, each of the red subpixel R, the green subpixel G, and the blue subpixel B is disposed along the line direction. One pixel in this TFT array includes neighboring red subpixels R, green subpixels G, and blue subpixels G along the column direction. Each of the TFTs includes a pixel electrode of a liquid crystal cell in which data voltages from the data lines D1 to D6 are disposed on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G6. To feed.

As described above, the gate driving circuit 13 of the present invention sequentially applies gate pulses to the gate lines G1 to Gn during the impulse driving period x, and then gate lines during the original data driving period y. Gate pulses are sequentially applied to the fields G1 to Gn. The operation of the gate driving circuit 13 will be described in detail with reference to FIGS. 9 and 10.

9 is a view illustrating in detail the gate driving circuit shown in FIG. 5. 10 is a waveform diagram illustrating a gate timing control signal for controlling a gate driving circuit.

9 and 10, each of the gate drive ICs of the gate driving circuit includes a plurality of AND gates connected between the shift register 91, the level shifter 94, the shift register 91, and the level shifter 94. 92) and the like.

The shift register 91 sequentially shifts the gate start pulse GSP in synchronization with the rising edge of the gate shift clock GSC using a plurality of cascaded D-flip flops. Each of the AND gates 92 outputs the result of the AND operation of the output signal of the shift register 91 and the gate output enable signal GOE inverted by the inverter 93.

The level shifter 94 converts the output voltage swing width of the AND gate 92 into a swing width between the gate high voltage V _GH and the gate low voltage V _GL to sequentially apply the gate lines G1 to Gn. Supply.

The gate start pulse GSP is generated twice in one frame period. The first gate start pulse GSP is generated at the start of the impulse driving period x, and the second gate start pulse GSP is generated at the start of the original data driving period y. The shift register 91 sequentially shifts the first gate start pulse GSP during the impulse driving period x, and then sequentially shifts the second gate start pulse GSP during the original data driving period y. Therefore, the gate drive IC sequentially supplies the gate pulses to the gate lines G1 to Gn during the impulse driving period x as shown in FIG. 11, and then applies the second gate start pulse GSP during the original data driving period y. Shift sequentially.

As shown in FIG. 11, the data driving circuit 12 includes data of the current voltage or the data voltage of the impulse data W / B synchronized with the gate pulses sequentially supplied to the gate lines G1 to Gn during the impulse driving period x. After supplying the voltage to the data lines D1 to Dm, the data voltage of the current data synchronized with the gate pulses sequentially supplied to the gate lines G1 to Gn during the original data driving period y is obtained. Supply to D1 ~ Dm).

12 shows the response characteristic improving unit 17 in detail.

Referring to FIG. 12, the response characteristic improving unit 17 includes a frame memory 111, a comparator 112, a data selector 113, a register 114, and the like. In FIG. 12, 'FRn-1' is previous data input in the n-th frame period, and 'FRn' is current data input in the n-th frame period.

The frame memory 111 stores input data and delays the data for one frame period. The comparator 112 compares current data to be written to the same pixel in the liquid crystal display panel 10 with previous data delayed by the frame memory 111, and supplies the comparison result to the data selector 113.

The data selector 113 selects impulse data W / B to be written in the pixels during the impulse driving period x in response to the comparison result input from the comparator 112. If the current data is larger than the previous data, the data selector 113 outputs white gray data White as shown in FIG. 13A, and if the current data is smaller than the previous data, the data selector 113 outputs black gray data Black as shown in FIG. 13B. . In addition, if the current data and the previous data are the same, the data selector 113 supplies the current data to the timing controller 11 as impulse data. The register 114 stores white gray data Black and black gray data Black used as impulse data W / B, and supplies the data to the data selector 113.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10 liquid crystal display panel 11 timing controller
12: data driving circuit 13: gate driving circuit
17: response characteristics improvement unit

Claims (9)

A liquid crystal display panel in which data lines and gate lines intersect and pixels in a matrix form are arranged by an intersection structure of the lines;
Compare the current data with the previous data to be written in the same pixel and select the impulse data as the white gray data if the current data is larger than the previous data, and if the current data is smaller than the previous data, the impulse data is black gray data. Responsive characteristic improvement unit selected by;
A timing controller for time-dividing one frame period into an impulse driving period and an original data driving period, outputting the impulse data during the impulse driving period, and outputting the current data during the original data driving period;
A data driving circuit converting the digital video data including the impulse data and the current data into a data voltage and supplying the data voltage to the data lines; And
The gate pulse synchronized with the data voltage of the current data during the original data driving period after sequentially supplying gate gates synchronized with the data voltage of the impulse data during the impulse driving period to the gate lines under the control of the timing controller. And a gate driving circuit which sequentially supplies the gate lines to the gate lines.
The method of claim 1,
The response characteristic improving unit,
And if the current data is the same as the previous data, selecting the current data as the impulse data and the current data as the impulse data.
The method of claim 1,
The response characteristic improving unit,
A frame memory for outputting the previous data by delaying input data by one frame period;
A comparator for comparing the current data with the previous data and outputting a comparison result; And
And a data selector which selects one of the white gray data, the black gray data, and the current data in response to a comparison result from the comparator.
The method of claim 1,
The timing controller,
Control operation timings of the data driving circuit and the gate driving circuit;
And a gate timing control signal for controlling the operation timing of the gate driving circuit comprises a gate start pulse for controlling the shift operation start timing of the gate driving circuit.
The method of claim 1,
The timing controller,
And after the first gate start pulse is supplied at the start of the impulse driving period, the second gate start pulse is supplied at the start of the original data driving period.
The method of claim 1,
The impulse driving period is a time between 1 msec ~ 3 msec liquid crystal display device.
Comparing current data with previous data to be written to the same pixel in a liquid crystal display panel;
Selecting impulse data as white gray data if the current data is larger than the previous data;
Selecting the impulse data as black gray data if the current data is smaller than the previous data; And
Time-dividing one frame period into an impulse driving period and an original data driving period, writing a data voltage of the impulse data into a pixel of the liquid crystal display panel during the impulse driving period, and writing the current data into the liquid crystal during the original data driving period. And writing to the pixels of the display panel.
The method of claim 7, wherein
And selecting the current data as the impulse data if the current data and the previous data are the same.
The method of claim 7, wherein
And wherein the impulse driving period is a time between 1 msec and 3 msec.

Images