KR20120042817A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a formation method thereof are provided to reduce parasitic capacitance by forming a bit line spacer with an oxide film. CONSTITUTION: An storage electrode contact plug(26) is electrically connected to a junction region of a first active region. A bit line contact plug is electrically connected to a junction region of a second active region. A spacer is formed on a sidewall of the bit line contact plug and the storage electrode contact plug. The spacer insulates the storage electrode contact plug from the bit line contact plug. The spacer comprises an oxide film.

Description

Semiconductor device and its formation method {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a semiconductor device and a method of forming the same. More particularly, the present invention relates to a semiconductor device including a bit line and a method of forming the same.

In recent years, although the demand for increasing the capacity of semiconductor memory devices, particularly DRAM (DRAM) devices, is increasing, the capacity increase of DRAM devices is also limited due to an increase in chip size. Increasing chip size reduces the number of chips per wafer, resulting in reduced device productivity. Therefore, in recent years, efforts have been made to change cell layouts to reduce cell area, thereby consolidating more memory cells onto one wafer.

In order to protect the sidewall of the bit line, a spacer made of nitride is mainly used. Since the nitride film is a material having a relatively high dielectric constant, parasitic capacitance increases in the bit line. .

In the process of forming a storage electrode contact and a bit line, an invention in which two storage electrode contacts are formed at a time and a bit line is formed by using a damascene process, while separating the storage electrode contacts into two again. This is known. However, the present invention also suffers from an overlay problem when the storage electrode contact hole is etched, thereby increasing the contact resistance. In addition, when the bit line tungsten is formed by the damascene process, a tungsten etch back process is included. In this tungsten etch back process, polysilicon of the storage electrode contact plug is etched together.

The present invention is to solve the conventional problems as described above, by reducing the parasitic capacitance by forming the bit line spacer as an oxide film, and because the storage electrode contact is a line type, it is possible to secure a patterning margin, the storage electrode contact plug An object of the present invention is to provide a semiconductor device and a method for forming the same, which reduce leakage current by forming polysilicon having different concentrations.

In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate including an active region defined as an isolation layer, a bit line hole provided on the semiconductor substrate, an oxide film provided on sidewalls of the bit line hole, and A parasitic capacitance is reduced by forming a bit line spacer as an oxide film, including a bit line conductive layer embedded in a bit line hole in which an oxide film is formed.

Further, the storage device may further include a storage electrode contact hole provided adjacent to the bit line hole and connected to the semiconductor substrate, and a storage electrode contact plug embedded in the storage electrode contact hole.

In addition, the storage electrode contact plug may include a low concentration contact plug provided under the storage electrode contact hole and a high concentration contact plug provided on the low concentration contact plug in the storage electrode contact hole, thereby reducing leakage current such as a GIDL. It is characterized by.

The oxide film is formed on the sidewall of the storage electrode contact plug, and the oxide film formed on the high concentration contact plug is thicker than the thickness of the oxide film formed on the low concentration contact plug. It is desirable to prevent etching of the polysilicon layer in the etch back process.

In addition, the storage electrode contact hole is formed of a line type crossing the bit line, it is characterized in that the patterning margin can be secured.

Furthermore, it is preferable that the semiconductor device further includes a landing plug provided on the semiconductor substrate and disposed below the bit line hole and including polysilicon.

The semiconductor device may further include a bit line hard mask provided on the bit line conductive layer in the bit line hole to insulate and protect the bit line conductive layer.

The bit line conductive layer may include a barrier metal layer formed on a surface of the bit line hole and a conductive layer embedded in the bit line hole in which the barrier metal layer is formed.

In addition, a buried gate is formed to be embedded in the active region and the device isolation layer of the semiconductor substrate to a predetermined depth, characterized in that to reduce the parasitic capacitance of the bit line.

On the other hand, the method of forming a semiconductor device according to the present invention, forming a device isolation film defining an active region in the semiconductor substrate, forming a bit line hole on the semiconductor substrate, an oxide film on the sidewalls of the bit line hole And forming a bit line conductive layer in the bit line hole in which the oxide film is formed, thereby forming parasitic capacitance by forming a bit line spacer as an oxide film.

In this case, the forming of the oxide film on the sidewall of the bit line hole may include a dry oxidation process or a radical oxidation process.

Furthermore, after the step of forming an oxide film on the sidewall of the bit line hole, the bit line hole is etched back to remove the oxide film at the bottom of the bit line hole to expose the landing plug under the bit line hole. .

The method may further include forming a storage electrode contact plug on the semiconductor substrate before forming the bit line hole.

In the forming of the bit line hole, the patterning margin may be improved by separating the storage electrode contact plug.

The forming of the storage electrode contact plug may include forming a storage electrode contact hole exposing the semiconductor substrate, embedding polysilicon in the storage electrode contact hole, and performing a low concentration ion implantation process on the polysilicon. Forming a low concentration polysilicon layer on the bottom and performing a high concentration ion implantation process on the polysilicon to form a high concentration polysilicon layer on the top, characterized in that to reduce the leakage current, such as GIDL.

Further, the forming of the storage electrode contact plug may include forming a storage electrode contact hole exposing the semiconductor substrate, embedding polysilicon under the storage electrode contact hole, and performing a low concentration ion implantation process on the polysilicon. Forming a low concentration polysilicon layer, embedding polysilicon on the low concentration polysilicon layer, and performing a high concentration ion implantation process on the polysilicon to form a high concentration polysilicon layer on the low concentration polysilicon layer. It may include the step.

And forming an oxide film on the sidewalls of the bit line holes, oxidizing the storage electrode contact plug sidewalls, and forming an oxide film of the high concentration polysilicon layer thicker than the oxide film of the low concentration polysilicon layer. It is desirable to protect the polysilicon layer during the etchback process of the bitline conductive layer.

The forming of the storage electrode contact hole may include forming the storage electrode contact hole in a line type crossing the bit line to secure a patterning margin.

In addition, after the forming of the bit line conductive layer, it is preferable to protect the bit line conductive layer by forming a bit line hard mask on the bit line conductive layer in the bit line hole.

Further, the forming of the bit line conductive layer may include forming a barrier metal layer on a surface of the bit line hole and filling a conductive layer in the bit line hole in which the barrier metal layer is formed. .

The method may further include forming a buried gate in the semiconductor substrate of the cell region before forming the bit line hole to reduce the parasitic capacitance of the bit line.

On the other hand, another embodiment of the semiconductor device according to the present invention, the first and second active regions formed in the semiconductor substrate and insulated from each other by the isolation layer, formed in the first active region, the junction of the first active region A storage electrode contact plug electrically connected to a region, a bit line contact plug formed in the second active region and electrically connected to a junction region of the second active region, and the storage electrode contact plug and the bit line contact plug. And a spacer formed on the sidewall to insulate the storage electrode contact plug from the bit line contact plug and include an oxide layer.

Further, the spacer may include an oxide film and no nitride film, and the spacer may have a thickness thinner than that of the semiconductor substrate. In addition, the storage electrode contact plug preferably extends over the device isolation layer.

Another embodiment of the method of forming a semiconductor device according to the present invention includes forming a first active region and a second active region insulated from each other by an isolation layer on a semiconductor substrate, respectively in the first and second active regions. Forming first and second junction regions insulated from each other by an isolation layer; forming an insulating layer on the first and second active regions and the isolation layer; etching the insulation layer to etch the first and second junction regions. Forming a first trench of a continuous line pattern exposing a second junction region and the device isolation layer, forming a conductive layer filling the first trench, etching the conductive layer to etch the second junction region A storage in which the first conductive layer in a continuous line pattern is a separate island type and electrically connected to the first junction region while forming a second trench that exposes Forming an electrode contact plug, forming a spacer on a sidewall of the second trench, and forming a bitline contact plug to fill the second trench, wherein the spacer is the bitline contact plug and the storage electrode contact plug. Characterized in that it comprises the step of separating.

Furthermore, the spacer preferably includes an oxide film and no nitride film.

In the semiconductor device and the method of forming the same, the parasitic capacitance is reduced by forming the bit line spacer as an oxide film, and since the storage electrode contact is a line type, a patterning margin can be secured. Forming it provides an effect of reducing leakage current.

1 is a plan view of a semiconductor device according to the present invention; And,
2 to 9 are cross-sectional views showing a method of forming a semiconductor device according to the present invention.

Hereinafter, an embodiment of a semiconductor device and a method for forming the same according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a semiconductor device according to the present invention. Referring to FIG. 1, the semiconductor substrate 10 includes an active region 12 and an isolation layer 14 defining the active region 12. In addition, the gate 40 is formed in the horizontal direction so that the two gates 40 intersect in one active region 12, and the bit line 30 intersects one bit line 30 in one active region 12. 30) is formed in the longitudinal direction. In addition, a line type storage electrode contact 20 is provided in a space between adjacent gates 40 along a direction parallel to the gate 40.

In this case, the gate 40 is preferably a buried gate embedded in the lower portion of the semiconductor substrate 10. The bit line 30 is formed by a damascene process, and the storage electrode contacts 20 are preferably separated from each other in this damascene process.

2 to 9 are cross-sectional views illustrating a method of forming a semiconductor device according to the present invention, and FIGS. 2 to 9 (a) are cross-sectional views along the line AA ′ of FIG. 1, and (b) is a BB ′ of FIG. 1. Section along the line. Hereinafter, a method of forming a semiconductor device according to the present invention will be described with reference to these drawings.

Referring to FIG. 2, an isolation layer 14 defining an active region 12 is formed in the semiconductor substrate 10. In this step, it is preferable to use an STI (Shallow Trench Isolation) process in which a trench is formed in the semiconductor substrate 10 and the trench is embedded with an insulating film such as an oxide film to form the device isolation film 14. In this case, the device isolation layer 14 preferably includes an oxide film, and a liner layer 18 including an oxide film or a nitride film may be additionally formed on the interface between the substrate 10 and the device isolation film 14.

The buried gate 40 is formed on the semiconductor substrate 10. This process is performed by first forming a hard mask (not shown) defining a recessed region in the active region 12 and the device isolation layer 14 of the semiconductor substrate 10, and then using the hard mask to form the active region 12 and the device. The separator 14 is etched to form a recess 42 having a predetermined depth. Subsequently, a gate electrode 44 material is buried under the recess 42, and a capping layer 46 is buried therein to insulate the gate electrode 44. In this case, the gate electrode 44 may include a metal such as tungsten (W), titanium (Ti), or titanium nitride (TiN) or polysilicon, and the capping film 46 may include a nitride film or an oxide film (Oxide). It is preferable. Thus, when the buried gate is formed, parasitic capacitance generated between the bit line gates can be effectively reduced.

Subsequently, after removing the hard mask (not shown), a landing plug 16 is formed in the space where the hard mask is removed, and the landing plug 16 may include a conductive material such as polysilicon. In this way, an interlayer dielectric layer 22 (InterLayer Dielectric) is formed on the semiconductor substrate 10 on which the buried gate 40 and the landing plug 16 are formed, and the interlayer dielectric layer 22 preferably includes an oxide layer.

As shown in FIG. 3A, the interlayer insulating layer 22 is etched to form a storage node contact hole 24 exposing an upper portion of the landing plug 16. The storage electrode contact hole 24 is formed in a line type extending in the direction of the gate 40 as shown in FIG. 3B, which is more clearly shown in FIG. 1. As a result, the overlay margin is improved as compared with the conventional hole type storage electrode contact hole, and the problem that the contact with the lower landing plug 16 does not occur does not occur.

As illustrated in FIG. 4, a storage node contact plug 26 filling the storage electrode contact hole 24 is formed. The storage electrode contact plug 26 may include polysilicon and may be formed of polysilicon of a uniform material. However, as shown in FIG. 4, it is preferable to include the low concentration polysilicon 26b formed under the storage electrode contact hole 24 and the high concentration polysilicon 26a formed on the storage electrode contact hole 24. At this time, the concentration of high or low concentration refers to the concentration implanted with ions.

At this time, there are two methods for forming the polysilicon 26a, 26b having different concentrations. (i) first embedding the polysilicon layer in the storage electrode contact hole 24 and then performing a low concentration ion implantation process to form the whole polysilicon as a low concentration polysilicon layer, and then performing a high concentration ion implantation process to perform a low concentration polysilicon layer There is a method of forming the upper portion of the highly concentrated polysilicon layer. And (ii) embedding the polysilicon layer only in the lower portion of the storage electrode contact hole 24 and then implanting low-concentration ions to form the low-concentration polysilicon layer 26b first, and then embedding the polysilicon layer on the upper portion and then high-concentration ions. There is a method of forming a high concentration polysilicon layer 26a on the contact hole 24 by implantation.

When the storage electrode contact plug 26 is formed of polysilicon having different concentrations as described above, since the ion concentration of the lower portion (low concentration polysilicon layer) of the storage electrode contact plug 26 adjacent to the junction region is low, The effect of reducing leakage current such as GIDL (Gate Induced Drain Leakage) can be obtained. In addition, as described below, the oxide film thickness may be differently formed during the oxidation process of the bit line hole, thereby providing the effect of protecting the storage electrode contact plug 26 during the bit line conductive layer etch back process.

Referring to FIG. 5, an etching mask pattern 39 made of a material such as a nitride film is formed on the storage electrode contact plug 26 and the interlayer insulating layer 22, and the storage electrode contact plug 26 and the interlayer insulating layer are formed using the mask. The 22 is etched to form a bitline hole 32. As shown in FIG. 5B, the bit line hole 32 is formed to expose the landing plug 16 or the device isolation layer 14. The bit line hole 32 is for forming a bit line by a damascene process, and at the same time, two storage electrode contact plugs 26 are formed in one active region 12 by separating the storage electrode contact plugs 26 formed in a line type. ) Is formed (see FIG. 1).

Meanwhile, in the etching process of forming the bit line hole 32 exposing the landing plug 16 in FIG. 5B, the storage electrode contact plug 26 made of polysilicon is not sufficiently etched and the landing plug 16 is not etched. May remain on top. In this case, when the oxidation process is performed around the bit line hole 32, the remaining polysilicon is oxidized to SiO ₂ to remove the remaining polysilicon, and all of the storage electrode contact plugs 26 may be separated from each other. Will be.

As shown in FIG. 6, an oxidation process is performed on the bit line holes 32. The oxidation process may include a dry oxidation or a radical oxidation process, and when the dry oxidation process is performed, an oxide film 34 having a different thickness from the upper and lower portions as shown in FIG. ) Can be formed. This is because the oxidation proceeds more easily in the polysilicon 26a having a high ion concentration, and as shown in FIG. 6B, a thicker oxide film 34 is formed on the side of the high concentration polysilicon 26a.

The oxide film 34 formed by this oxidation process insulates the bit lines 30 (see FIG. 9) and the storage electrode contact plugs 26 from each other, insulates the two adjacent storage electrode contact plugs 26 from each other, and stores them. It may serve to insulate the electrode contact plug 26 and the landing plug 16. In addition, the nitride film, which is formed as a spacer on the side of the bit line, may serve to protect the side of the bit line, and the oxide layer 34 as the spacer has better film quality than the nitride layer, thereby reducing the parasitic capacitance of the bit line. To provide.

Referring to FIG. 7, before forming the bit line, the oxide film 34 under the bit line hole 32 is removed by an etch back process to expose the landing plug 16.

As shown in FIG. 8, a barrier metal layer 36 and a bit line conductive layer 37 are formed in the bit line hole 32. The barrier metal layer 36 includes a structure in which titanium (Ti) and a titanium nitride film (TiN) are stacked, and the bit line conductive layer 37 includes tungsten (W). In the process of forming the bit line conductive layer 37, the bit line conductive layer 27 is deposited to fill the bit line hole 32, and then removed by an etch back process to remove only the bit line hole 32. The bit line conductive layer 27 remains. At this time, since the high concentration polysilicon layer 26a having the thick oxide layer 34 is present on the upper portion, the storage electrode contact plug 26 is not etched together in the etch back process of removing the upper portion of the bit line conductive layer 27. Do not. That is, the oxide film 34 serves to protect the side of the storage electrode contact plug 26.

Referring to FIG. 9, a bit line hard mask 38 is formed on the bit line conductive layer 27 in the bit line hole 32 to protect the top of the bit line conductive layer 27, and the bit line hard The mask 38 preferably includes a nitride film. The semiconductor device according to the present invention manufactured by such a method has a structure in which an oxide film 34 is formed like a spacer on the sidewall of the bit line hole 32.

Subsequently, although not shown, a capacitor is formed on the storage electrode contact plug 26 separated by the bit line 30 and a metal wiring is formed to form a semiconductor device.

In the semiconductor device of the present invention formed by the above method, the parasitic capacitance is reduced by forming the bit line spacers as the oxide film, and since the storage electrode contact is a line type, a patterning margin can be secured. By forming it, it is possible to provide the effect of reducing the leakage current.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

10 substrate 12 active region
14 device isolation layer 16 landing plug
18: liner film 20: storage electrode contact
22: interlayer insulating film 24: storage electrode contact hole
26: storage electrode contact plug 30: bit line
32: bit line hole 34: oxide film
26 barrier metal 37 bit line conductive layer
38: hard mask 39: etching mask
40: buried gate 42: recess
44 gate electrode 46 capping film

Claims (6)

First and second active regions formed on the semiconductor substrate and insulated from each other by an isolation layer;
A storage electrode contact plug formed in the first active region and electrically connected to the junction region of the first active region;
A bit line contact plug formed in the second active region and electrically connected to a junction region of the second active region; And
A spacer formed on sidewalls of the storage electrode contact plug and the bit line contact plug to insulate the storage electrode contact plug from the bit line contact plug and include an oxide layer
A semiconductor device comprising a. The method according to claim 1,
And the spacer includes an oxide film and no nitride film. The method according to claim 1,
And the spacer has a thickness thinner than that of the semiconductor substrate. The method according to claim 1,
The storage electrode contact plug extends over the device isolation layer. Forming a first active region and a second active region insulated from each other by an isolation layer in the semiconductor substrate;
Forming first and second junction regions in the first and second active regions, respectively, insulated from each other by an isolation layer;
Forming an insulating layer on the first and second active regions and the device isolation layer;
Etching the insulating layer to form a first trench of a continuous line pattern exposing the first and second junction regions and the device isolation layer;
Forming a conductive layer filling the first trench;
A storage electrode contact plug for etching the conductive layer to form a second trench exposing the second junction region, wherein the first conductive layer in a continuous line pattern is a separate island type and electrically connected to the first junction region. Forming to;
Forming spacers on sidewalls of the second trenches; And
Forming a bit line contact plug to fill the second trench so that the spacer separates the bit line contact plug from the storage electrode contact plug.
Forming method of a semiconductor device comprising a. The method according to claim 5,
And the spacer comprises an oxide film and no nitride film.

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