KR20160008375A - Semiconductor having vertical channel - Google Patents

Abstract

The present technology relates to a semiconductor device where the size of an area touching an active pillar changes according to the region of a gate. The semiconductor device may include an active pillar including a vertical channel, a gate which is located on the lateral surface of the active pillar and has a first region touching the first sidewall of the active pillar and a second region touching the sidewalls of the active pillar, and a bit line located under the gate.

Description

[0001] Semiconductor having vertical channel [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a vertical channel, and more particularly, to a semiconductor device having a different area in contact with an active pillar depending on a region of a gate.

Recently, although the demand for increasing the capacity of semiconductor devices has been increasing, the capacity increase of the DRAM device is also limited due to the increase of the chip size. As the chip size increases, the number of chips per wafer decreases and the productivity of the device decreases. Therefore, in recent years, efforts have been made to change the cell layout to reduce the cell area, and to accumulate more memory cells on a single wafer.

As a semiconductor device becomes more highly integrated, the semiconductor chip size decreases and the size of a semiconductor device formed in the chip also decreases.

However, as the size of the transistor decreases, the gate induced drain leakage (GIDL) generated in the region where the source and drain regions overlap with the gate electrode is rapidly increased.

Embodiments of the present invention provide a semiconductor device capable of improving the controllability of a gate while minimizing GIDL by improving the structure of a buried gate.

A semiconductor device according to an embodiment of the present invention includes an active pillar including a vertical channel, the pillar being located on a side surface of the active pillar, wherein a first region contacts only one sidewall of the active pillar and a second region contacts a plurality of sidewalls And a bit line located below the gate.

A semiconductor device according to another embodiment of the present invention is defined by a device isolation film and includes active regions whose upper portion is divided into a first active pillar and a second active pillar, the first active pillars of the active pillars and the second active pillars, The first active pillars having a first gate contacting one sidewall of the first active pillars and the remaining region having a first gate contacting a plurality of sidewalls of the first active pillars, The first region being in contact with only one side of the second active pillars and the second region being in contact with the plurality of sidewalls of the second active pillars, 2 gate and may include a bit line commonly connected to the first active pillar and the second active pillar of each active region The.

Embodiments of the present invention can provide a semiconductor device capable of improving the controllability of the gate while minimizing the GIDL by improving the structure of the buried gate.

1 is a plan view showing a structure of a semiconductor device according to an embodiment of the present invention;
2 is a cross-sectional view showing a cross-sectional view taken along line AA 'and B-B' in FIG. 1;
FIGS. 3 to 15 are views showing the processes of forming the structures of FIGS. 1 and 2. FIG.
16 is a sectional view showing the structure of a semiconductor device according to another embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view showing a structure of a semiconductor device according to an embodiment of the present invention. FIG. 2A is a cross-sectional view showing a section taken along line A-A 'in FIG. 1, and FIG. 2B is a sectional view showing a section taken along line B-B' in FIG.

Referring to FIGS. 1, 2A and 2B, an active region 102 formed by etching a semiconductor substrate 100 is defined by line type device isolation films 104a and 104b, and buried bit lines BBL Bit Line). The active regions 102 sharing the buried gate BG are arranged in a line in a line along the direction of the embedding gate BG.

The upper portion of each active region 102 is separated into a pair of active pillars 108a, 108b that include a vertical channel region (indicated by an arrow in FIG. 2B). The lower portions of the active pillars 108a and 108b are connected to the buried bit line BBL.

The buried bit line BBL proceeds in a direction perpendicular to the traveling direction of the buried gate BG and passes between the pair of active pillars 108a and 108b. A bit line contact BLC is formed on both sides of the buried bit line BBL. That is, the buried bit line BBL has a BSC (Both Side Contact) structure connected in common to the active pillars 108a and 108b on both sides. Wherein the bit line contact (BLC) comprises a silicide film.

The buried bit line BBL is located under the buried gate BG and is buried in the active region 102. The buried bit line BBL includes a metal layer (e.g., tungsten). By placing the bit line BBL below the buried gate BG while being buried in the active area 102, the distance between the bit line BBL and the storage node is sufficiently large, It is possible to reduce parasitic capacitance.

In the active region 102, a bulb-shaped insulating film 106 is formed under the buried bit line BBL. The insulating film 106 is formed so as to surround the lower portion of the buried bit line BBL, thereby preventing the parasitic capacitance between the bit line BBL and the semiconductor substrate 100 from being generated. At this time, the insulating film 106 includes an oxide film.

The pair of buried gates BG separated by the insulating film 112 proceeds in the same direction as the device isolation film 104b and passes between the active pillars 108a and 108b. Particularly, in this embodiment, the buried gate BG has a different area in contact with the active pillars 108a and 108b depending on the positions of the active pillars 108a and 108b (positions of the vertical channel regions). For example, the embedding gate BG includes an upper gate BG_U, a middle gate BG_M, and a low gate BG_L. At this time, the upper gate BG_U contacts only one side wall of the active pillars 108a and 108b, and the middle gate BG_M and the lower gate BG_L enclose the three side walls of the active pillars 108a and 108b. Since the upper gate BG_U contacts only one side wall of the active pillars 108a and 108b, gate induced drain leakage (GIDL) can be minimized. In addition, since the middle gate BG_M and the bottom gate BG_L enclose the three side walls of the active pillars 108a and 108b, the operation current Iop can be sufficiently secured.

Further, the middle gate BG_M may have a recess gate structure in which a part of the gate is embedded in the active pillars 108a and 108b. That is, the region where the middle gate BG_M is formed in the active pillars 108a and 108b is recessed to a certain depth, and the gate material is buried in the recessed region. Thus, the problem of the short channel can be also improved in this embodiment.

In FIG. 1, only buried gates formed between the insulating films 110 among the entire buried gates are shown for convenience of explanation, and insulating films formed on the buried gates BG are not shown.

FIGS. 3 to 15 are views showing the processes of forming the structures of FIGS. 1 and 2. FIG. In each drawing, (a) is a plan view, and (b) and (c) are cross-sectional views each showing a cross-sectional view taken along line A-A 'and B-B' in FIG.

Referring to FIG. 3, a pad oxide layer (not shown) and a pad nitride layer (not shown) are formed on a semiconductor substrate 200, and a hard mask layer (not shown) is formed on the pad nitride layer. At this time, the hard mask layer includes a nitride film.

Next, an ISO mask pattern (not shown) for defining a line type active region is formed on the hard mask layer, and then the hard mask layer is etched using the etch mask to form the hard mask pattern 202. At this time, the ISO mask pattern can be formed through an SPT (Spacer Pattern Technology) process. Then, a device isolation trench (not shown) is formed by successively etching the pad oxide film, the pad nitride film, and the semiconductor substrate 200 using the hard mask pattern 202 as an etching mask to define a line-type active region 204 . At this time, the active region 204 may be defined to intersect obliquely with bit lines and gates (word lines) formed in a subsequent process.

Next, a sidewall insulation film (not shown) is formed on the sidewall of the element isolation trench. Such a sidewall insulating film includes an oxide film (wall oxide). At this time, the sidewall insulating film can be formed by depositing an oxide film material on the sidewalls of the device isolation trench or by oxidizing the sidewalls of the device isolation trench through a dry or wet oxidation process.

Next, after an element isolation insulating film is formed so as to fill the trench for element isolation, the element isolation insulating film is flattened until the hard mask pattern 202 is exposed, thereby forming an element isolation film ( 206 are formed. At this time, the device isolation layer 206 includes an SOD (Spin On Dielectric) material or an HDP (High Density Plasma) oxide film having excellent gap-fill characteristics.

4, the hard mask pattern 202, the active region 204 and the element isolation film 206 are etched using an ISO cut mask for cutting (separating) the active region 204 by a predetermined length unit Thereby forming a trench 208 for element isolation. At this time, the element isolation trenches 208 are formed in a line type that proceeds in the same direction as the embedding gate formed in the subsequent process. Subsequently, a sidewall insulation film (not shown) is formed on the sidewall of the element isolation trench 208. Such a sidewall insulating film includes an oxide film (wall oxide).

Next, an isolation film is formed so that the element isolation trenches 208 are buried and then planarized to form an element isolation film 210 that separates the active regions 204 by a predetermined length unit. That is, an island-type active region 204 'defined by the element isolation films 206 and 210 is formed. At this time, the device isolation layer 210 includes an SOD (Spin On Dielectric) material or an HDP (High Density Plasma) oxide film having excellent gap-fill characteristics.

Referring to FIG. 5, the hard mask pattern 202, the active region 204 ', and the element isolation films 206 and 210 are etched using a mask (bit line mask) defining a bit line region, Trenches 212 are formed. The bit line trench 212 separates the upper portion of the active region 204 'into a pair of active pillars 214a and 214b.

Next, spacers 216 are formed on the sidewalls of the bit line trenches 212. For example, the spacers 216 may be formed on the sidewalls of the trenches 212 by forming an insulating film for the spacers on the sidewalls and bottom surfaces of the bit line trenches 212 and then etching them back. At this time, the spacer 216 includes a nitride film.

Referring to FIG. 6, the active region 204 'exposed on the bottom surface of the bit line trench 212 is secondarily etched in the form of a bulb using the spacer 216 as a barrier film to form a trench 218 ).

Next, referring to FIG. 7, after the spacer 216 is removed, for example, through a strip process, an insulating film 220 is formed so that the trench 218 is buried. At this time, the insulating film 220 includes an oxide film.

After the annealing process is performed on the insulating layer 220, the insulating layer 220 is etched until the hard mask pattern 202 is exposed.

Next, referring to FIG. 8, a trench (not shown) is formed by etching the insulating layer 220 to a predetermined depth, and spacers 222 are formed on the sidewalls of the trenches.

Subsequently, the trench 224 is formed by using the spacer 222 as a barrier film to secondarily etch the bottom surface of the trench. The silicon in the lower portion of the active pillar 214 is exposed by the trench 224.

Referring next to FIG. 9, a bit line contact 226 is formed on the sidewalls of the exposed active pillars 214a and 214b. At this point, the bit line contact 226 may comprise a silicide film. For example, a cobalt (Co) film is formed on the sidewall of the trench 224 and then a thermal process is performed to selectively transform the cobalt film contacted with the active pillars 214a and 214b into a cobalt silicide (CoSix) The membrane is removed through a cleaning process. Such a silicide film may be formed of a titanium silicide (TiSix) film, a tungsten silicide (WSix) film, and a nickel silicide (NiSix) film.

Subsequently, a metal layer (not shown) is formed to fill the trench 224, and the metal layer is etched back to form a buried bit line 228 under the trench 224. At this time, the metal layer includes tungsten, and the bottom of the buried bit line 228 is surrounded by the insulating layer 220 in the form of a bulb.

Referring to FIG. 10, after the spacer 222 is removed, a capping insulating layer 230 is formed on the buried bit line 228 so that the trench 224 is buried, and then the buried bit line 228 is planarized. At this time, the capping insulating film 230 includes an oxide film.

Referring to FIG. 11, an upper surface of the element isolation films 206 and 210 and the insulating film 230 is etched to a predetermined depth, and then an insulating film 232 is formed. At this time, the insulating film 232 is formed to the upper portion of the buried gate to be formed in the subsequent process, that is, the region corresponding to the upper gate BG_U in FIG. The insulating film 232 includes a nitride film.

Next, the hard mask pattern 202, the element isolation films 206 and 210, the active pillars 214a and 214b, and the capping insulating film 230 are etched using the gate mask defining the buried gate region to form the gate trench 234 ). At this time, the trench 234 is formed so that a part of the insulating film 230 remains on the buried bit line 228.

An insulating film 236 is formed to fill the gate trench 234 and then the insulating film 236 is etched back to leave the insulating film 236 only under the gate trench 234. At this time, the insulating film 236 is left by the height of the middle gate BG_M in FIG. The insulating film 236 includes an oxide film.

Referring to FIG. 12, a spacer 238 is formed on a sidewall of the trench 234, and then the insulating film 236 is etched to a predetermined depth to expose side walls of the active pillars 214a and 214b.

Subsequently, the sidewalls of the exposed active pillars 214a and 214b are etched in a bulb shape to form the recess 240.

Next, referring to FIG. 13, the insulating film 236 and the spacers 238 are removed. next, ? The device isolation film 206 is etched through a wetning process to expose the sidewalls of the active pillars 214a and 214b. That is, the trench 234 is etched to expose the sidewalls of the active pillars 214a and 214b. As a result, the side walls of the active pillars 214a and 214b corresponding to the regions where the middle gate BG_M and the low gate BG_L are formed in FIG. 2 are exposed.

Next, a gate insulating film 242 is formed on the exposed side walls of the active pillars 214a and 214b. For example, the side walls of the active pillars 214a and 214b exposed by the trenches 234 are oxidized through the oxidation process to form the gate insulating film 242.

Referring next to FIG. 14, after embedding the gate conductor 244 so that the trench 234 is buried, the gate conductor 244 is etched back. At this time, the gate conductive material may have a structure in which a barrier metal (TI, TIN) and a metal (e.g., tungsten) are stacked.

Then, an insulating film 246 is formed on the gate conductive material 244 so that the trench 234 is buried. At this time, the insulating film 246 includes an oxide film.

15, a center portion of the insulating film 246 and the gate conductive material 244 is etched using the line-shaped cut mast to separate the gate conductive material 244, thereby forming the buried gate 248 . At this time, the embedding gate 248 includes a low gate 248_L, a middle gate 248_M, and an upper gate 248_U. The upper gate 248_U contacts only one sidewall of the active pillars 214a and 214b and the middle gate BG_M and the lower gate BG_L enclose the three sidewalls of the active pillars 214a and 214b. Furthermore, the middle gate 248_M has a recess gate structure in which a part of the gate is embedded in the active pillars 214a and 214b.

Then, a capping insulating film 250 is formed to fill the trench between the buried gates 248.

16 is a cross-sectional view showing the structure of a semiconductor device according to another embodiment of the present invention.

2, only the middle gate BG_M 'in the buried gate BG' surrounds the three sidewalls of the active pillars 108a and 108b and the upper gate BG_U 'and the lower gate BG_L' 'Are formed so as to be in contact with only one side wall of the active pillars 108a and 108b.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It should be regarded as belonging to the claims.

For example, the gate structure described above can be applied to an active filament having a 4F2 structure.

100: semiconductor substrate 102: active
104a and 104b: element isolation films 106, 110 and 112:
108a and 108b:
BG: Embedded gate BG_U: Upper gate
BG_M: middle gate BG_L: bottom gate
BBL: buried bit line

Claims (17)

An active pillar comprising a vertical channel region;
A gate disposed on a side surface of the active pillar, wherein the first region contacts only one sidewall of the active pillar and the second region contacts a plurality of sidewalls of the active pillar; And
And a bit line located below said gate. 2. The device of claim 1, wherein the gate
An upper gate contacting only one side wall of the active pillars;
A middle gate located below the top gate and in contact with three sidewalls of the active pillars; And
And a bottom gate located below the middle gate and in contact with three sidewalls of the active pillars. 3. The method of claim 2, wherein the middle gate
And a recess gate structure in which a part of the active region is buried in the active pillar. In the second aspect,
Wherein the upper gate, the middle gate, and the lower gate are integrally formed. 2. The device of claim 1, wherein the gate
An upper gate contacting only one side wall of the active pillars;
A middle gate located below the top gate and in contact with three sidewalls of the active pillars; And
And a lower gate located below the middle gate and contacting only one sidewall of the active pillar. 6. The method of claim 5, wherein the middle gate
And a recess gate structure in which a part of the active region is buried in the active pillar. 6. The method of claim 5,
Wherein the upper gate, the middle gate, and the lower gate are integrally formed. The method according to claim 1,
Further comprising an insulating film having a bulb shape and surrounding a lower portion of the bit line. Active regions defined by a device isolation layer and separated by a first active pillar and a second active pillar;
The first active pillar and the second active pillar of the active pillars, wherein a portion of the first active pillar is in contact with only one sidewall of the first active pillar and the remaining region is in contact with a plurality of sidewalls of the first active pillar, gate;
Wherein the first active pillars pass between the first active pillars and the second active pillars of the active pillars and the first region contacts only one side of the second active pillars and the second region contacts the plurality of sidewalls of the second active pillars A second gate; And
And a bit line located below said first gate and said second gate and connected in common to said first active pillar and said second active pillar in each active region. 10. The method of claim 9,
Wherein the first gate and the second gate are arranged in parallel in a line along the traveling direction of the first gate and the second gate. 10. The method of claim 9, wherein the first gate and the second gate
An upper gate contacting only one sidewall of the corresponding active pillar;
A middle gate located below the top gate and in contact with three sidewalls of the active pillars; And
And a bottom gate located below the middle gate and in contact with three sidewalls of the active pillars. 12. The method of claim 11, wherein the middle gate
And a recess gate structure in which a part of the active region is buried in the active pillar. 12. The method of claim 11,
Wherein the upper gate, the middle gate, and the lower gate are integrally formed. 10. The method of claim 9, wherein the first gate and the second gate
An upper gate contacting only one sidewall of the corresponding active pillar;
A middle gate located below the top gate and in contact with three sidewalls of the active pillars; And
And a lower gate located below the middle gate and contacting only one sidewall of the active pillar. 15. The method of claim 14, wherein the middle gate
And a recess gate structure in which a part of the active region is buried in the active pillar. 15. The method of claim 14,
Wherein the upper gate, the middle gate, and the lower gate are integrally formed. 10. The method of claim 9,
Further comprising an insulating film having a bulb shape and surrounding a lower portion of the bit line in the active region.

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