KR20120042420A - Therr dimensional semiconductor memory devices - Google Patents

Abstract

PURPOSE: A three-dimensional semiconductor memory device is provided to minimize resistance of a common source area by forming a strapping contact plug in order to be connected to the common source area. CONSTITUTION: A plurality of laminated structures(170) is located on a substrate. Each laminated structure includes a repetitively laminated gate pattern and an insulating pattern. A plurality of vertical type active patterns(130) respectively penetrates the laminated structures. Common source areas(150) are formed inside of the substrate between the laminated structures. A strapping contact plug(180) is electrically connected to the common source area.

Description

3D Semiconductor Memory Device {THERR DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES}

The present invention relates to a semiconductor device, and more particularly to a three-dimensional semiconductor memory device.

Due to their small size, versatility and / or low manufacturing cost, semiconductor devices are becoming an important element in the electronics industry. As the electronics industry develops, there is an increasing demand for better performance and / or lower cost semiconductor devices. In order to meet these requirements, the trend toward higher integration of semiconductor devices is intensifying. In particular, high integration of semiconductor memory devices for storing logic data is further intensified.

The degree of integration of a conventional two-dimensional semiconductor memory device may act as a main determinant of the planar area occupied by the unit memory cells. As a result, the degree of integration of the two-dimensional semiconductor memory device may be greatly influenced by the level of technology for forming a fine pattern. However, the technology of forming fine patterns is approaching the limit, and also, there are problems such as an increase in the manufacturing cost of semiconductor memory devices due to the need for expensive equipment.

In order to overcome these limitations, a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells has been proposed. However, the three-dimensional semiconductor memory device may cause problems such as deterioration in reliability due to its structural shape.

One object of the present invention is to provide a three-dimensional semiconductor memory device having excellent reliability.

Another object of the present invention is to provide a three-dimensional semiconductor memory device optimized for high integration.

Provided are a three-dimensional semiconductor memory device for solving the above technical problems. A three-dimensional semiconductor memory device according to an embodiment of the present invention is a stacked structure disposed on a substrate and extending in a first direction, the stacked structure includes gate patterns and insulating patterns stacked alternately and repeatedly The stack-structure comprises a first portion and a second portion, the second portion of the stack-structure having a width less than the first portion in a second direction perpendicular to the first direction; A plurality of vertical active patterns penetrating the stack-structure; A multilayer dielectric film interposed between sidewalls of each vertical active pattern and each gate pattern; A common source region formed in the substrate on one side of the stack-structure; And a strapping contact plug disposed on the common source region. In this case, the strapping contact plug may be located next to the second portion of the stack-structure.

According to one embodiment, the first portion of the laminate-structure may have a first sidewall and a second sidewall facing each other and extending side by side in the first direction, the second portion of the laminate-structure facing each other. It may have a first side wall and a second side wall. The first sidewall of the second portion of the stack-structure may be laterally recessed relative to the first sidewall of the first portion. The strapping contact plug may be located next to the first sidewall of the second portion.

According to one embodiment, the second sidewall of the first portion and the second sidewall of the second portion may form a flat sidewall extending substantially in the first direction.

In example embodiments, the second sidewall of the second portion may be laterally recessed with respect to the second sidewall of the first portion.

In example embodiments, the common source region may extend in the first direction. The common source region may include a non-landing portion located next to the first portion of the stack-structure and a landing portion located next to the second portion of the stack-structure. . Preferably, the width of the landing part in the second direction is larger than the width of the non-landing part in the second direction.

In example embodiments, the device may further include an isolation pattern disposed on the common source region. The strapping contact plug may be electrically connected to the common source region through the device isolation pattern.

According to one embodiment, the device comprises a bit line electrically connected to the top of the vertical active pattern; And a strapping line electrically connected to an upper surface of the strapping contact plug.

In example embodiments, the bit line and the strapping line may be positioned at substantially the same level from an upper surface of the substrate. In this case, the bit line and the strapping line may extend side by side in the second direction.

In example embodiments, at least a portion of the multilayer dielectric layer may extend laterally to cover top and bottom surfaces of the gate patterns.

A three-dimensional semiconductor memory device according to another embodiment of the present invention includes a plurality of stacked-structures disposed on a substrate and extending side by side in a first direction, each stacked-structure being alternately and repeatedly stacked gate patterns and An insulating pattern, wherein the plurality of stack-structures are arranged at the same pitch in a second direction perpendicular to the first direction; A plurality of vertical active patterns penetrating the respective stacked-structures; A multilayer dielectric film interposed between sidewalls of each vertical active pattern and each gate pattern; A plurality of common source regions formed in the substrate between the stack-structures and extending side by side in the first direction; And a strapping contact plug electrically connected to any one of the common source regions. At least one of the pair of stack-structures adjacent to both sides of the strapping contact plug may include a first portion and a second portion having a smaller width in the second direction than the first portion. The strapping contact plug may be located next to the second portion.

According to an embodiment, the common source region electrically connected to the strapping contact plug may include a non-landing portion and a landing portion. The landing portion may have a larger width than the non-landing portion in the second direction, and the landing portion and the second portion of the stack-structure may be arranged in the second direction.

According to one embodiment, the strapping contact plug may be provided in plurality. The plurality of strapping contact plugs may be electrically connected to the common source regions, respectively. Each of the stack-structures may include the first portion and the second portion, wherein the strapping contact plugs and the second portions of the stack-structures are alternately and repeatedly arranged along the second direction. Can be.

In an embodiment, the device may include: a connection doped region formed in the substrate and extending in the second direction to connect the common source regions; And a strapping line electrically connected to an upper surface of the strapping contact plug and extending in the second direction. The number of the strapping contact plugs below the strapping line may be smaller than the number of the common source regions.

According to the three-dimensional semiconductor memory element described above, a strapping contact plug is in contact with the common source region. As a result, the resistance of the common source region can be minimized. The strapping contact plug is also located next to the second portion of the stack-structure having a relatively small width. Due to the second portion of the laminate structure, a planar area of a portion of the common source region in contact with the strapping contact plug can be sufficiently secured within a limited area. As a result, a three-dimensional semiconductor memory device having excellent reliability and optimized for high integration can be realized.

1A is a plan view showing a three-dimensional semiconductor memory device according to an embodiment of the present invention.
FIG. 1B is an enlarged plan view of a portion of the stack-structure of FIG. 1A. FIG.
1C is a cross-sectional view taken along II ′ and II-II ′ of FIG. 1A;
FIG. 2A is a cross-sectional view taken along II ′ and II-II ′ of FIG. 1A to illustrate a three-dimensional semiconductor memory device according to another embodiment of the present invention; FIG.
FIG. 2B is an enlarged view of a portion A of FIG. 2A; FIG.
3A is a plan view showing a three-dimensional semiconductor memory device according to still another embodiment of the present invention.
3B is an enlarged plan view of a portion of the gate stack-structure of FIG. 3A.
4A is a plan view showing a three-dimensional semiconductor memory device according to still another embodiment of the present invention.
4B is a cross sectional view taken along III-III ′ and IV-IV ′ of FIG. 4A;
5A through 5F are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 1A to illustrate a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention.
6A and 6B are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 1A to illustrate a method of manufacturing a three-dimensional semiconductor memory device according to another embodiment of the present invention.
FIG. 7 is a cross-sectional view taken along III-III 'and IV-IV' of FIG. 4A to explain a method of manufacturing a three-dimensional semiconductor memory device according to another embodiment of the present invention;
8 is a block diagram schematically illustrating an example of an electronic system including a three-dimensional semiconductor memory device based on the technical idea of the present invention.
9 is a block diagram schematically illustrating an example of a memory card including a three-dimensional semiconductor memory device based on the technical idea of the present invention;

Objects, other objects, features and advantages of the present invention will be readily understood through the following preferred embodiments associated with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate or a third film between them. In addition, in the drawings, sizes, thicknesses, etc. of components are exaggerated for clarity. It should also be understood that although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., It should not be. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. The expression 'and / or' is used herein to include at least one of the components listed before and after. Portions denoted by like reference numerals denote like elements throughout the specification.

FIG. 1A is a plan view illustrating a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention, FIG. 1B is an enlarged plan view of a part of the stack-structure of FIG. 1A, and FIG. 1C is II ′ and II-II of FIG. 1A. It is a cross section taken along.

1A and 1C, a plurality of stack-structures 170 may be disposed on a semiconductor substrate 100 (hereinafter, referred to as a substrate). As disclosed in FIG. 1A, the plurality of stack-structures 170 may extend side by side in a first direction. The first direction may be parallel to an upper surface of the substrate 100. The first direction may correspond to the x-axis direction in FIG. 1A. The substrate 100 may be doped with a dopant of a first conductivity type.

Each stack-structure 170 may include gate patterns GSG, CG, and SSG and insulating patterns 110a that are alternately and repeatedly stacked. The gate patterns GSG, CG, and SSG in each stack structure 170 may include at least one ground select gate pattern GSG, and a plurality of cell gate patterns stacked on the ground select gate pattern GSG in turn. At least one layer of the string selection gate pattern SSG stacked on the cell CG and the uppermost cell gate pattern. According to an embodiment, as shown in FIG. 1C, a plurality of ground select gate patterns GSG may be stacked between the lowermost cell gate pattern and the substrate 100. In addition, a plurality of string select gate patterns SSG may be stacked on the uppermost cell gate pattern. However, the present invention is not limited thereto. Each stack-structure 170 may include one ground select gate pattern GSG and one string select gate pattern SSG.

The thicknesses of the insulating patterns 110a in the stack-structure 170 may be adjusted for characteristics required by the device. For example, the insulating pattern between the lowermost cell gate pattern and the ground select gate pattern GSG may be thicker than the insulating patterns between the cell gate patterns CG. Similarly, the insulating pattern between the uppermost cell gate pattern and the string select gate pattern SSG may also be thicker than the insulating patterns between the cell gate patterns CG. However, the present invention is not limited thereto. Thicknesses of the insulating patterns 110a may be implemented in various forms.

The insulating patterns 110a may include an oxide. The gate patterns GSG, CG, and SSG may include a conductive material. For example, the gate patterns GSG, CG, and SSG may be formed of doped semiconductors (ex, doped silicon, etc.), metals (ex, tungsten, copper, aluminum, etc.), conductive metal nitrides (ex, titanium nitride, tantalum nitride, etc.). Etc.) or transition metals (ex, titanium, tantalum, etc.) and the like.

A plurality of vertical active patterns 130 may penetrate each of the stack-structures 170. The vertical active patterns 130 may be in contact with the substrate 100. The vertical active pattern 130 may include a vertical semiconductor pattern 120 having a five shape or a macaroni shape. The vertical semiconductor pattern 120 may be filled by a filling dielectric pattern 125. The vertical active pattern 130 may further include a capping semiconductor pattern 127 disposed on the charge dielectric pattern 125 and the vertical semiconductor pattern 120. The vertical and capping semiconductor patterns 120 and 127 may include the same semiconductor element as the substrate 100. For example, when the substrate 100 is a silicon substrate, the vertical and capping semiconductor patterns 120 and 127 may include silicon. The vertical semiconductor pattern 120 may be doped with the same type of dopant as the substrate 100 or may be undoped. A drain region may be formed in at least a portion of the capping semiconductor pattern 127. The drain region may be doped with a dopant of a second conductivity type.

The multilayer dielectric layer 160 may be interposed between sidewalls of the vertical active patterns 130 and the gate patterns GSG, CG, and SSG. The multilayer dielectric layer 160 may include a tunnel dielectric layer, a charge storage layer, and a blocking dielectric layer. The tunnel dielectric layer may be adjacent to the sidewall of the vertical active pattern 130, and the blocking dielectric layer may be adjacent to each of the gate patterns GSG, CG, and SSG. The charge storage layer may be interposed between the tunnel dielectric layer and the blocking dielectric layer. The tunnel dielectric layer may include an oxide and / or an oxynitride. The blocking dielectric layer may include a high dielectric layer (eg, a metal oxide layer such as a hafnium oxide layer and / or an aluminum oxide layer) having a higher dielectric constant than the tunnel dielectric layer. In addition, the blocking dielectric layer may further include a barrier dielectric layer having a higher energy band gap than the high dielectric layer. The barrier dielectric layer may be interposed between the high dielectric layer and the charge storage layer. The charge storage layer may include a dielectric material having traps capable of storing charge. For example, the charge storage layer may include an oxide and / or a metal oxide. The multilayer dielectric layer 160 between the cell gate pattern CG and the vertical active pattern 130 may be used as a data storage element for storing logic data. The multilayer dielectric layer 160 between the selection gate patterns GSG and SSG and the vertical active pattern 130 may be used as a gate dielectric layer of the selection transistors. At least a portion of the multilayer dielectric layer 160 may extend horizontally to cover lower and upper surfaces of the gate patterns GSG, CG, and SSG. As illustrated in FIG. 1C, according to one embodiment, the entire tunnel dielectric layer, the charge storage layer, and the blocking dielectric layer in the multilayer dielectric layer 160 extend horizontally to form lower portions of the gate patterns GSG, CG, and SSG. It can cover the surface and the top surface.

Each vertical active pattern 130 may implement one vertical cell string. The vertical cell string may include cell transistors connected and stacked in series with each other. In addition, the vertical cell string may include at least one ground select transistor, a plurality of cell transistors, and at least one string select transistor that are sequentially stacked. The ground select transistor, cell transistors, and string select transistors may be connected in series with each other. The cell transistor may be defined at an intersection point of each vertical active pattern 130 and each cell gate pattern CG. The ground select transistor may be defined at an intersection point of each of the vertical active pattern 130 and the ground select gate pattern GSG, and the string select transistor may include the vertical active pattern 130 and the string select. It may be defined at the intersection of the gate pattern SSG. The ground select, cell and string select transistors included in the vertical cell string may include vertical channel regions defined on sidewalls of the vertical active pattern 130. The ground select transistor including the lowermost ground select gate pattern GSG may further include a horizontal channel region defined under the ground select gate pattern GSG.

A buffer dielectric pattern 103a may be disposed between each of the stack-structures 170 and the substrate 100. In this case, the vertical active pattern 130 may extend downward to penetrate the buffer dielectric layer 103. Thus, the vertical active pattern 130 may be in contact with the substrate 130. The buffer dielectric pattern 103a may include an oxide. Capping dielectric patterns 135 may be disposed on each of the stack-structures 170 and vertical active patterns 130 penetrating through the stack-structures. Both sidewalls of the capping dielectric pattern 135 may be aligned with both sidewalls of the stack-structure 170 below. The capping dielectric pattern 135 may include an oxide, nitride, and / or oxynitride.

Common source regions 150 may be formed in the substrate 100 between the stack-structures 170. That is, the common source regions 150 may be disposed in the substrate 100 adjacent to both sides of each stack-structure 170. The common source regions 150 may extend side by side in the first direction. The common source regions 150 may be spaced apart from each other in a second direction perpendicular to the first direction. The second direction may be parallel to an upper surface of the substrate 100. The second direction may correspond to the y-axis direction of FIG. 1A. The stack-structures 170 and the common source regions 150 may be alternately and repeatedly arranged in the second direction. The common source regions 150 may be doped with dopants of the second conductivity type. That is, the common source regions 150 may be doped with a different type of dopant from the substrate 100 and may be doped with the same dopant as the drain region.

Device isolation patterns 177 may fill the spaces between the stacked structures 170, respectively. That is, each device isolation pattern 177 may be disposed on each common source region 150. An upper surface of the device isolation pattern 177 may be substantially coplanar with an upper surface of the capping dielectric pattern 135. The device isolation pattern 177 may include an oxide, nitride, and / or oxynitride.

A strapping contact plug 180 may be electrically connected to the common source region 150 through the device isolation pattern 177. In this case, at least one of the pair of stacked-structures 170 adjacent to both sides of the strapping contact plug 180 may have a first portion and a second portion having a smaller width than the first portion. It may include. This will be described in more detail with reference to FIG. 1B. FIG. 1B is an enlarged plan view of the stack-structure 170 and the common source region 150 adjacent thereto in FIG. 1A. 1B omits the bit line 190a and the strapping line 190b of FIG. 1A for convenience of description.

1A and 1B, as described above, the plurality of stack-structures 170 may extend side by side in the first direction. In this case, the plurality of stacked structures 170 may be arranged at substantially the same pitch P along the second direction.

Referring to FIG. 1B, the stack-structure 170 may include a first portion 168a and a second portion 168b. The first portion 168a and the second portion 168b may be aligned in the first direction. The second portion 168b preferably has a smaller width than the first portion 168a in the second direction. The entirety of the first portion 168a may have a substantially uniform first width W1. The width of the first portion 168b may vary depending on the position of the first direction. The minimum width of the second portion 168b is defined as a second width W2. According to one embodiment, the second width W2 of the second portion 168b may be a substantially central portion of the second portion 168b.

The first portion 168a of the stack-structure 170 may have a first sidewall 172a and a second sidewall 172b extending side by side in the first direction and facing each other. Similarly, second portion 168b of stack-structure 170 may have first sidewall 173a and second sidewall 173b opposite each other. The first sidewall 172a and the second sidewall 172b of the first portion 168a may be connected to the first sidewall 173a and the second sidewall 173b of the second portion 168b, respectively. In plan view, the first sidewall 173a of the second portion 168b may be laterally concave with respect to the first sidewall 172a of the first portion 168a. That is, the first sidewall 173a of the second portion 168b may be concave toward the second sidewall 173b of the second portion 168b. The first sidewall 173a of the second portion 168b may have a round shape.

As shown in FIG. 1B, according to one embodiment, the second sidewall 173b of the second portion 168b and the second sidewall 172b of the first portion 168a extend in the first direction. One flat sidewall can be made.

The common source region 150 next to the stack-structure 170 having the first and second portions 168a and 168b may include a non-landing portion 148a and a landing portion 148b. The non-landing portion 148a may be located next to the first portion 168a of the stack-structure 170, and the landing portion 148b is a second portion 168b of the stack-structure 170. It can be located next to it. The strapping contact plug 180 may be electrically connected to the landing portion 148b. The landing part 148b may have a larger width than the non-landing part 148ab. Similar to the first and second portions 168a and 168b of the stack-structure 170, the entirety of the non-landing portion 148a may have a substantially uniform width S1, and the landing portion The width of 148b may vary depending on the position of the first direction. Due to the second portion 168b of the stack-structure 170, the landing portion 148b of the common source region 150 may include a portion having a maximum width S2. The sum of the first width W1 of the first portion 168a of the stack-structure 170 and the width S1 of the non-landing portion 148a is the second portion 168b of the stack-structure 170. It may be substantially equal to the sum of the second width (W2) and the maximum width (S2) of the landing portion (148b). The strapping contact plug 180 may directly contact the landing portion 148b. Alternatively, a metal-semiconductor compound layer (not shown) may be formed on an upper surface of the common source region 150, and the strapping contact plug 180 may contact the metal-semiconductor compound layer. The metal-semiconductor compound layer may be disposed under the device isolation pattern 177. For example, the metal compound semiconductor layer may be a metal silicide layer.

With continued reference to FIGS. 1A and 1B, each of the plurality of stack-structures 170 may have the first portion 168a and the second portion 168b. Thus, each of the common source regions 150 may include the non-landing portion 148a and the landing portion 148b. A plurality of strapping contact plugs 180 may penetrate the device isolation patterns 177 and contact the common source regions 150, respectively. Second portions 148b of the stack-structures 170 and the strapping contact plugs 180 may be alternately and repeatedly arranged in the second direction.

1A, 1B, and 1C, an interlayer dielectric layer 183 may be disposed on the strapping contact plugs 180, the device isolation patterns 177, and the vertical active patterns 130. Can be. Bit lines 190a may be disposed on the interlayer dielectric layer 183. The bit lines 190a may be electrically connected to upper ends of the vertical active patterns 130. A strapping line 190b may be disposed on the interlayer dielectric film 183. The strapping line 190b may be electrically connected to upper surfaces of the strapping contact plugs 180.

As shown in FIG. 1B, the bit lines 190a and the strapping line 190b may be positioned at substantially the same level from the top surface of the substrate 100. As illustrated in FIG. 1A, the bit lines 190a and the strapping line 190b may extend side by side in the second direction.

The bit line 190a may be electrically connected to the vertical active pattern 130 under the bit line 190a via the first conductive plug 185a. The first conductive plug 185a may continuously penetrate the interlayer dielectric layer 183 and the capping dielectric pattern 135 between the bit line 190a and the vertical active pattern 130. The strapping line 190ba may be electrically connected to the strapping contact plug 180 via the second conductive plug 185b. The second conductive plug 185b may pass through the interlayer dielectric layer 183 between the strapping line 190ab and the strapping contact plug 180. The conductive plugs 185a and 185b may be selected from a metal (ex, tungsten, copper or aluminum, etc.), a conductive metal nitride (ex, titanium nitride or tantalum nitride, etc.) or a transition metal (ex, titanium, tantalum, etc.). It may include at least one. The bit line 190a and the strapping line 190b may be formed of a metal (ex, tungsten, copper, or aluminum), a conductive metal nitride (ex, titanium nitride or tantalum nitride, etc.) or a transition metal (ex, titanium, tantalum, etc.). It may include at least one selected from).

According to an embodiment, the vertical active pattern under the strapping line 190ba may be a dummy vertical active pattern. In addition, the vertical active pattern adjacent to the strapping line 190ab may also be a dummy vertical active pattern. The dummy vertical active pattern may not be used as a vertical cell string. The first conductive plug 185a may not be formed on the dummy vertical active pattern. As a result, the function of the dummy vertical active pattern may be limited. The dummy vertical active pattern may not be electrically connected to the bit line. At least a portion of the dummy vertical active pattern may penetrate the second portion 168b of the stack-structure 170.

According to the three-dimensional semiconductor memory element described above, the common source region 150 is electrically connected to the strapping line 190b via the strapping contact plug 180. As a result, the resistance of the common source region 150 may be lowered to improve reliability of the 3D semiconductor memory device. In addition, the stack-structure 170 may include a first portion 168a and a second portion 168b having a smaller width than the first portion 168a. Accordingly, it is possible to secure a planar area in which the strapping contact plug 180 can contact the common source region 150. As a result, the strapping contact plug 180 may be brought into contact with the common source region 150 while the gap between the stack structures 170 is minimized. In particular, the stack-structures 170 may be arranged at the same pitch P, and the width of the landing portion 148b of the common source region 150 may be increased. As a result, a three-dimensional semiconductor memory device optimized for high integration can be realized.

In the above-described three-dimensional semiconductor memory device, the entirety of the multilayer dielectric layer 160 may extend horizontally to cover the top and bottom surfaces of the gate patterns GSG, CG, and SSG. Alternatively, the multilayer dielectric film may have a different shape. This will be described with reference to the drawings.

FIG. 2A is a cross-sectional view taken along lines II ′ and II-II ′ of FIG. 1A to illustrate a three-dimensional semiconductor memory device according to another embodiment of the present invention, and FIG. 2B is an enlarged view of portion A of FIG. 2A.

2A and 2B, the multilayer dielectric layer 260 between the vertical active pattern 230 and the gate patterns GSG, CG, and SSG may include a tunnel dielectric layer, a charge storage layer, and a blocking dielectric layer. The tunnel dielectric layer, the charge storage layer, and the blocking dielectric layer of the multilayer dielectric layer 260 may be formed of the same material as the tunnel dielectric layer, the charge storage layer, and the blocking dielectric layer of the multilayer dielectric layer 160 of FIG. 1B, respectively.

The multilayer dielectric film 260 may include a first sub film 255 and a second sub film 257. The first sub layer 255 may extend vertically to be interposed between the vertical active pattern 230 and the insulating pattern 110a. The second sub layer 257 may extend horizontally to cover lower and upper surfaces of the gate patterns GSG, CG, and SSG. The first sub layer 255 may include at least a portion of the tunnel dielectric layer, and the second sub layer 257 may include at least a portion of the blocking dielectric layer. One of the first and second sub layers 255 and 257 may include the charge storage layer. In example embodiments, the first sub layer 255 may include the tunnel dielectric layer, the charge storage layer, and a barrier dielectric layer in the blocking dielectric layer, and the second sub layer 257 may be a high dielectric layer in the blocking dielectric layer. It may include. However, the present invention is not limited thereto. The first and second sub layers 255 and 257 may be configured in other combinations.

The vertical active pattern 230 may include a first vertical semiconductor pattern 227 and a second vertical semiconductor pattern 228. The first vertical semiconductor pattern 227 may be interposed between the second vertical semiconductor pattern 228 and the first sub layer 255. The first vertical semiconductor pattern 227 may not be in contact with the substrate 100 by an extension of the first sub layer 255. The second vertical semiconductor pattern 228 may be in contact with the first vertical semiconductor pattern 227 and the substrate 100. The charge dielectric pattern 125 may fill an inner space surrounded by the second vertical semiconductor pattern 228. The vertical active pattern 230 may further include the first and second vertical semiconductor patterns 227 and 228 and a capping semiconductor pattern 127 disposed on the charging dielectric pattern 125.

Meanwhile, the second sidewall 173b of the second portion 168b of the stack-structure 170 described with reference to FIGS. 1A, 1B, and 1C may have the second sidewall 172b of the first portion 168a together. One flat side wall can be achieved. Alternatively, the second sidewall of the second portion of the stack-structure 170 may be of other shapes. This will be described with reference to the drawings.

FIG. 3A is a plan view illustrating a three-dimensional semiconductor memory device according to still another embodiment of the present invention, and FIG. 3B is an enlarged plan view of a part of the gate stack-structure of FIG. 3A.

3A and 3B, the pair of stacked-structures 170 adjacent to both sides of the strapping contact plug 180 may have a symmetrical structure with respect to the strapping contact plug 180. As disclosed in FIG. 3B, the stack-structure 170 may include a first portion 168a and a second portion 168b '. The first sidewall 173a of the second portion 168b 'may be laterally recessed based on the first sidewall 172a of the first portion 168a. Similarly, the second sidewall 173b 'of the second portion 168b' may be concave laterally based on the second sidewall 172b of the first portion 168a. That is, the first sidewall 173a and the second sidewall 173b 'of the second portion 168b' may be concave toward each other. Accordingly, the sidewalls adjacent to the strapping contact plug 180 of the second portions 168b 'of the pair of stack-structures 170 may be concave. As shown in FIG. 3A, even in the present embodiment, the stack-structures 170 may be arranged at the same pitch P in the second direction. As a result, the width of the landing portion 148b 'of the common source region 150 to which the strapping contact plug 180 is in contact may be further increased within a limited area. Also in this embodiment, the sum of the maximum width S2 'of the landing portion 148b' and the minimum width W2 'of the second portion 168b' of the stack-structure 170 is the common source region 150. May be equal to the sum of the width S1 of the non-landing portion 148a and the width W1 of the first portion 168a of the stack-structure 170.

The vertical active pattern 230 and the multilayer dielectric film 260 described with reference to FIGS. 2A and 2B may also be applied to the three-dimensional semiconductor memory device disclosed in FIGS. 3A and 3B.

According to the embodiments described above, the strapping contact plug 180 may be disposed on each common source region 150. Alternatively, a strapping contact plug may not be formed on some of the common source regions 150. This will be described with reference to the drawings.

4A is a plan view illustrating a three-dimensional semiconductor memory device according to still another embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along III-III 'and IV-IV' of FIG. 4A.

4A and 4B, the strapping contact plugs 180 may contact the common source regions selected from the common source regions 150. The strapping contact plug may not be in contact with the non-selected common source regions among the common source regions 150. The strapping contact plugs 180 may be arranged in the second direction, and the non-selected common source region may be disposed between the strapping contact plugs 180. The strapping contact plugs 180 are electrically connected to the strapping line 190b. According to the present embodiment, the number of strapping contact plugs 180 under the strapping line 190b may be smaller than the number of common source regions 150 under the strapping line 190b.

The common source region 150 in contact with the strapping contact plug may include a non-landing portion 148a and a landing portion 148b 'described with reference to FIGS. 3A and 3B. In this case, the facing sidewalls of the second portions of the pair of stack-structures 170 adjacent to both sides of the landing portion 148b 'may all be concave laterally. Alternatively, the common source region 150 in contact with the strapping contact plug may include the non-landing portion 148a and the landing portion 148b described with reference to FIGS. 1A and 1B. In this case, any one of the sidewalls facing each other of the second portions of the pair of stack-structures 170 adjacent to both sides of the landing portion 148bb may be concave sideways. The non-selected common source region may not include a landing portion. That is, the non-selected common source region may have a substantially uniform width, and the width of the non-selected common source region may be substantially the same as the width of the non-landing unit 148a of the selected common source region. According to one embodiment, the stack-structures 170 may comprise a stack-structure having an overall uniform width.

As shown in FIG. 4B, a connection doped region 200 doped with the same type of dopant as the common source regions 150 may be disposed in the substrate 100. As illustrated in FIG. 4A, the connection doped region 200 may extend in the second direction to be connected to the selected common source region and the non-selected common source region. According to an embodiment, the connection doped region 200 may be disposed under the strapping line 190ab. In other words, the connection doped region 200 and the strapping line 190ab may overlap. As a result, the connection doped region 200 may be connected to the landing portion of the selected common source region. The unselected common source region may be electrically connected to the strapping contact plug 180 on the selected common source region via the connection doped region 200.

Next, a method of manufacturing a 3D semiconductor memory device according to embodiments of the present invention will be described with reference to the drawings.

5A through 5F are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 1A to explain a method of manufacturing a 3D semiconductor memory device according to example embodiments.

Referring to FIG. 5A, a buffer dielectric layer 103 may be formed on a substrate 100 doped with a dopant of a first conductivity type. The sacrificial layers 105 and the insulating layers 110 may be alternately and repeatedly stacked on the buffer dielectric layer 103. The sacrificial layers 105 may be formed of a material having an etching selectivity with respect to the insulating layer 110. For example, the insulating layers 110 may be formed of oxide layers, and the sacrificial layers 105 may be formed of nitride layers.

The insulating layers 110, the sacrificial layers 105, and the buffer dielectric layer 103 are successively patterned to form channel holes 115. The channel holes 115 may expose the substrate 100. A semiconductor film may be conformally formed on the substrate 100 having the channel holes 115, and a charge dielectric layer may be formed on the semiconductor film to fill the channel holes 115. The charging dielectric layer 115 may be formed of an oxide layer, a nitride layer, and / or an oxynitride layer. The charge dielectric layer and the semiconductor layer may be planarized until the uppermost insulating layer is exposed to form a vertical semiconductor pattern 120 and a charge dielectric pattern 125 in each channel hole 115. The vertical semiconductor pattern 120 and the charge dielectric pattern 125 are recessed so that upper ends of the vertical semiconductor pattern 120 and the charge dielectric pattern 125 are lower than the upper surface of the upper insulating layer. Can be located. Subsequently, a capping semiconductor layer may be formed on the substrate 100. The capping semiconductor layer may fill the channel hole 115 on the vertical semiconductor pattern 120 and the charge dielectric pattern 125. The capping semiconductor layer may be planarized until the uppermost insulating layer is exposed to form the capping semiconductor pattern 127. The vertical semiconductor pattern 120 and the capping semiconductor pattern 127 may constitute a vertical active pattern 130. A drain region may be formed by providing a second conductive dopant in at least a portion of the capping semiconductor pattern 127.

Referring to FIG. 5B, a capping dielectric layer may be formed on the vertical active patterns 130 and the uppermost insulating layer. The capping dielectric layer, the insulating layers 110, the sacrificial layers 105, and the buffer dielectric layer 103 are successively patterned to sequentially stack the buffer dielectric patterns 103a, the preliminary mold structure 140, and the capping dielectric patterns 135. ) Can be formed. In this case, the plurality of preliminary mold structures 140 may be formed on the substrate 100. A trench 145 is formed between the preliminary mold structures 140. The sacrificial patterns 105a may be exposed by the trench 145. Each preliminary mold structure 140 may include sacrificial patterns 105a and insulating patterns 110a that are alternately and repeatedly stacked. Each preliminary mold structure 140 may include a plurality of vertical active patterns 130.

Like the stack-structure 170 of FIG. 1A, the preliminary mold structures 140 may extend side by side in a first direction in a plan view. In the plan view, the preliminary mold structures 140 may be arranged at the same pitch in a second direction perpendicular to the first direction. According to one embodiment, each preliminary mold structure 140 may include a first portion and a second portion. The first portion of the preliminary mold structure 140 has a first width W1 in the second direction, and the second portion of the preliminary mold structure 140 has the first width W1 in the second direction. It can have a smaller width. The second portion of the preliminary mold structure 140 may have a second width W2. The second width W2 of the second portion of the preliminary mold structure 140 may be the minimum width of the second portion of the preliminary mold structure 140. In plan view, the preliminary mold structure 140 may have a shape substantially the same as the planar shape of the stack-structure 170 of FIG. 1A.

Common source regions 150 may be formed by providing the second conductivity type dopant in the substrate 100 under the trench 145. Due to the shape of the preliminary mold structures 140, the common source regions 150 may be formed in the shape described with reference to FIGS. 1A and 1B.

Referring to FIG. 5C, empty regions 155 may be formed by removing sacrificial patterns 105a exposed in the trench 145. As a result, the mold structure 140a may be formed. The mold structure 140a may include the stacked insulating patterns 110a and the empty regions 155 between the insulating patterns 110a. In example embodiments, the empty regions 155 may expose portions of sidewalls of the vertical active pattern 130.

Referring to FIG. 5D, the multilayer dielectric layer 160 may be conformally formed on the substrate 100 having the empty regions 155. The multilayer dielectric layer 160 may be formed on the inner surfaces of the empty regions 155 to have a substantially uniform thickness.

A gate conductive layer 165 may be formed on the substrate 100 having the multilayer dielectric layer 160 to fill the empty regions 155. The gate conductive layer 165 may partially fill the trench 145. However, the present invention is not limited thereto.

Referring to FIG. 5E, gate patterns GSG, CG, and SSG filling the empty regions 155 may be formed by removing the gate conductive layer 165 outside the empty regions 155. . By removing the gate conductive layer 165 outside the empty regions 155, the gate patterns GSG, CG, and SSG may be separated from each other. Alternately and repeatedly stacked gate patterns GSG, CG, SSG and insulating patterns 110a may be included in stack-structure 170.

In example embodiments, the multilayer dielectric layer 160 outside the empty regions 155 may be removed. Alternatively, at least a portion of the multilayer dielectric layer 160 outside the empty regions 155 may remain.

Subsequently, a device isolation layer filling the trench 145 may be formed on the substrate 100, and the device isolation layer may be planarized to form a device isolation pattern 177 filling the trench 145.

Referring to FIG. 5F, strapping contact plugs 180 may be formed to penetrate the device isolation pattern 177 and contact the common source regions 150, respectively.

Subsequently, an interlayer dielectric layer 183 may be formed on the entire surface of the substrate 100. A first conductive plug 185a may be formed to continuously penetrate through the interlayer dielectric layer 183 and the capping dielectric pattern 135 to be in contact with the top of the vertical active pattern 130. In this case, the first conductive plug 185a may not be formed on the vertical active pattern used as the dummy vertical active pattern described with reference to FIGS. 1A, 1B, and 1C. A second conductive plug 185b may be formed through the interlayer dielectric layer 183 and in contact with the strapping contact plug 180. The first and second conductive plugs 185a and 185b may be formed at the same time.

Bit lines 190a and strapping lines 190b of FIGS. 1A and 1C may be formed on the interlayer dielectric layer 183. As a result, the three-dimensional semiconductor memory device described with reference to FIGS. 1A, 1B, and 1C may be implemented.

Next, a method of manufacturing the three-dimensional semiconductor memory device disclosed in Figs. 2A and 2B will be described centering on the characteristic parts.

6A and 6B are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 1A to explain a method of manufacturing a 3D semiconductor memory device according to another exemplary embodiment.

Referring to FIG. 6A, a buffer dielectric layer 103 may be formed on the substrate 100, and the sacrificial layers 105 and the insulating layers 110 are alternately and repeatedly stacked on the buffer dielectric layer 103. You can. The channel holes 115 may be formed by successively patterning the insulating layers 110, the sacrificial layers 105, and the buffer dielectric layer 103.

The first sub layer 255 may be conformally formed on the substrate 100 having the channel holes 115. The first semiconductor layer may be conformally formed on the first sub layer 255. The first semiconductor layer and the first sub layer 255 may be continuously anisotropically etched until the substrate 100 under the channel hole 115 is exposed. Accordingly, a first vertical semiconductor pattern 227 may be formed on the sidewall of the channel hole 115. The first sub layer 255 may be interposed between the sidewall of the channel hole 115 and the first vertical semiconductor pattern 227. The first sub layer 255 on the bottom surface of the channel hole 115 and the upper insulating layer may be removed by the anisotropic etching.

Referring to FIG. 6B, a second semiconductor layer may be conformally formed on the entire surface of the substrate 100, and a filling dielectric layer may be formed on the second semiconductor layer to fill the channel hole 115. The charge dielectric layer and the first semiconductor layer may be planarized until the uppermost insulating layer is exposed. As a result, a second vertical semiconductor pattern 228 and a charging dielectric pattern 125 may be formed in the channel hole 115. The second vertical semiconductor pattern 228 may contact the substrate 100 under the first vertical semiconductor pattern 227 and the channel hole 115. Upper ends of the first and second vertical semiconductor patterns 227 and 228 and the charging dielectric pattern 125 may be recessed to form a capping semiconductor pattern 127. The first and second vertical active patterns 227 and 228 and the capping semiconductor pattern 127 may be included in the vertical active pattern 230. A drain region may be formed in at least a portion of the capping semiconductor pattern 127.

Subsequently, a capping dielectric layer may be formed on the entire surface of the substrate 100. The capping dielectric layer, the insulating layers 110, the sacrificial layers 105, and the buffer dielectric layer 103 are successively patterned to form a trench 145, a buffer dielectric pattern 103a, a preliminary mold structure, and a capping dielectric pattern, which are sequentially stacked. 135 can be formed. The preliminary mold structure may include sacrificial patterns and insulating patterns 110a that are alternately and repeatedly stacked. The sacrificial patterns may be removed to form empty regions 155. The empty regions 155 may expose the first sub layer 255 on the sidewall of the vertical active pattern 230.

The second sub layer 257 may be conformally formed on the substrate 100 having the empty regions 155. The second sub-film 257 may be formed on the inner surfaces of the empty regions 155 to have a substantially uniform thickness. The first and second sub layers 255 and 257 may be included in the multilayer dielectric layer 260. Subsequent subsequent processes may be performed in the same manner as described with reference to FIGS. 5D to 5F. Thus, the three-dimensional semiconductor memory device disclosed in FIGS. 2A and 2B can be implemented.

Meanwhile, in the method of manufacturing the 3D semiconductor memory device described with reference to FIGS. 5A to 5F, the planar shape of the preliminary mold structure 140 of FIG. 5B is described with reference to FIGS. 3A and 3B. It can be formed in the planar form of. Thus, the three-dimensional semiconductor memory device disclosed in FIGS. 3A and 3B can be implemented.

The manufacturing method of the three-dimensional semiconductor memory device disclosed in Figs. 4A and 4B will be described centering on the characteristic parts. The manufacturing method of the three-dimensional semiconductor memory device disclosed in FIGS. 4A and 4B is also similar to the manufacturing method described with reference to FIGS. 5A to 5F. However, as shown in FIG. 7, the connection doped region 200 of FIGS. 4A and 4B may be formed before forming the sacrificial layers 105 and the insulating layers 110. The connection doped region 200 may be formed using a mask pattern defining the connection doped region 200. The buffer dielectric layer 103 may be used as an ion implantation buffer layer for forming the connection doped region 200. Alternatively, the buffer dielectric layer 103 may be formed after the connection doped region 200 is formed. In addition, the planar shape of the preliminary mold structure 140 of FIG. 5B may be formed into the planar shape of the stack-structures 170 of FIGS. 4A and 4B. Other manufacturing processes may be performed in the same manner as described with reference to FIGS. 5A to 5F. Thus, the three-dimensional semiconductor memory device shown in FIGS. 4A and 4B can be implemented.

The 3D semiconductor memory devices disclosed in the above-described embodiments may be implemented in various types of semiconductor package. For example, three-dimensional semiconductor memory devices according to embodiments of the present invention may be packaged on packages (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) The package may be packaged in a Wafer-Level Processed Stack Package (WSP).

The package in which the 3D semiconductor memory device is mounted according to embodiments of the present invention may further include at least one other semiconductor device (eg, a controller, a memory device, and / or a hybrid device, etc.) that performs other functions. have.

8 is a block diagram schematically illustrating an example of an electronic system including a 3D semiconductor memory device based on the technical spirit of the present invention.

Referring to FIG. 8, an electronic system 1100 according to an embodiment may include a controller 1110, an input / output device 1120, an I / O, a memory device 1130, an interface 1140, and a bus 1150. bus). The controller 1110, the input / output device 1120, the memory device 1130, and / or the interface 1140 may be coupled to each other through the bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar thereto. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The memory device 1130 may include at least one of the three-dimensional semiconductor memory devices disclosed in the above-described embodiments. In addition, the memory device 1130 may further include other types of semiconductor memory devices (eg, magnetic memory devices, phase change memory devices, DRAM devices, and / or SRAM devices). The interface 1140 may perform a function of transmitting data to or receiving data from a communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired / wireless transceiver. Although not shown, the electronic system 1100 may further include a high speed DRAM device and / or an SRAM device as an operation memory device for improving the operation of the controller 1110.

The electronic system 1100 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

9 is a block diagram schematically illustrating an example of a memory card including a 3D semiconductor memory device based on the inventive concept.

9, a memory card 1200 according to an embodiment of the present invention includes a memory device 1210. The memory device 1210 may include at least one of the three-dimensional semiconductor memory devices disclosed in the above-described embodiments. The memory device 1210 may further include other types of semiconductor memory devices (eg, magnetic memory devices, phase change memory devices, DRAM devices, and / or SRAM devices). The memory card 1200 may include a memory controller 1220 that controls the exchange of data between the host and the storage device 1210.

The memory controller 1220 may include a processing unit 1222 for controlling the overall operation of the memory card. In addition, the memory controller 1220 may include an SRAM 1221, which is used as an operation memory of the processing unit 1222. In addition, the memory controller 1220 may further include a host interface 1223 and a memory interface 1225. The host interface 1223 may include a data exchange protocol between the memory card 1200 and a host. The memory interface 1225 may contact the memory controller 1220 and the memory device 1210. Further, the memory controller 1220 may further include an error correction block 1224 (Ecc). The error correction block 1224 can detect and correct errors in data read from the storage device 1210. [ Although not shown, the memory card 1200 may further include a ROM device for storing code data for interfacing with a host. The memory card 1200 may be used as a portable data storage card. Alternatively, the memory card 1200 may be implemented as a solid state disk (SSD) capable of replacing a hard disk of a computer system.

As mentioned above, although embodiments of the present invention have been described with reference to the accompanying drawings, the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. It is therefore to be understood that the above-described embodiments are illustrative and non-restrictive in every respect.

Claims (10)

A stack-structure disposed on a substrate and extending in a first direction, the stack-structure including gate patterns and insulating patterns alternately and repeatedly stacked, the stack-structure comprising a first portion and a second portion; A second portion of the stack-structure having a width smaller than the first portion in a second direction perpendicular to the first direction;
A plurality of vertical active patterns penetrating the stack-structure;
A multilayer dielectric film interposed between sidewalls of each vertical active pattern and each gate pattern;
A common source region formed in the substrate on one side of the stack-structure; And
And a strapping contact plug disposed on the common source region, wherein the strapping contact plug is located next to the second portion of the stack-structure. The method according to claim 1,
The first portion of the stack-structure has a first sidewall and a second sidewall facing each other and extending side by side in the first direction,
The second portion of the stack-structure has a first sidewall and a second sidewall opposite to each other,
The first sidewall of the second portion of the stack-structure is laterally concave relative to the first sidewall of the first portion,
And the strapping contact plug is located next to the first sidewall of the second portion. The method according to claim 2,
And the second sidewall of the first portion and the second sidewall of the second portion form a flat sidewall extending in the first direction. The method according to claim 2,
And the second sidewall of the second portion is recessed laterally relative to the second sidewall of the first portion. The method according to claim 1,
The common source region extends in the first direction,
The common source region includes a non-landing portion located next to the first portion of the stack-structure and a landing portion located next to the second portion of the stack-structure, And a width in the second direction of the landing portion is greater than a width in the second direction of the non-landing portions. The method according to claim 1,
Further comprising a device isolation pattern disposed on the common source region,
And the strapping contact plug is electrically connected to the common source region through the device isolation pattern. The method according to claim 1,
At least a portion of the multilayer dielectric film extends laterally to cover the top and bottom surfaces of each gate pattern. A plurality of stack-structures disposed on a substrate and extending side by side in a first direction, each stack-structure including gate patterns and insulating patterns stacked alternately and repeatedly; Arranged at the same pitch in a second direction perpendicular to the first direction;
A plurality of vertical active patterns penetrating the respective stacked-structures;
A multilayer dielectric film interposed between sidewalls of each vertical active pattern and each gate pattern;
A plurality of common source regions formed in the substrate between the stack-structures and extending side by side in the first direction; And
A strapping contact plug electrically connected to any one of the common source regions,
At least one of a pair of the stack-structures adjacent to both sides of the strapping contact plug includes a first portion and a second portion having a width smaller in the second direction than the first portion, wherein the strapping contact plug includes A three-dimensional semiconductor memory element located next to the second portion. The method of claim 8,
The common source region electrically connected to the strapping contact plug includes a non-landing portion and a landing portion,
The landing part has a width greater than the non-landing part in the second direction,
And the second portion of the landing portion and the stack-structure is arranged in the second direction. The method of claim 8,
The strapping contact plug is provided in plural, the plurality of strapping contact plugs are respectively connected to the common source regions,
Each of the stack-structures comprises the first portion and the second portion,
And the second portions of the strapping contact plugs and the stack-structures are alternately and repeatedly arranged along the second direction.

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