KR20120039902A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20120039902A
KR20120039902A KR1020100101351A KR20100101351A KR20120039902A KR 20120039902 A KR20120039902 A KR 20120039902A KR 1020100101351 A KR1020100101351 A KR 1020100101351A KR 20100101351 A KR20100101351 A KR 20100101351A KR 20120039902 A KR20120039902 A KR 20120039902A
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KR
South Korea
Prior art keywords
contact hole
pattern
forming
spacer
semiconductor device
Prior art date
Application number
KR1020100101351A
Other languages
Korean (ko)
Inventor
이동진
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100101351A priority Critical patent/KR20120039902A/en
Publication of KR20120039902A publication Critical patent/KR20120039902A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent SAC(Self-Aligned Contact) failure between a contact hole and a gate since a spacer is formed by depositing a spacer material on one side of an outermost contact hole. CONSTITUTION: A pattern is formed on a semiconductor substrate. An insulating layer is formed on the pattern and on the semiconductor board. A contact hole(130) is formed by etching the insulating layer until the semiconductor substrate is exposed. A barrier layer(115) is formed on the contact hole and the insulating layer. One side of an outermost contact hole is blocked. A spacer is selectively formed on one side of the outermost contact hole.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of preventing self-aligned contact (SAC) failure between a contact plug and a gate and improving the characteristics of the semiconductor device.

As the recent development of semiconductor device manufacturing technology and the application field of memory devices have been expanded, there is an urgent need to develop a technology for manufacturing a large-capacity memory device in which integration degree is improved and electrical characteristics are not degraded. Accordingly, various studies have been conducted to improve photo-lithography processes or to obtain stable process conditions by overcoming limitations such as cell structures, wiring forming materials, and insulating film forming materials. Among these, the photolithography process is an essential technology applied to the contact forming process or the pattern forming process for connecting the various layers constituting the device to each other, and the improvement of the photolithography process technology determines the success or failure of the highly integrated semiconductor device. Becomes

The photolithography process uses a principle of changing a property by causing a chemical reaction when a specific chemical (photo resist) receives light.However, by using a mask of a desired pattern, a photoresist is selectively injected to the light to mask the pattern of the mask. It is a process of forming in the same pattern as. The photolithography process is a coating process for applying a photoresist corresponding to a film of a general photograph, an exposure process for selectively scanning light using a mask, and a photoresist for removing a portion of the lighted portion using a developer to form a pattern. It consists of a developing process.

The photolithography process currently commercialized uses exposure equipment using short wavelength light sources such as KrF and ArF, and the resolution of the pattern obtained from such short wavelength light sources is limited to about 0.1 μm. Thus, it is very difficult to fabricate highly integrated semiconductor devices of smaller sized patterns.

In particular, a resist flow process using heat has been performed to reduce the size of a contact hole pattern, which is one of fine patterns included in a semiconductor device, using a conventional technology. However, in the resist flow process, even if the same energy is delivered to the front surface of the photoresist at a temperature higher than the glass transition temperature, the upper part of the pattern spreads more than the lower part because the photoresist flows relatively higher than the upper and middle parts of the photoresist. There is a problem that overflow occurs.

As described above, the technology for reducing the size of the contact hole pattern is not yet complete. In addition, the development of the technology of the exposure equipment has also reached a limit point, the situation of technology development is delayed. In the case where fine patterns of non-uniform size are formed on the semiconductor substrate, the measurement accuracy of the critical dimension (CD) is reduced, thereby not only obtaining sufficient etching margin for performing a stable subsequent etching process, but also yielding final semiconductor device yield. This decreasing phenomenon occurs.

In the above-described method for manufacturing a semiconductor device, as the design rule of the DRAM device becomes smaller, defects in the contact hole or contact plug area reduced in forming the contact hole or contact plug are continuously generated. The defects in forming the contact plugs are caused by short defects and bridge defects between the contact plugs and the gate pattern or the bit line pattern. If a short defect occurs between the contact plug and the gate pattern or the bit line pattern, it may cause data transmission between adjacent cells, an operation error of the device, and reduce the yield of the semiconductor device.

In order to solve the above problems, the present invention forms a contact hole, and then deposits a spacer material on one side of a region (especially the outermost contact hole) in which a short between the lower layer and the contact hole frequently occurs. A method of manufacturing a semiconductor device capable of preventing self-aligned contact (SAC) failure between a contact hole and a gate by forming a spacer is provided.

The present invention provides a method of forming a contact hole on a semiconductor substrate, forming an insulating film on the pattern and the semiconductor substrate, etching the insulating film until the semiconductor substrate is exposed, and forming a contact hole. And forming a blocking layer on the insulating layer, blocking a part of the outermost contact hole, and forming a spacer in the outermost contact hole. .

Preferably, the pattern includes a gate pattern, a bit line pattern or all conductive patterns.

Preferably, the spacer is characterized in that it comprises a nitride (Nitride).

Preferably, the part of the contact hole is selectively blocked by adjusting the size of the blocking film.

Preferably, the CD (Critical Dimension) of the contact hole is adjusted by adjusting the thickness of the spacer.

Preferably, after the step of selectively forming a spacer on one side of the outermost contact hole, characterized in that it further comprises the step of removing the blocking film.

According to the present invention, after forming a contact hole, a spacer is formed by depositing a spacer material on one side of a region (particularly, an outermost contact hole) where a short between the lower layer and the contact hole occurs frequently, thereby forming a spacer. There is an advantage that can prevent the SAC (Self-Aligned Contact) fail with the gate.

1 is a plan view showing a method of manufacturing a semiconductor device according to the present invention.
2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if it is mentioned that the layer is on another layer or substrate it may be formed directly on another layer or substrate, Alternatively, a third layer may be interposed therebetween. Also, the same reference numerals throughout the specification represent the same components.

1 is a plan view illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1, the bit line contact holes 130 are formed on a semiconductor substrate.

Next, a selective blocking layer 115 is deposited on the entire surface including the bit line contact hole 130. In this case, the bit line contact hole 130 of the region where the short defect of the bit line contact hole 130 and the gate pattern (not shown) frequently occurs (called the outer region or referred to as the X region) is a selective blocking layer. A portion of the bit line contact hole 130 is formed to be partially blocked by the 115, and a material 140 for spacers is deposited in the unoccupied area of the non-blocked bit line contact hole 130. short) defects or self-aligned contact (SAC) failure can be prevented (see enlarged drawing of region Y in FIG. 1).

2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2, a gate pattern 110 is formed on the semiconductor substrate 100. Here, the gate pattern 110 is described as an embodiment, and the present invention can be applied to a technique of forming all conductive patterns including bit line patterns instead of the gate pattern 110. In this case, the gate pattern 110 may be formed in a stacked structure of a gate oxide layer (not shown) and a gate electrode layer (not shown). In addition, the spacer 115 may be formed on the sidewall of the gate pattern 110.

Next, an insulating film 120 and a photoresist film (not shown) are sequentially formed on the entire surface including the gate pattern 110. In this case, the insulating film 120 preferably includes an oxide film.

Then, a photosensitive film pattern (not shown) is formed by an exposure and development process using a bit line contact plug mask. The bit line contact hole 130 is formed by etching the insulating layer 120 until the semiconductor substrate 100 is exposed using the photoresist pattern as an etching mask.

Next, a selective blocking layer (115, a selective blocking layer of FIG. 1) is formed on the entire surface including the bit line contact hole 130. Here, the selective blocking film 115 is a mask, and selectively blocks one side of the outermost bit line contact hole 130 in which short fail frequently occurs. That is, the outermost bit line contact hole is selectively blocked as shown in 'X' of FIG. 1. In addition, the spacer 140 may be deposited in an open area of the bit line contact hole 130 to prevent a short fail between the bit line contact hole 130 and the gate pattern 110 adjacent to the bit line contact hole 130. Thereafter, the selective blocking film (115 in FIG. 1) is removed.

Subsequently, the conductive material is filled in the bit line contact hole 130 and then flattened and etched by a method such as chemical mechanical polishing to complete the bit line contact plug (not shown).

Here, although the method for forming a contact of a DRAM device of the present invention has been described, it is also applied to the formation of a contact hole or a contact plug of a flash or SRAM device, and thus an electrical short or fail. Defects can be prevented.

As described above, in the present invention, after forming a contact hole, a spacer material is deposited by depositing a spacer material on one side of an area (especially, the outermost contact hole) in which a short between the lower layer and the contact hole occurs frequently. Formation has an advantage of preventing self-aligned contact (SAC) failure between the contact hole and the gate.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (6)

Forming a pattern on the semiconductor substrate;
Forming an insulating film on the pattern and the semiconductor substrate;
Etching the insulating layer until the semiconductor substrate is exposed to form contact holes;
Forming a blocking layer on the contact hole and the insulating layer, and blocking one side of the outermost contact hole; And
Selectively forming a spacer on one side of the outermost contact hole;
And forming a second insulating film on the semiconductor substrate. The method of claim 1,
The pattern may include a gate pattern, a bit line pattern, or any conductive pattern. The method of claim 1,
The spacer comprises a nitride film (Nitride). The method of claim 1,
And partially blocking the contact hole by controlling the size of the blocking film. The method of claim 1,
And controlling the CD (critical dimension) of the contact hole by adjusting the thickness of the spacer. The method of claim 1,
After the step of selectively forming a spacer on one side of the outermost contact hole,
The method of manufacturing a semiconductor device further comprising the step of removing the blocking film.
KR1020100101351A 2010-10-18 2010-10-18 Method for manufacturing semiconductor device KR20120039902A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100101351A KR20120039902A (en) 2010-10-18 2010-10-18 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100101351A KR20120039902A (en) 2010-10-18 2010-10-18 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20120039902A true KR20120039902A (en) 2012-04-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100101351A KR20120039902A (en) 2010-10-18 2010-10-18 Method for manufacturing semiconductor device

Country Status (1)

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KR (1) KR20120039902A (en)

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