KR20120033706A - Semiconductor device using hard mask and fabricating method thereof - Google Patents

Abstract

PURPOSE: A semiconductor device which uses a hard mask and a manufacturing method thereof are provided to protect a metal gate electrode from an etching phenomenon by forming a hard mask which is overlapped with the metal gate electrode. CONSTITUTION: A metal gate electrode(11) is formed on a substrate(1). A gate spacer(17) is formed on both sides of the metal gate electrode. A first insulating layer(5) is arranged on both sides of the gate spacer. An etching stopping layer(21) is arranged on the metal gate electrode. A hard mask(41) is formed on the etching stopping layer. A second insulating layer(51) is arranged on the hard mask.

Description

Semiconductor device using hard mask and method of manufacturing the same {Semiconductor device using hard mask and fabricating method

The present invention relates to a semiconductor device using a hard mask and a method of manufacturing the same.

In general, semiconductor devices include individual elements such as transistors or capacitors, and wiring for connecting the individual elements. In addition, the semiconductor device includes individual elements and individual elements, individual elements and wires, or contacts connecting the wires and wires.

In accordance with the recent trend toward higher performance, such semiconductor devices have reduced the size of gate electrodes of semiconductor devices, resulting in higher integration of devices. As a result, the size of the wirings and the contacts, as well as the devices, are also drastically reduced, thereby reducing the margin of the area where the wirings and the contacts are to be formed. Margin reduction with increasing integration can cause electrical failures between interconnects and contacts.

An object of the present invention is to provide a semiconductor device in which a hard mask is formed on an upper portion of a gate electrode.

Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can reduce damage to a gate electrode even when misalignment of a photoresist pattern occurs in a photolithography process for forming a contact.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the semiconductor device manufacturing method of the present invention for solving the above problems is a metal gate electrode, a gate spacer located on both sides of the metal gate electrode, and a first insulation disposed on both sides of the gate spacer on the substrate. Forming a layer, forming an etch stop layer on the metal gate electrode and the first insulating layer, forming a hard mask on the etch stop layer so as to overlap with the metal gate electrode, and forming the etch stop layer and the hard Forming a first contact hole by forming a second insulating layer on the mask and removing a portion of the second insulating layer to expose the etch stop layer.

One aspect of the semiconductor device of the present invention for solving the above problems is a substrate, a metal gate electrode formed on the substrate, a gate spacer located on both sides of the metal gate electrode, a first insulating layer located on both sides of the gate spacer An etch stop layer formed on the metal gate, a hard mask formed to overlap the metal gate electrode on the etch stop layer, a second insulating layer formed on the hard mask, and a contact spacer formed on a side surface of the second insulating layer. It includes.

Other specific details of the invention are included in the detailed description and drawings.

1 to 9 are cross-sectional views of intermediate structures for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one device is referred to as "directly connected to" or "directly coupled to" with another device indicates that no other device is intervened. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

Embodiments of the present invention will be described below using a semiconductor device using a metal gate electrode. However, it will be apparent to those skilled in the art that the present invention can be applied to a semiconductor device using a polysilicon gate electrode.

1 to 9 are diagrams for describing a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention. 1 to 9, illustrations of source / drain regions and element isolation regions such as shallow trench isolation (STI), which are formed in the substrate 1, are omitted for convenience of description.

First, referring to FIG. 1, a metal gate electrode 11, a barrier layer 13, a gate insulating layer pattern 15, a gate spacer 17, and a first insulating layer 5 are disposed on a substrate 1. Can be formed.

The substrate 1 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 1 may be a silicon substrate or may include other materials such as germanium, indium antimonide, lead tellurium compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonium, It is not limited to this.

A gate insulating layer (not shown) and a sacrificial gate electrode layer (not shown) are sequentially formed on the substrate 1, and then patterned to sequentially stack the gate insulating layer pattern 15 and the sacrificial gate electrode (not shown). A series of processes of forming the structure and forming the gate spacers 17 on both sides of the stacked structure may be performed.

An etch stop layer (not shown) and a first insulating layer 5 are formed on the substrate 1 on which the stacked structure is formed, and chemical mechanical polishing (CMP) is performed to expose the top surface of the sacrificial gate electrode (not shown). chemical mechanical polishing) process. Subsequently, the sacrificial gate electrode (not shown) is removed to form a trench (not shown), and the barrier layer 13 is formed along the top surface of the first insulating layer 5 and the side and bottom surfaces of the trench (not shown). After forming the foam, the metal gate electrode 11 may be formed by filling a metal layer to fill the trench (not shown). Then, for example, a chemical mechanical polishing process may be performed to stop polishing at the gate spacer 17. As a result, the upper surface of the metal gate electrode 11, the upper surface of the gate spacer 17, and the upper surface of the first insulating layer 5 may be located on the same plane. However, it will be apparent to those skilled in the art that the detailed process order and method included in the process of forming the metal gate electrode 11 of FIG. 1 may be changed.

The gate insulating layer pattern 15 may include, for example, a silicon oxide film or a high dielectric constant material formed by a chemical vapor deposition (CVD) method. That is, the silicon oxide film may be a single film, a high dielectric constant material single film, or a laminated film of the silicon oxide film and the high dielectric constant material. Here, the high dielectric constant material may include any one of hafnium oxide and hafnium silicon oxide.

The barrier layer 13 may be formed of titanium nitride (TiN) using, for example, sputtering. In addition, the gate spacer 17 may be formed of, for example, silicon nitride. The sacrificial gate electrode (not shown) may be formed of, for example, polysilicon, and the metal gate electrode 11 may be formed of a single layer or multiple layers including, for example, hafnium, zirconium, titanium, tantalum, aluminum and alloys thereof. have. The first insulating layer 5 may be formed of silicon oxide using, for example, a high density plasma deposition process. However, the above listed materials are exemplary and not limited thereto.

Subsequently, referring to FIG. 2, an etch stop layer 21 and an oxide layer 23 may be sequentially formed on the structure formed according to FIG. 1.

An etch stop layer 21 may be formed on the metal gate electrode 11 and the first insulating layer 5. The etch stop layer 21 may be formed of silicon nitride (SiN) using, for example, a chemical vapor deposition method.

The oxide layer 23 may be formed on the etch stop layer 21. For example, the oxide layer 23 may be formed of silicon oxide using a chemical vapor deposition method. In addition, the etch stop layer 21 and the oxide layer 23 may be formed in an in-situ manner.

3, a portion of the oxide layer 23 may be selectively removed to form the recess 31 so that the etch stop layer 21 is exposed.

Specifically, a photo-lithography process may be used. An oxide layer is formed by forming a photoresist pattern (not shown) on the oxide layer 23 except for a region overlapping with the metal gate electrode 11 and performing an anisotropic etching process using the photoresist pattern (not shown) as an etching mask. 23 may be etched to form a recess 31. The recess 31 may be formed in an area overlapping the metal gate electrode 11. After the etching process, the photoresist pattern (not shown) may be removed through an ashing and cleaning process.

Subsequently, referring to FIG. 4, the hard mask 41 may be formed to fill the recess 31 and overlap the metal gate electrode 11.

Specifically, an insulating layer (not shown) for a hard mask may be deposited to a thickness sufficient to fill the recess 31. For example, an insulating layer (not shown) for a hard mask may be formed of silicon nitride or silicon oxide using a chemical vapor deposition method, but is not limited thereto. After depositing an insulating layer (not shown) for the hard mask, the hard mask 41 may be formed by chemical mechanical polishing or etching back to expose the oxide layer 23. The etch back may be performed by dry etching using, for example, plasma. By the etch back, the hard mask 41 may be formed in a region overlapping with the metal gate electrode 11.

Subsequently, referring to FIG. 5, a second insulating layer 51 may be formed on the structure formed according to FIG. 4. For example, the second insulating layer 51 may be formed of silicon oxide using a chemical vapor deposition method, but is not limited thereto.

Subsequently, referring to FIG. 6, portions of the second insulating layer 51 and the oxide layer 23 may be selectively removed to form first contact holes 61 and 63.

Specifically, a photolithography process can be used. In order to form the first contact holes 61 and 63 between the neighboring metal gate electrodes 11, a photoresist pattern (not shown) is formed in the region overlapping with the metal gate electrodes 11 of the second insulating layer 51. And the first contact holes 61 and 63 may be formed by performing an etching process using a photoresist pattern (not shown) as an etching mask. That is, a portion of the second insulating layer 51 and the oxide layer 23 may be selectively removed so that a portion of the etch stop layer 21 positioned between the adjacent metal gate electrodes 11 is exposed. 63). For example, the etching process may be performed by dry etching using a CF _x -based gas having a high etching selectivity of the oxide film with respect to the nitride film. Therefore, as compared with the second insulating layer 51 and the oxide layer 23 formed of the oxide film, for example, the hard mask 41 and the etch stop layer 21 formed of the nitride film do not relatively etch, so that the second insulating layer Selective removal of part 51 and oxide layer 23 may be possible. After the first contact holes 61 and 63 are formed, the photoresist pattern (not shown) may be removed through an ashing and cleaning process.

As illustrated in FIG. 6, the sidewall profiles of the first contact holes 61 and 63 may have a constant slope, and specifically, may have a positive slope. In the present specification, the positive slope refers to the slope of the sidewall profile when the width of the first contact hole is widened from bottom to top. However, the present invention is not limited thereto, and the profile of the sidewalls of the first contact holes 61 and 63 may be formed vertically.

When the photoresist pattern (not shown) is formed without misalignment, the first contact hole 63 may be formed through the etching process without exposing the hard mask 41. Therefore, the problem that the metal gate electrode 11 is damaged by etching may not occur.

However, since the design rule in the semiconductor device is gradually reduced and the gap between the conducting lines such as the gate line is narrowed and the margin in the etching process is not sufficient, the photoresist pattern (not shown) is misaligned (not shown). misalignment) can cause problems. For example, when the photoresist pattern (not shown) is misaligned, the second insulating layer 51 disposed on the metal gate electrode 11 may be etched during the etching process. Although the etch stop layer 21 is positioned on the metal gate electrode 11 to protect the metal gate electrode 11, the thickness of the etch stop layer 21 may be limited in terms of securing performance of the semiconductor device. Therefore, when the etch stop layer 21 is removed during the etching process, the metal gate electrode 11 may be exposed and etched. As a result, when only the etch stop layer 21 is provided without the hard mask 41, it may be difficult to protect the metal gate electrode 11 during the etching process for forming the first contact hole.

When a misalignment of the photoresist pattern (not shown) occurs in the semiconductor manufacturing process including the hard mask 41, a first contact hole 61 exposing a portion of the hard mask 41 may be formed. . That is, the first contact hole 61 may be formed by overlapping a part of the hard mask 41. However, since the hard mask 41 is formed to overlap the metal gate electrode 11, the metal gate electrode 11 may be protected from etching even if a misalignment of the photoresist pattern occurs. Although the second insulating layer 51 positioned on the metal gate electrode 11 is etched during the etching process due to the misalignment of the photoresist pattern (not shown), the upper portion of the metal gate electrode 11 may be etched. Since the portion of the hard mask 41 is only exposed, and the etch stop layer 21 is positioned below the hard mask 41, the metal gate electrode 11 may be formed of the hard mask 41 and the etch stop layer ( Double protection).

Next, referring to FIG. 7, in order to form contact spacers 71 on the side surfaces of the first contact holes 61 and 63, insulation for the contact spacers is formed along the side surfaces and the bottom surfaces of the first contact holes 61 and 63. The layer can be conformally deposited. For example, the insulating layer for contact spacers may be formed of silicon nitride using a chemical vapor deposition method.

Subsequently, referring to FIG. 8, portions of the etch stop layer 21 and the first insulating layer 5 may be selectively removed so that the surface of the substrate 1 may be formed to form second contact holes 81 and 83. have. Unlike the process of forming the first contact holes 61 and 63 which perform the direct contact etching process, the second contact holes 81 and 83 may be formed by the self aligned contact (SAC) etching process. Can be.

Specifically, a photolithography process can be used. By forming a photoresist pattern (not shown) on the second insulating layer 51 and performing an etching process using the photoresist pattern (not shown), the contact spacer 71 and the gate spacer 17 as an etching mask. Second contact holes 81 and 83 may be formed. That is, the second contact holes 81 and 83 may be formed by selectively removing portions of the etch stop layer 21 and the first insulating layer 5 so that a part of the surface of the substrate 1 is exposed. The second contact holes 81 and 83 may be formed between neighboring gate spacers 17, and the second contact holes 81 and 83 may be formed to connect with the first contact holes 61 and 63. . After forming the second contact holes 81 and 83, the photoresist pattern (not shown) may be removed through ashing and cleaning processes.

By forming the contact spacers 71 on the side surfaces of the first contact holes 61 and 63, a small contact etch may be possible even if the design rule is reduced. By forming the contact spacers 71 on the side surfaces of the first contact holes 61 and 63 and using the contact spacers 71 as etch masks, the contact holes may be narrowed by the thickness of the contact spacers 71. In addition, even if a misalignment or etch skew occurs in the photoresist pattern, the contact spacer 71 may secure a margin of the etching process.

Further, when the second contact holes 81 and 83 are formed without the contact spacer 71, the second insulating layer 51 on the metal gate electrode 11 may be formed due to misalignment or etch skew of the photoresist pattern. Since the hard mask 41 and the etch stop layer 21 are also etched, there is a risk that the conductive material and the metal gate electrode 11 come into contact with each other during the formation of the conductive layer 91 to be described later. . Therefore, the contact spacer 71 can protect the metal gate electrode 11 together with the hard mask 41.

Subsequently, referring to FIG. 9, the conductive layer 91 may be formed by filling the first contact holes 61 and 63 and the second contact holes 81 and 83 with a conductive material.

Specifically, the conductive material constituting the conductive layer 91 may include conductive polysilicon, titanium nitride (TiN), and tungsten (W), but is not limited thereto. After the conductive layers 91 are formed in the first contact holes 61 and 63 and the second contact holes 81 and 83, the planarization process may be performed on the semiconductor device. The planarization process may use a chemical mechanical polishing process or an etch back process.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1: substrate 5: first insulating layer
11: metal gate electrode 13: barrier layer
15: gate insulating layer pattern 17: gate spacer
21: etch stop layer 23: oxide layer
31: recess 41: hard mask
51: second insulating layer 61, 63: first contact hole
71: contact spacer 81, 83: second contact hole
91: conductive layer

Claims (10)

Forming a metal gate electrode, a gate spacer positioned at both sides of the metal gate electrode, and a first insulating layer positioned at both sides of the gate spacer, on the substrate;
Forming an etch stop layer on the metal gate electrode and the first insulating layer,
Forming a hard mask on the etch stop layer to overlap the metal gate electrode,
Forming a second insulating layer on the etch stop layer and the hard mask,
And removing a portion of the second insulating layer to form a first contact hole so that the etch stop layer is exposed. The method of claim 1, wherein forming the hard mask
Forming an oxide layer on the etch stop layer,
A recess is formed by removing a portion of the oxide layer positioned in an area overlapping with the metal gate electrode of the oxide layer,
Depositing an insulating layer for the hard mask to fill the recess,
A method of manufacturing a semiconductor device comprising etching back the insulating layer for hard mask. The method of claim 2, further comprising forming a contact spacer on a side surface of the first contact hole.
The forming of the first contact hole may include removing a portion of the oxide layer to expose the etch stop layer. 4. The method of claim 3, wherein forming the contact spacers
An insulating layer for contact spacers is formed along side and bottom surfaces of the first contact hole,
And removing the insulating layer for the contact spacer located on the bottom surface of the first contact hole. 4. The second contact of claim 3, wherein a portion of the etch stop layer and the first insulating layer under the first contact hole is removed using the contact spacer as an etch mask so as to be connected to the first contact hole. The method for manufacturing a semiconductor device, further comprising forming a hole. The method of claim 5, further comprising forming a conductive layer by filling a conductive material in the first and second contact holes. The method of claim 1, wherein the first contact hole overlaps at least a portion of the hard mask. The method of claim 1, wherein an upper surface of the metal gate electrode, an upper surface of the gate spacer, and an upper surface of the first insulating layer are disposed on the same plane. Board;
A metal gate electrode formed on the substrate;
Gate spacers positioned at both sides of the metal gate electrode;
First insulating layers positioned at both sides of the gate spacer;
An etch stop layer formed on the metal gate;
A hard mask formed on the etch stop layer to overlap the metal gate electrode;
A second insulating layer formed on the hard mask; And
And a contact spacer formed on a side surface of the second insulating layer. The semiconductor device of claim 9, wherein one end of the contact spacer is in contact with an upper portion of the hard mask.

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