KR20120026965A - Clock management unit - Google Patents
Clock management unit Download PDFInfo
- Publication number
- KR20120026965A KR20120026965A KR1020110080642A KR20110080642A KR20120026965A KR 20120026965 A KR20120026965 A KR 20120026965A KR 1020110080642 A KR1020110080642 A KR 1020110080642A KR 20110080642 A KR20110080642 A KR 20110080642A KR 20120026965 A KR20120026965 A KR 20120026965A
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- KR
- South Korea
- Prior art keywords
- clock
- signal
- flip
- flop
- reset
- Prior art date
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- 230000003111 delayed effect Effects 0.000 claims abstract description 13
- 230000000630 rising effect Effects 0.000 claims description 19
- 230000001960 triggered effect Effects 0.000 claims description 5
- 238000013461 design Methods 0.000 abstract description 8
- 238000012360 testing method Methods 0.000 abstract description 6
- 238000012423 maintenance Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 101000821257 Homo sapiens Syncoilin Proteins 0.000 description 3
- 102100021919 Syncoilin Human genes 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000015607 signal release Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Abstract
Description
The present invention relates to a clock management apparatus, and more particularly, to a clock management apparatus capable of maintaining an interval between the time for releasing the reset signal and the time for which the clock signal is provided to an external circuit.
In order to meet the demand for digital chips with many functions and good performance, the processor core, a plurality of multimedia modules and various peripheral equipment modules are integrated in a single-chip application processor. Thus, many circuit modules are typically integrated in a processor, and the number of gates contained in the processor is increasing to more than tens of millions. Since many circuit modules in a chip have different clock sources, there are many asynchronous reset circuit modules, and they need to test for timing violations during post-design (e.g., during timing closure). Do.
More specifically, when testing a chip, a plurality of circuit modules in the chip may be reset in response to one or more reset signals. The reset signals may be high level or low level. Upon receiving the high level (or low level) reset signals, the circuit modules will be reset. If the rising edge (or falling edge) of the clock signal input to the circuit module occurs at or near the time the circuit module receives the reset signal, the reset signal may not be captured correctly by the circuit module. If the reset signal is not captured correctly by the circuit module, a timing violation may occur, which may cause instability in the circuit module and may cause an error in the test of the circuit module. Therefore, in the prior art, a method of synchronizing the reset signal in the clock signal to maintain the interval between the rising edge (or falling edge) time of the clock signal and the reset signal release time is proposed.
1 is a conventional circuit for synchronization of a reset signal and a clock signal, and FIG. 2 is a timing diagram of the circuit of FIG.
1 and 2, the
As shown, the reset signal RESET for resetting the
However, in the circuit as shown in FIG. 1, the clock signal CLK is supplied while the reset signal RESETn 'is supplied to the
An object of the present invention is to overcome the disadvantages of the prior art described above. In this regard, an exemplary embodiment of the present invention provides a clock management apparatus, in order to maintain the interval between the release time of the reset signal and the time when the clock signal is provided to the external circuit more than a predetermined time.
According to an embodiment of the present invention, a clock management device may include a first flip-flop, a second flip-flop, and a clock gate, wherein the first flip-flop is provided to an external circuit to reset the external circuit. The first D terminal to receive; A first clock terminal for receiving a clock signal; A second output terminal connected to a second D terminal of the second flip flop, wherein the second flip flop is connected to a first output terminal of the first flip flop; A second clock terminal for receiving the clock signal; And a second output terminal coupled to the enable terminal of the clock gate, wherein the clock gate comprises an enable terminal; A clock terminal for receiving the clock signal; A valid clock terminal coupled to the external circuit, providing the clock signal to the external circuit in accordance with an output of the second output terminal of the second flip-flop through a valid clock terminal, the reset in the external circuit After receiving the signal, no clock signal is provided to the external circuit during at least two periods of the clock signal.
Preferably, the clock management device may further include at least one flip-flop cascaded between the first flip-flop and the second flip-flop.
Preferably, the clock management device may further include an AND gate, which receives a reset signal and an enable signal and transmits the reset signal to the first D terminal of the first flip-flop according to the enable signal. The enable signal is a signal provided to an external circuit for operating the external circuit.
Advantageously, said reset signal and said enable signal are at a high level and if the AND gate receives said reset signal at a high level and said enable signal at a high level, said AND gate is at said high level. The reset signal is provided to the first D terminal of the first flip-flop.
Preferably each of the flip-flops may be a rising edge triggered D flip-flop.
Preferably, the interval between the time when the reset signal is released and the time when the clock signal is provided to an external circuit is maintained at least two cycles of the clock signal, which is a time violation when the release time of the reset signal approaches the clock signal. This is to prevent this from happening. During the reset signal is released and at least two periods of the clock signal, no clock signal is provided to the external circuit.
In accordance with another aspect of the present invention, a clock management device includes a delay unit configured to receive a reset signal and a clock signal for resetting an external circuit and to supply a delayed reset signal to an output unit; And an output unit configured to receive the clock signal and the delayed reset signal and supply a processed signal to an external circuit, and to the external circuit for at least two periods of the clock signal after the reset signal is received from the external circuit. It is characterized in that no clock signal is provided.
Preferably, the delay unit may include a cascaded first flip flop and a second flip flop.
Preferably, the delay unit further comprises at least one flip-flop cascaded between the first flip-flop and the second flip-flop.
Preferably, each of the flip-flops is a rising edge D triggered flip-flop.
The apparatus may further include an input unit configured to receive the reset signal and the enable signal, and to provide the delayed reset signal to the delay unit according to the enable signal.
Preferably, when the input unit receives the high level reset signal and the high level enable signal, the input unit provides the high level reset signal to the delay unit.
Thus, during post-design for the chip (e.g., tie closure), no test is needed to determine whether a sufficient interval is maintained between the release time of the reset signal and the clock signal, so the post design can be simplified. Can be.
The above described embodiments and / or other embodiments, features, and advantages will be more readily understood and apparent from the following detailed description of exemplary embodiments in detail in conjunction with the drawings.
1 is a schematic diagram showing a conventional circuit for synchronizing a reset signal and a clock signal.
2 is a timing diagram of the circuit of FIG. 1.
3 is a block diagram illustrating a clock management apparatus according to an embodiment of the present invention.
4 is a schematic diagram illustrating a circuit of a clock management apparatus according to an embodiment of the present invention.
FIG. 5 is a timing diagram of the clock management device of FIG. 4.
Exemplary embodiments will be described in more detail below with reference to the drawings. However, example embodiments may be configured in many different forms and should not be construed as limited to the embodiments set forth herein. Moreover, these embodiments are provided so that these disclosures will be more complete and will fully convey the scope of the exemplary embodiments to those skilled in the art. In the drawings, the relative sizes or sizes of layers and zones may be exaggerated for clarity. In the drawings, like reference numerals refer to like elements.
3 is a block diagram illustrating a
According to an exemplary embodiment, the
To this end, the
In order to reduce power consumption, the external circuit is generally activated to perform an operation by the enable signal EN input from the outside. Therefore, according to an exemplary embodiment, the enable signal EN may be provided to the
4 is a schematic diagram illustrating a circuit of a
The first flip-
The second flip-
As shown in FIG. 4, the
The truth table of
[Table 1]
In an exemplary embodiment, the
In FIG. 5, the reference signal SYNC0 refers to the output signal of the first flip-
In one embodiment of the present invention, two flip-flops constitute a
According to another embodiment of the present invention, the
According to an embodiment of the present invention, a first flip-flop includes a first D terminal for receiving a reset signal (eg, a reset signal provided from an AND gate), a first clock terminal for receiving a clock signal, and a second It may include a first output terminal connected to the second D terminal of the flip-flop. In addition, the reset signal may be provided to the first reset terminal of the first flip-flop.
An i-th flip-flop (where i is a natural number greater than 1 and smaller than n) is an i-th D terminal connected to an i-1 output terminal of an i-1 flip-flop among the first flip-flop to n-th flip-flop The i th clock terminal receiving the clock signal may include an i th output terminal connected to an i + 1 D terminal of an i + 1 flip-flop. The reset signal may be provided to the i th reset terminal of the i th flip flop.
The n-th flip-flop is an n-th D terminal connected to an n-th output terminal of the n-th flip-flop, an n-th clock terminal receiving a clock signal, and an n-th terminal connected to an enable terminal of the
Thus, the number of flip-flops included in the
According to an exemplary embodiment of the invention, the interval between the release time of the reset signal and the time that the clock signal is provided from the effective clock terminal of the clock gate (e.g., the time when the rising edge of the clock signal reaches an external circuit). Can be maintained in at least two periods of the clock signal, to prevent time violations that occur when the release time of the reset signal approaches the clock signal (e.g., the rising edge of the clock signal).
Thus, during at least two periods of the clock signal after the reset signal is released, the clock signal is not provided to the external circuit. Thus, during post-design (e.g., timing closure), no test is needed to determine whether a sufficient interval is maintained between the release time of the reset signal and the clock signal (e.g., the rising edge of the clock signal). Therefore, post design including timing closure and the like is simplified.
While exemplary embodiments of the invention have been shown and described, those skilled in the art are not intended to limit the scope of the claims, and that modifications and variations can be made without departing from the spirit and scope of the invention as defined in the claims. Will understand.
Claims (10)
A first flip-flop; A second flip-flop; Clock gates; And an AND gate,
The first flip-flop is connected to a first D terminal provided to an external circuit and receiving a reset signal for resetting the external circuit, a first clock terminal to receive a clock signal, and a second D terminal of the second flip flop. A first output terminal,
The second flip-flop includes the second D terminal, a second clock terminal for receiving the clock signal, and a second output terminal connected to the enable terminal of the clock gate.
The clock gate includes the enable terminal, a clock terminal for receiving the clock signal, and a valid clock terminal connected to the external circuit, wherein the clock gate includes the valid clock terminal according to an output of the second output terminal of the second flip-flop. Providing a clock signal to the external circuit through
The AND gate receives the reset signal and the enable signal, and provides the reset signal to the first D terminal of the first flip-flop according to the enable signal.
The enable signal is provided to the external circuit for operating the external circuit, and the clock signal is not provided to the external circuit for at least two periods of the clock signal after the reset signal is received from the external circuit. A clock management device characterized in that.
An output unit configured to receive the clock signal and the delayed reset signal and supply a processed signal to an external circuit,
And the clock signal is not provided to the external circuit for at least two periods of the clock signal after the reset signal is received from the external circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/228,814 US8514004B2 (en) | 2010-09-10 | 2011-09-09 | Clock management unit and method of managing a clock signal |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010281126.2 | 2010-09-10 | ||
CN201020081126 | 2010-09-10 |
Publications (1)
Publication Number | Publication Date |
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KR20120026965A true KR20120026965A (en) | 2012-03-20 |
Family
ID=46132615
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020110080642A KR20120026965A (en) | 2010-09-10 | 2011-08-12 | Clock management unit |
Country Status (1)
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KR (1) | KR20120026965A (en) |
-
2011
- 2011-08-12 KR KR1020110080642A patent/KR20120026965A/en not_active Application Discontinuation
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