KR20120026965A

KR20120026965A - Clock management unit

Info

Publication number: KR20120026965A
Application number: KR1020110080642A
Authority: KR
Inventors: 웨이콩 후
Original assignee: 삼성전자주식회사
Priority date: 2010-09-10
Filing date: 2011-08-12
Publication date: 2012-03-20

Abstract

PURPOSE: A clock management unit is provided to simplify post design by eliminating a test for determining the maintenance of enough intervals between a release time and clock signal of a reset signal in post-design for a chip. CONSTITUTION: A clock management unit(100) is used for driving an external circuit like various circuit modules in a chip. The clock management unit offers clock signals to the external circuit from reset signals for resetting the external circuit at least after two cyclical intervals of the clock signal. A delay unit(110) receives the clock signal and the reset signal. The delay unit outputs a delayed reset signal. An output unit(120) receives the clock signal and the delayed reset signal. The output unit offers the clock signals to the external circuit according to a delayed reset signal. An input unit(130) receives the reset signal and an enable signal.

Description

Clock Management Unit

The present invention relates to a clock management apparatus, and more particularly, to a clock management apparatus capable of maintaining an interval between the time for releasing the reset signal and the time for which the clock signal is provided to an external circuit.

In order to meet the demand for digital chips with many functions and good performance, the processor core, a plurality of multimedia modules and various peripheral equipment modules are integrated in a single-chip application processor. Thus, many circuit modules are typically integrated in a processor, and the number of gates contained in the processor is increasing to more than tens of millions. Since many circuit modules in a chip have different clock sources, there are many asynchronous reset circuit modules, and they need to test for timing violations during post-design (e.g., during timing closure). Do.

More specifically, when testing a chip, a plurality of circuit modules in the chip may be reset in response to one or more reset signals. The reset signals may be high level or low level. Upon receiving the high level (or low level) reset signals, the circuit modules will be reset. If the rising edge (or falling edge) of the clock signal input to the circuit module occurs at or near the time the circuit module receives the reset signal, the reset signal may not be captured correctly by the circuit module. If the reset signal is not captured correctly by the circuit module, a timing violation may occur, which may cause instability in the circuit module and may cause an error in the test of the circuit module. Therefore, in the prior art, a method of synchronizing the reset signal in the clock signal to maintain the interval between the rising edge (or falling edge) time of the clock signal and the reset signal release time is proposed.

1 is a conventional circuit for synchronization of a reset signal and a clock signal, and FIG. 2 is a timing diagram of the circuit of FIG.

1 and 2, the reset synchronizer 10 includes a first D flip-flop 11 and a second D flip-flop 12. The clock signal CLK drives the first D flip-flop 11 and the second D flip-flop 12. The pull-up signal PULL-UP or the pull-down signal (not shown) is provided to the first D flip-flop 11. External circuit 20 may include flip-flops, logic, memories, and / or other types of circuits. The clock signal CLK drives the external circuit 20.

As shown, the reset signal RESET for resetting the external circuit 20 is not directly supplied to the external circuit 20 but is supplied to the reset synchronizer 10. The reset signal RESET changes from the reset synchronizer 10 to the reset signal RESETn via the inverter, which is supplied to the D flip-flops 11 and 12. The reset synchronizer 10 outputs a reset signal RESETn 'according to the reset signal RESET and the clock signal CLK, which are synchronized with the clock signal CLK. As described in FIG. 2, a sufficient interval is maintained between the synchronized reset signal RESETn 'and the release time of the rising edge of the clock signal CLK, so that timing violations can be prevented. The violation range is shown in FIG. If the release time of the reset signal supplied to the external circuit 20 is in the violation range, a timing violation may occur in the external circuit 20.

However, in the circuit as shown in FIG. 1, the clock signal CLK is supplied while the reset signal RESETn 'is supplied to the external circuit 20. Thus, during post-design, for example during timing closure, a specialized Post-Static Timing Analysis (Post-STA) is required for each module including the conventional circuit shown in FIG. 1, which is a synchronized reset. This is to determine whether a sufficient interval is maintained between the release time of the signal RESETn 'and the rising edge of the clock signal CLK.

An object of the present invention is to overcome the disadvantages of the prior art described above. In this regard, an exemplary embodiment of the present invention provides a clock management apparatus, in order to maintain the interval between the release time of the reset signal and the time when the clock signal is provided to the external circuit more than a predetermined time.

According to an embodiment of the present invention, a clock management device may include a first flip-flop, a second flip-flop, and a clock gate, wherein the first flip-flop is provided to an external circuit to reset the external circuit. The first D terminal to receive; A first clock terminal for receiving a clock signal; A second output terminal connected to a second D terminal of the second flip flop, wherein the second flip flop is connected to a first output terminal of the first flip flop; A second clock terminal for receiving the clock signal; And a second output terminal coupled to the enable terminal of the clock gate, wherein the clock gate comprises an enable terminal; A clock terminal for receiving the clock signal; A valid clock terminal coupled to the external circuit, providing the clock signal to the external circuit in accordance with an output of the second output terminal of the second flip-flop through a valid clock terminal, the reset in the external circuit After receiving the signal, no clock signal is provided to the external circuit during at least two periods of the clock signal.

Preferably, the clock management device may further include at least one flip-flop cascaded between the first flip-flop and the second flip-flop.

Preferably, the clock management device may further include an AND gate, which receives a reset signal and an enable signal and transmits the reset signal to the first D terminal of the first flip-flop according to the enable signal. The enable signal is a signal provided to an external circuit for operating the external circuit.

Advantageously, said reset signal and said enable signal are at a high level and if the AND gate receives said reset signal at a high level and said enable signal at a high level, said AND gate is at said high level. The reset signal is provided to the first D terminal of the first flip-flop.

Preferably each of the flip-flops may be a rising edge triggered D flip-flop.

Preferably, the interval between the time when the reset signal is released and the time when the clock signal is provided to an external circuit is maintained at least two cycles of the clock signal, which is a time violation when the release time of the reset signal approaches the clock signal. This is to prevent this from happening. During the reset signal is released and at least two periods of the clock signal, no clock signal is provided to the external circuit.

In accordance with another aspect of the present invention, a clock management device includes a delay unit configured to receive a reset signal and a clock signal for resetting an external circuit and to supply a delayed reset signal to an output unit; And an output unit configured to receive the clock signal and the delayed reset signal and supply a processed signal to an external circuit, and to the external circuit for at least two periods of the clock signal after the reset signal is received from the external circuit. It is characterized in that no clock signal is provided.

Preferably, the delay unit may include a cascaded first flip flop and a second flip flop.

Preferably, the delay unit further comprises at least one flip-flop cascaded between the first flip-flop and the second flip-flop.

Preferably, each of the flip-flops is a rising edge D triggered flip-flop.

The apparatus may further include an input unit configured to receive the reset signal and the enable signal, and to provide the delayed reset signal to the delay unit according to the enable signal.

Preferably, when the input unit receives the high level reset signal and the high level enable signal, the input unit provides the high level reset signal to the delay unit.

Thus, during post-design for the chip (e.g., tie closure), no test is needed to determine whether a sufficient interval is maintained between the release time of the reset signal and the clock signal, so the post design can be simplified. Can be.

The above described embodiments and / or other embodiments, features, and advantages will be more readily understood and apparent from the following detailed description of exemplary embodiments in detail in conjunction with the drawings.
1 is a schematic diagram showing a conventional circuit for synchronizing a reset signal and a clock signal.
2 is a timing diagram of the circuit of FIG. 1.
3 is a block diagram illustrating a clock management apparatus according to an embodiment of the present invention.
4 is a schematic diagram illustrating a circuit of a clock management apparatus according to an embodiment of the present invention.
FIG. 5 is a timing diagram of the clock management device of FIG. 4.

Exemplary embodiments will be described in more detail below with reference to the drawings. However, example embodiments may be configured in many different forms and should not be construed as limited to the embodiments set forth herein. Moreover, these embodiments are provided so that these disclosures will be more complete and will fully convey the scope of the exemplary embodiments to those skilled in the art. In the drawings, the relative sizes or sizes of layers and zones may be exaggerated for clarity. In the drawings, like reference numerals refer to like elements.

3 is a block diagram illustrating a clock management apparatus 100 according to an exemplary embodiment.

According to an exemplary embodiment, the clock management apparatus 100 may receive a clock signal CLK, which is used to drive external circuits such as various circuit modules inside the chip. The reset signal RESET may reset an external circuit and may be simultaneously supplied to the clock management device 100 and the external circuit. The clock management device 100 is provided at intervals of at least two cycles of the clock signal CLK from the supply of the reset signal RESET to the external circuit (ie, the release time of the reset signal RESET) for the reset of the external circuit. The clock signals are then provided to external circuitry. That is, the interval between the release time of the reset signal RESET and the clock signal time provided to the external circuit (for example, the time when the rising edge of the clock signal reaches the external circuit) is at least two cycles of the clock signal CLK. This is to prevent timing violations that occur when the release time of the reset signal RESET approximates a clock signal provided to an external circuit (eg, the rising edge of the clock signal).

To this end, the clock management device 100 may include a delay device 110 and an output device 120 as shown in FIG. 3. The delay apparatus 110 may receive a clock signal CLK and a reset signal RESET. The delay apparatus 110 may delay the reset signal RESET. Thereafter, the delay apparatus 110 may output the delayed reset signal RESETn '. The output device 120 may receive the clock signal CLK and the delayed reset signal RESETn '. The output device 120 may provide clock signals to an external circuit according to the delayed reset signal RESETn '. Therefore, after the external circuit receives the reset signal RESETn ', the clock signal is not provided to the external circuit in a period up to at least two cycles of the clock signal CLK. Thus, timing violations can be prevented.

In order to reduce power consumption, the external circuit is generally activated to perform an operation by the enable signal EN input from the outside. Therefore, according to an exemplary embodiment, the enable signal EN may be provided to the clock management apparatus 100 at the same time. In this case, the clock management apparatus 100 may include an input device 130. The input device 130 may receive a reset signal RESET and an enable signal EN, and may provide a reset signal RESET to the delay device 110 according to the received enable signal EN. . Therefore, when the enable signal EN is not received and the external circuit is inactivated, the clock management apparatus 100 does not operate without the enable signal EN, and thus power consumption may be reduced.

4 is a schematic diagram illustrating a circuit of a clock management apparatus 100 according to an exemplary embodiment. 5 is a timing diagram of the clock management apparatus 100 of FIG. 4. 4 schematically shows a circuit configuration of the clock management apparatus 100; However, it will be apparent to those skilled in the art to use other circuit configurations to perform the clock management apparatus 100 according to an exemplary embodiment.

Delay device 110 may include flip-flops, such as a D flip-flop. In order to delay the reset signal RESET for a desired time, the delay device 110 may include at least two flip-flops 111 and 112. For convenience, the delay device 110 including two flip-flops 111 and 112 is shown in FIG. 4. In an exemplary embodiment of the invention, flip-flops 111 and 112 may be rising edge triggered D flip-flops.

The first flip-flop 111 is a first D terminal that receives the reset signal RESET, a first clock terminal that receives the clock signal CLK, and a first D terminal connected to the second D terminal of the second flip-flop 112. It may include an output terminal. In addition, the reset signal RESET may be provided to the first reset terminal of the first flip-flop 111.

The second flip-flop 112 is a second D terminal connected to the first output terminal of the first flip-flop 111, a second clock terminal receiving the clock signal CLK, and a second terminal connected to the output device 120. It may include an output terminal. In addition, the reset signal RESET may be provided to the second reset terminal of the second flip-flop 112.

As shown in FIG. 4, the output device 120 may include a clock gate 121. The clock gate 121 includes an active terminal connected to the second output terminal of the second flip-flop 112, a clock terminal receiving the clock signal CLK, a scan active terminal receiving the scan activation signal SE, and an external circuit. It may include a valid clock terminal to be connected. The clock gate 121 may provide a clock signal to an external circuit through an effective clock terminal according to the output of the second flip-flop 112 from the second output terminal.

The truth table of clock gate 121 is shown in Table 1.

[Table 1]

In an exemplary embodiment, the input device 130 may include an AND gate 131. The AND gate 131 may receive the reset signal RESET and the enable signal EN, and according to the enable signal EN, the reset signal RESET may be applied to the first D terminal of the first flip-flop 111. RESET). In this case, the reset signal RESET and the enable signal EN may be at a high level. When the AND gate 131 receives the high level reset signal RESET and the high level enable signal EN, the AND gate 131 is at a high level at the first D terminal of the first flip-flop 111. Provide a reset signal (RESET). Therefore, when the external circuit is not operated because the high level enable signal EN is not received, the AND gate 131 does not provide the reset signal RESET to the delay device 110, and thus, power consumption is reduced. Decreases.

In FIG. 5, the reference signal SYNC0 refers to the output signal of the first flip-flop 111, the reference signal SYNC1 refers to the output signal of the second flip-flop 112, and the reference signal ECK is Refers to an output signal of the clock gate 121. As shown in FIG. 5, when the rising edge of the clock signal CLK reaches the first flip-flop 111, the first flip-flop 111 may output the high level signal SYNC0, which is a specific time with respect to the reset signal RESET. This is to delay the signal SYNC0 for. For example, the first flip-flop 111 may delay the signal SYNC0 for 0.5 period of the clock signal CLK with respect to the reset signal RESET, and the delayed time may be reached by the reset signal RESET. At one time, it depends on the state of the clock signal CLK received by the first flip-flop 111. When the rising edge of the clock signal CLK reaches the second flip-flop 112, the second flip-flop 112 may output the high level signal SYNC1, which is associated with the signal SYNC0 during one period of the clock signal CLK. This is to delay the signal SYNC1. Then, the clock gate 121 starts outputting the signal ECK when the next rising edge of the clock signal CLK is reached, which is due to the characteristics of the gate clock 121 as described above. Therefore, the time interval between the time when the reset signal RESET is released and the clock signal is applied to the external circuit (for example, the rising edge of the signal ECK output from the effective clock terminal of the clock gate 121) ( Tmargin may be greater than or equal to two periods of the clock signal CLK. Therefore, the release of the reset signal RESET reaches a stable state before the rising edge of the clock signal provided to the external circuit, whereby timing violation can be prevented.

In one embodiment of the present invention, two flip-flops constitute a delay device 110 that performs synchronization, thereby preventing metastability. In particular, the reset signal RESET is asynchronous to the first flip-flop 111, that is, the arrival time of the reset signal RESET is uncertain, and therefore, the arrival time of the reset signal RESET is the flip-flop 111. If the timing requirement is not satisfied, the flip-flop 111 is metastable and makes the output value uncertain. Accordingly, the second flip-flop 112 may be cascaded to prevent further transmission of uncertain values.

According to another embodiment of the present invention, the delay device 110 may include n flip-flops, that is, from the first flip-flop to the n-th flip-flop (where n is two or more). Natural numbers)

According to an embodiment of the present invention, a first flip-flop includes a first D terminal for receiving a reset signal (eg, a reset signal provided from an AND gate), a first clock terminal for receiving a clock signal, and a second It may include a first output terminal connected to the second D terminal of the flip-flop. In addition, the reset signal may be provided to the first reset terminal of the first flip-flop.

An i-th flip-flop (where i is a natural number greater than 1 and smaller than n) is an i-th D terminal connected to an i-1 output terminal of an i-1 flip-flop among the first flip-flop to n-th flip-flop The i th clock terminal receiving the clock signal may include an i th output terminal connected to an i + 1 D terminal of an i + 1 flip-flop. The reset signal may be provided to the i th reset terminal of the i th flip flop.

The n-th flip-flop is an n-th D terminal connected to an n-th output terminal of the n-th flip-flop, an n-th clock terminal receiving a clock signal, and an n-th terminal connected to an enable terminal of the clock gate 121. It may include an output terminal. In addition, the reset signal may be provided to the nth reset terminal of the nth flip-flop.

Thus, the number of flip-flops included in the delay apparatus 110 may be determined as needed, so that a predetermined interval between the release time of the reset signal and the time that the clock signal is provided externally, for example, at least a clock It can be maintained in two cycles of the signal.

According to an exemplary embodiment of the invention, the interval between the release time of the reset signal and the time that the clock signal is provided from the effective clock terminal of the clock gate (e.g., the time when the rising edge of the clock signal reaches an external circuit). Can be maintained in at least two periods of the clock signal, to prevent time violations that occur when the release time of the reset signal approaches the clock signal (e.g., the rising edge of the clock signal).

Thus, during at least two periods of the clock signal after the reset signal is released, the clock signal is not provided to the external circuit. Thus, during post-design (e.g., timing closure), no test is needed to determine whether a sufficient interval is maintained between the release time of the reset signal and the clock signal (e.g., the rising edge of the clock signal). Therefore, post design including timing closure and the like is simplified.

While exemplary embodiments of the invention have been shown and described, those skilled in the art are not intended to limit the scope of the claims, and that modifications and variations can be made without departing from the spirit and scope of the invention as defined in the claims. Will understand.

Claims

In the clock management apparatus,
A first flip-flop; A second flip-flop; Clock gates; And an AND gate,
The first flip-flop is connected to a first D terminal provided to an external circuit and receiving a reset signal for resetting the external circuit, a first clock terminal to receive a clock signal, and a second D terminal of the second flip flop. A first output terminal,
The second flip-flop includes the second D terminal, a second clock terminal for receiving the clock signal, and a second output terminal connected to the enable terminal of the clock gate.
The clock gate includes the enable terminal, a clock terminal for receiving the clock signal, and a valid clock terminal connected to the external circuit, wherein the clock gate includes the valid clock terminal according to an output of the second output terminal of the second flip-flop. Providing a clock signal to the external circuit through
The AND gate receives the reset signal and the enable signal, and provides the reset signal to the first D terminal of the first flip-flop according to the enable signal.
The enable signal is provided to the external circuit for operating the external circuit, and the clock signal is not provided to the external circuit for at least two periods of the clock signal after the reset signal is received from the external circuit. A clock management device characterized in that.

The clock management apparatus of claim 1, further comprising at least one flip-flop cascaded between the first flip-flop and the second flip-flop.

The logic gate of claim 1, wherein when the reset signal and the enable signal are at a high level, and the AND gate receives the reset signal at a high level and the enable signal at a high level, the AND gate is set to a high level. And providing the reset signal to the first D terminal of the first flip-flop.

The apparatus of claim 1, wherein each of the flip-flops is a rising edge D triggered flip-flop.

A delay unit for receiving a reset signal and a clock signal for resetting an external circuit and supplying a delayed reset signal to an output unit; And
An output unit configured to receive the clock signal and the delayed reset signal and supply a processed signal to an external circuit,
And the clock signal is not provided to the external circuit for at least two periods of the clock signal after the reset signal is received from the external circuit.

The clock management apparatus of claim 5, wherein the delay unit comprises a cascaded first flip flop and a second flip flop.

The clock management apparatus of claim 6, wherein the delay unit further comprises at least one flip-flop cascaded between the first flip-flop and the second flip-flop.

7. The clock management apparatus of claim 6, wherein each of the flip-flops is a rising edge D triggered flip-flop.

The clock management apparatus of claim 5, further comprising an input unit configured to receive the reset signal and the enable signal, and to provide the delayed reset signal to the delay unit according to the enable signal.

The apparatus of claim 9, wherein the input unit provides the high level reset signal to the delay unit when the input unit receives the high level reset signal and the high level enable signal.