CN212342250U - LED drive circuit, display device and display system - Google Patents
LED drive circuit, display device and display system Download PDFInfo
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- CN212342250U CN212342250U CN202021713660.1U CN202021713660U CN212342250U CN 212342250 U CN212342250 U CN 212342250U CN 202021713660 U CN202021713660 U CN 202021713660U CN 212342250 U CN212342250 U CN 212342250U
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Abstract
The application provides an LED drive circuit, a display device and a display system. The LED drive circuit includes: a driving unit including a plurality of data channels; the control unit is arranged in the LED drive circuit, and the control unit controls all the data channels to be in a closed state when detecting that the data in all the data channels are 0 within a preset time period, wherein the preset time period is determined according to the time length of an external input signal input into the LED drive circuit.
Description
Technical Field
The application relates to the field of LED display, in particular to an LED driving circuit, a display device and a display system.
Background
Currently, a Static Random-Access Memory (SRAM) is arranged in an LED driving chip and can store two frames of data, where one frame is currently displayed data and the other frame is data to be displayed in the next frame, and the chip realizes frame change by receiving a frame synchronization signal. The existing dynamic energy-saving method determines whether to perform dynamic energy saving by detecting whether the next frame of display data is all 0, and the display data is 0 to indicate that the corresponding LED is in a closed state, that is, the corresponding LED is in a black screen state, and if the next frame of display data is all 0, the method enters the dynamic energy-saving state, that is, the data channel corresponding to the LED in the black screen state is closed, so as to realize the black screen energy saving.
However, some conventional LED constant current driving chips have no SRAM inside, and the system side does not send a frame synchronization signal, so how to implement dynamic power saving in such LED constant current driving chips becomes a problem to be solved.
SUMMERY OF THE UTILITY MODEL
The main purpose of the present application is to provide an LED driving circuit, a display device and a display system, so as to solve the problem that dynamic energy saving cannot be realized in an LED constant current driving chip without an SRAM inside in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided an LED driving circuit including: a driving unit including a plurality of data channels; and the control unit is electrically connected with the driving unit and controls all the data channels to be in a closed state under the condition that the control unit detects that the data in all the data channels are 0 within a preset time period, wherein the preset time period is determined according to the duration of an external input signal input into the LED driving circuit.
Optionally, the control unit comprises: the detection module is electrically connected with the driving unit and used for detecting whether the data in all the data channels is 0 or not; the counter module is electrically connected with the detection module; and the signal generation module is respectively electrically connected with the detection module and the counter module and is provided with an output end, the output end outputs a state signal, and the state signal is used for controlling all the data channels to be in a closed state under the condition that the data in all the data channels is 0.
Optionally, the signal generating module has a first input end and a second input end, the counter module has a first input end and an output end, the output end of the detecting module is electrically connected to the first input end of the signal generating module and the first input end of the counter module, respectively, and the output end of the counter module is electrically connected to the second input end of the signal generating module.
Optionally, the driving unit further includes a reference current generating module and a current output module, the reference current generating module is electrically connected to the signal generating module and the current output module, respectively, and the state signal controls the reference current generating module to be in a closed state when data in all the data channels is 0.
Optionally, the drive unit further comprises: the shift register is provided with a first input end, a second input end and an output end, wherein the first input end is used for inputting serial data, and the second input end is used for inputting an external clock signal; the input end of the first inverter is used for inputting a latch enabling signal; the input end of the second inverter is used for inputting a channel enabling signal; the data latch is provided with a first input end, a second input end, a third input end and an output end, the data output by the output end of the data latch is a plurality of data in the data channel, the output end of the data latch is respectively electrically connected with the input end of the detection module and the input end of the current output module, the first input end of the data latch is electrically connected with the output end of the first phase inverter, the second input end of the data latch is electrically connected with the output end of the shift register, and the third input end of the data latch is electrically connected with the output end of the second phase inverter.
Optionally, the driving unit further includes a third inverter, the counter module further has a second input end, an input end of the third inverter is electrically connected to an output end of the first inverter, and an output end of the third inverter is electrically connected to the second input end of the counter module.
Optionally, the current output module has a first input end, a second input end, and an output end, the first input end of the current output module is electrically connected to the output end of the data latch, the second input end of the current output module is electrically connected to the output end of the second inverter, and the output end of the current output module outputs multiple paths of constant current signals.
Optionally, the driving unit further includes a first in-phase buffer and a second in-phase buffer, an input end of the first in-phase buffer is used for inputting the serial data, an output end of the first in-phase buffer is electrically connected to a first input end of the shift register, an input end of the second in-phase buffer is used for inputting the external clock signal, and an output end of the second in-phase buffer is electrically connected to a second input end of the shift register.
Optionally, the detection module comprises a nor gate.
According to another aspect of the present application, there is provided a display device, comprising an LED driving circuit and an LED display screen, wherein the LED driving circuit is any one of the LED driving circuits.
According to still another aspect of the present application, there is provided a display system including an LED driving circuit, the LED driving circuit being any one of the LED driving circuits.
By applying the technical scheme, the control unit is arranged in the LED driving circuit, when the control unit detects that the data in all the data channels are 0 within the preset time period, namely the driven LED is in a black screen state, all the data channels are controlled to be in a closed state, so that the power consumption of the driving unit is reduced, and dynamic energy conservation is realized.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a schematic diagram of an LED driver circuit according to an embodiment of the present application;
FIG. 2 shows another LED driver circuit schematic according to an embodiment of the present application; and
fig. 3 shows a schematic diagram of a control unit according to an embodiment of the application.
Wherein the figures include the following reference numerals:
01. a drive unit; 10. a data channel; 11. a reference current generating module; 12. a current output module; 13. a shift register; 14. a first inverter; 15. a second inverter; 16. a data latch; 17. a third inverter; 18. a first in-phase buffer; 19. a second in-phase buffer; 02. a control unit; 20. a detection module; 21. a counter module; 210. a first D flip-flop; 22. a signal generation module; 220. a third in-phase buffer; 221. and a second D flip-flop.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, dynamic energy saving cannot be achieved in an LED constant current driving chip without an SRAM in the prior art, and in order to solve the above technical problems, embodiments of the present application provide an LED driving circuit, a display device, and a display system.
According to an embodiment of the present application, there is provided an LED driving circuit.
Fig. 1 is a schematic diagram of an LED driving circuit according to an embodiment of the present application. As shown in fig. 1, the LED driving circuit includes:
a driving unit 01 including a plurality of data channels 10, data in the data channels being used to drive the LEDs;
and a control unit 02 electrically connected to the driving unit 01, wherein when the control unit 02 detects that data in all the data channels 10 is 0 within a predetermined time period, all the data channels 10 are controlled to be in a closed state, and the predetermined time period is obtained by counting an external input signal, and is determined according to a time length of an external input signal input to the LED driving circuit.
In the above scheme, by setting the control unit in the LED driving circuit, the control unit detects that data in all data channels is 0 within a predetermined time period, that is, the driven LED is in a black screen state, and controls all data channels to be in a closed state, so as to reduce power consumption of the driving unit, so as to achieve dynamic energy saving, the driving unit is equivalent to an LED constant current driving chip without an SRAM inside, that is, the LED driving circuit of the present scheme achieves dynamic energy saving in the LED constant current driving chip without an SRAM inside, and an external input signal is a signal other than the LED driving circuit, so that resources of the LED driving circuit are not occupied, and resources of the driving unit are not occupied.
Specifically, the external input signal is a signal other than the LED driving circuit, and the external input signal is not on the LED driving circuit or the driving unit, that is, not on the LED constant current driving chip without the SRAM inside, and thus does not occupy the resource of the chip itself, and the resource of the chip is saved.
Alternatively, the predetermined time period may be determined according to a time period of an external input signal input to the LED driving circuit, and specifically, the predetermined time period may be obtained by counting a rising edge, a falling edge, a high level, and a low level of the external input signal.
Specifically, the predetermined time period includes, but is not limited to, 5s, 10s, and 15s, and the predetermined time period may be adjusted according to actual conditions.
Specifically, the external input signal may be a latch enable signal, an external input clock signal, a channel enable signal, and the like.
The LED constant current driving chip without the SRAM therein is referred to as a chip without the SRAM therein, so that a control unit needs to be added to achieve dynamic energy saving.
Specifically, the number of the data channels is one of the following: 8, 16, 32, 64, certainly, the number of the data channels can be set according to actual conditions, for example, one LED display screen includes 64 LEDs, the 64 LEDs can be averagely divided into 8 parts, each part has 8 LEDs, 8 driving units are set, each driving unit includes 8 data channels, and data in each data channel drives one LED, so that the driving of the whole LED display screen is realized.
In an embodiment of the present application, as shown in fig. 2, the control unit 02 includes a detection module 20, a counter module 21, and a signal generation module 22, where the detection module 20 is electrically connected to the driving unit 01 and is configured to detect whether data in all the data channels 10 is 0; the counter module 21 is electrically connected with the detection module 20; the signal generating module 22 is electrically connected to the detecting module 20 and the counter module 21, respectively, and has an output terminal outputting a status signal PD _ STAT, in the case where the data in all the data lanes 10 is 0, the status signal PD _ STAT is used to control all the data lanes 10 to be in the off state, in case the detection module 20 detects that the data in all the data channels 10 is 0, the counter module 21 starts counting, in the case where the data in all of the above data channels 10 is still 0 within the predetermined time period timed by the counter module 21, that is, the data of the data channel 10 is in an idle state in a predetermined time period, and in order to save energy, at this time, the signal generating module 22 outputs a status signal PD _ STAT, where the status signal PD _ STAT is used to control all the data channels 10 to be in an off state to save energy.
In another embodiment of the present application, as shown in fig. 2, the signal generating module 22 has a first input terminal and a second input terminal, the counter module 21 has a first input terminal and an output terminal, the output terminal of the detecting module 20 is electrically connected to the first input terminal of the signal generating module 22 and the first input terminal of the counter module 21, the output terminal of the counter module 21 is electrically connected to the second input terminal of the signal generating module 22, the output signal of the output terminal of the detecting module 20 is PD _ RSLT, when the detecting module 20 detects that the data in all the data channels 10 is 0, the counter module 21 starts timing, when the data in all the data channels 10 is still 0 within a predetermined time period timed by the counter module 21, that is, when the data in the data channels 10 is idle within the predetermined time period, in order to save energy, at this time, the signal generating module 22 outputs a status signal PD _ STAT, and the status signal PD _ STAT controls all the data channels 10 to be in a closed state to save energy.
In yet another embodiment of the present application, as shown in fig. 2, the driving unit 01 further includes a reference current generating module 11 and a current output module 12, the reference current generating module 11 is electrically connected to the signal generating module 22 and the current output module 12, the status signal PD _ STAT controls the reference current generating module 11 to be in an off state when data in all the data channels 10 is 0, the counter module 21 starts timing when the detection module 20 detects that data in all the data channels 10 is 0, the signal generating module 22 outputs the status signal PD _ STAT when data in all the data channels 10 is still 0 within a predetermined time period timed by the counter module 21, that is, data in the data channels 10 is in an idle state within the predetermined time period, so as to save energy, the state signal PD _ STAT controls the reference current generation module 11 to be in an off state, that is, the reference current generation module 11 is controlled not to generate the reference current, that is, the current output module 12 is controlled not to generate the constant current outputs IOUT0 to IOUT15, so as to achieve dynamic energy saving.
In one embodiment of the present application, as shown in fig. 2 and fig. 3, the driving unit 01 further includes a shift register 13, a first inverter 14, a second inverter 15, and a data latch 16, where the shift register 13 has a first input terminal, a second input terminal, and an output terminal, the first input terminal is used for inputting serial data SIN, and the second input terminal is used for inputting an external clock signal CLK 2; an input terminal of the first inverter 14 is used for inputting a latch enable signal LE; the input end of the second inverter 15 is used for inputting a channel enable signal OE; a data latch 16 having a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the data output from the output terminal of the data latch 16 is the data in the plurality of data channels 10, the output terminal of the data latch 16 is electrically connected to the input terminal of the detection module 20 and the input terminal of the current output module 12, the first input terminal of the data latch 16 is electrically connected to the output terminal of the first inverter 14, the second input terminal of the data latch 16 is electrically connected to the output terminal of the shift register 13, the third input terminal of the data latch 16 is electrically connected to the output terminal of the second inverter 15, the serial data SIN input from the first input terminal of the shift register 13 is input to the data latch 16 through the shift register 13 by the input of the external clock signal CLK2, the data latch 16 latches the data outputted from the shift register 13 and outputs the latched data, the data outputted from the output terminal of the data latch 16 is the data in the plurality of data channels 10, and when the detection module 20 detects that the data in all the data channels 10 is 0, that is, when all of Data0 to Data15 in FIG. 3 are 0, the counter module 21 starts counting time, in the case where the data in all of the above data channels 10 is still 0 within the predetermined time period timed by the counter module 21, namely, the data of the data channel 10 is in an idle state in a predetermined time period, and is energy saving, at this time, the signal generating module 22 outputs the state signal PD _ STAT, and the state signal PD _ STAT controls the reference current generating module 11 and the current output module 12 to be in an off state, that is, the current output module 12 is controlled not to generate constant current output, so as to realize dynamic energy saving.
In a more specific embodiment, as shown in fig. 2, the driving unit 01 further includes a third inverter 17, the counter module 21 further has a second input terminal, an input terminal of the third inverter 17 is electrically connected to the output terminal of the first inverter 14, an output terminal of the third inverter 17 is electrically connected to the second input terminal of the counter module 21, the latch enable signal LE input from the input terminal of the first inverter 14 outputs an LE _ BUF signal after two inversions of the first inverter 14 and the third inverter 17, where the LE _ BUF signal is a clock signal of the counter module 21.
In a specific embodiment, the second input terminal of the counter module is electrically connected to the output terminal of the second inverter, i.e. the channel enable signal serves as the clock signal of the counter module.
In a specific embodiment, the second input terminal of the counter module is electrically connected to the output terminal of the second in-phase buffer, i.e. the external clock signal is used as the clock signal of the counter module.
In an embodiment of the present application, as shown in fig. 3, the detection module 20 includes a nor gate, where the nor gate in fig. 3 is a 16-input nor gate with one output, and of course, the detection module 20 may also be other types of logic gate circuits, and may be a single logic gate circuit or a combination of multiple logic gate circuits, as long as the output is 1 when all input signals are 0, and the counter module 21 starts to count time when the output is 1.
In an embodiment of the present application, as shown in fig. 3, the signal generating module 22 includes a third in-phase buffer 220, an output terminal Q1 of the signal generating module 22 is connected to an input terminal of the third in-phase buffer 220, and an output terminal of the third in-phase buffer 220 outputs a status signal PD _ STAT.
In a specific embodiment of the present application, as shown in fig. 2 and fig. 3, the counter module 21 is formed by cascading a plurality of first D flip-flops 210, each of the first D flip-flops 210 has a clock signal input terminal CLK, a data terminal D, a first output terminal Q, a second output terminal QN, and a reset terminal RN, the second output terminal QN of each of the first D flip-flops 210 is connected to the data terminal D thereof, a signal input terminal CLK inputs a signal LE _ BUF, the signal input terminal CLK is a second input terminal of the counter module 21 in fig. 2, in two adjacent first D flip-flops 210, the second output terminal QN of the first D flip-flop 210 is connected to the clock signal input terminal CLK of the second first D flip-flop 210; the signal generating module 22 includes a second D flip-flop 221, the second D flip-flop 221 has a clock signal input terminal CLK1, a data terminal D1, a first output terminal Q1, a second output terminal QN1 and a reset terminal RN1, the clock signal input terminal CLK1 of the second D flip-flop 221 is connected to the first output terminal Q of the first D flip-flop 210; an output signal of the output end of the detection module 20 is PD _ RSLT, and the output end of the detection module 20 is connected to the reset end RN of the first D flip-flop, the reset end RN1 of the second D flip-flop 221 and the data end D1 of the signal generation module 22 respectively; when the Data in at least one of the 16 Data channels 10 in total from Data0 to Data15 is not 0, the output signal of the output end of the detection module 20 is PD _ RSLT is 0, that is, the input signal of the reset end RN is 0, the output of the first output end Q of the first D flip-flop 210 is 0, and the output of the second output end QN is 1; similarly, the input signal of the reset terminal RN1 is 0, at this time, the output of the first output terminal Q of the second D flip-flop 221 is 0, the output of the second output terminal QN is 1, that is, as long as there is data in the 16 data channels 10 that is not 0, the output of the first output terminal Q of the first D flip-flop 210 is 0, the output of the first output terminal Q of the second D flip-flop 221 is 0, that is, the signal generating module 22 outputs the status signal PD _ STAT to be zero, at this time, the status signal PD _ STAT does not function, that is, the reference current generating module 11 and the current output module 12 are in a normal operating state; under the condition that all Data in 16 Data channels 10 from Data0 to Data15 are 0, the output signal of the output end of the detection module 20 is PD _ RSLT is 1, that is, the input signal of the reset end RN is 1, at this time, the counter module 21 starts timing, and under the condition that all Data in the Data channels 10 are still 0 within the predetermined time period timed by the counter module 21, under the combined action of the counter module 21 and the detection module 20, the status signal PD _ STAT is not 0, at this time, the status signal PD _ STAT controls the reference current generation module 11 and the current output module 12 to be in an off state, that is, the current output module 12 is controlled not to generate constant current output, so as to achieve dynamic energy saving.
In a more specific implementation, as shown in fig. 3, when the detection module 20 detects that all the Data in 16 Data channels 10, i.e., Data 0-Data 15, are 0, the detection module 20 is triggered to start timing, LE _ BUF is a clock input signal of the detection module 20, i.e., an input signal of the second input terminal of the counter module 21, the output terminal Q of the counter module 21 is connected to the second input terminal CLK1 of the signal generation module 22, and the output terminal of the detection module 20 is connected to the first input terminal RN of the counter module 21.
In another embodiment of the present application, as shown in fig. 2, the current output module 12 has a first input end, a second input end, and an output end, the first input end of the current output module 12 is electrically connected to the output end of the data latch 16, the second input end of the current output module 12 is electrically connected to the output end of the second inverter 15, the output end of the current output module 12 outputs multiple paths of constant current signals, the multiple paths of constant current signals output by the current output module 12 are used for driving an external LED, and the external LED is not driven when the current output module 12 is in an off state, so that energy saving is achieved.
In an alternative embodiment, as shown in fig. 2, the driving unit 01 further includes a first in-phase buffer 18 and a second in-phase buffer 19, an input end of the first in-phase buffer 18 is used for inputting the serial data SIN, an output end of the first in-phase buffer 18 is electrically connected to a first input end of the shift register 13, an input end of the second in-phase buffer 19 is used for inputting the external clock signal CLK2, an output end of the second in-phase buffer 19 is electrically connected to a second input end of the shift register 13, the first in-phase buffer 18 buffers the input serial data SIN, and the second in-phase buffer 19 buffers the input external clock signal CLK 2.
In a preferred embodiment, as shown in fig. 2, the channel enable signal OE, the latch enable signal LE, the serial data SIN, and the external clock signal CLK2 are all externally input signals, and do not occupy the resources of the driving unit 01 itself.
In a typical embodiment of the present application, a display device is provided, including an LED driving circuit and an LED display screen, where the LED driving circuit is any one of the above LED driving circuits, and a control unit is disposed in the LED driving circuit, where the control unit detects that data in all data channels is 0 within a predetermined time period, that is, a driven LED is in a black screen state, and controls all data channels to be in an off state, so as to control part of LEDs in the LED display screen not to display (that is, in the black screen state), so as to achieve dynamic energy saving of the LED display screen, where the above driving unit is equivalent to an LED constant current driving chip without an SRAM inside, that is, the LED driving circuit in this scheme achieves dynamic energy saving in the LED constant current driving chip without an SRAM inside.
In another exemplary embodiment of the present application, a display system is provided, including an LED driving circuit, where the LED driving circuit is any one of the LED driving circuits, and a control unit is disposed in the LED driving circuit, where the control unit detects that data in all data channels is 0 within a predetermined time period, that is, a driven LED is in a black screen state, and controls all data channels to be in a closed state, so as to reduce power consumption of the driving unit, so as to implement dynamic energy saving.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) the LED drive circuit comprises a control unit, wherein the control unit is arranged in the LED drive circuit, the control unit detects that data in all data channels are 0 within a preset time period, namely, driven LEDs are in a black screen state, all data channels are controlled to be in a closed state, so that the power consumption of the drive unit is reduced, dynamic energy conservation is realized, the drive unit is equal to an LED constant current drive chip without an SRAM inside, namely, the LED drive circuit of the scheme realizes dynamic energy conservation in the LED constant current drive chip without the SRAM inside, and external input signals are signals outside the LED drive circuit, so that the LED drive circuit does not occupy resources of the LED drive circuit and does not occupy resources of the drive unit.
2) The display device comprises a control unit arranged in an LED drive circuit, wherein the control unit detects that data in all data channels are 0 within a preset time period, namely, driven LEDs are in a black screen state, all data channels are controlled to be in a closed state, partial LEDs in the LED display screen are controlled not to display (namely, the black screen state) so as to realize dynamic energy conservation of the LED display screen, the drive unit is equal to an LED constant current drive chip without an SRAM inside, namely, the LED drive circuit of the scheme realizes dynamic energy conservation in the LED constant current drive chip without the SRAM inside, and external input signals are signals outside the LED drive circuit, so that the resources of the LED drive circuit are not occupied, and the resources of the drive unit are not occupied.
3) The display system comprises a control unit arranged in an LED drive circuit, wherein the control unit detects that data in all data channels are 0 within a preset time period, namely, driven LEDs are in a black screen state, all data channels are controlled to be in a closed state, so that the power consumption of the drive unit is reduced, dynamic energy conservation is realized, the drive unit is equal to an LED constant current drive chip without an SRAM inside, namely, the LED drive circuit of the scheme realizes dynamic energy conservation in the LED constant current drive chip without the SRAM inside, and external input signals are signals outside the LED drive circuit, so that the resources of the LED drive circuit are not occupied, and the resources of the drive unit are not occupied.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (11)
1. An LED driving circuit, comprising:
a driving unit including a plurality of data channels;
and the control unit is electrically connected with the driving unit and controls all the data channels to be in a closed state under the condition that the control unit detects that the data in all the data channels are 0 within a preset time period, wherein the preset time period is determined according to the duration of an external input signal input into the LED driving circuit.
2. The LED driving circuit according to claim 1, wherein the control unit comprises:
the detection module is electrically connected with the driving unit and used for detecting whether the data in all the data channels is 0 or not;
the counter module is electrically connected with the detection module;
and the signal generation module is respectively electrically connected with the detection module and the counter module and is provided with an output end, the output end outputs a state signal, and the state signal is used for controlling all the data channels to be in a closed state under the condition that the data in all the data channels is 0.
3. The LED driving circuit of claim 2, wherein the signal generating module has a first input terminal and a second input terminal, the counter module has a first input terminal and an output terminal, the output terminal of the detection module is electrically connected to the first input terminal of the signal generating module and the first input terminal of the counter module, respectively, and the output terminal of the counter module is electrically connected to the second input terminal of the signal generating module.
4. The LED driving circuit according to claim 2, wherein the driving unit further comprises a reference current generating module and a current output module, the reference current generating module is electrically connected to the signal generating module and the current output module, respectively, and the status signal controls the reference current generating module to be in an off state in a case where data in all the data channels is 0.
5. The LED driving circuit according to claim 4, wherein the driving unit further comprises:
the shift register is provided with a first input end, a second input end and an output end, wherein the first input end is used for inputting serial data, and the second input end is used for inputting an external clock signal;
the input end of the first inverter is used for inputting a latch enabling signal;
the input end of the second inverter is used for inputting a channel enabling signal;
the data latch is provided with a first input end, a second input end, a third input end and an output end, the data output by the output end of the data latch is a plurality of data in the data channel, the output end of the data latch is respectively electrically connected with the input end of the detection module and the input end of the current output module, the first input end of the data latch is electrically connected with the output end of the first phase inverter, the second input end of the data latch is electrically connected with the output end of the shift register, and the third input end of the data latch is electrically connected with the output end of the second phase inverter.
6. The LED driving circuit according to claim 5, wherein the driving unit further comprises a third inverter, the counter module further having a second input, an input of the third inverter being electrically connected to the output of the first inverter, an output of the third inverter being electrically connected to the second input of the counter module.
7. The LED driving circuit according to claim 5, wherein the current output module has a first input terminal, a second input terminal and an output terminal, the first input terminal of the current output module is electrically connected to the output terminal of the data latch, the second input terminal of the current output module is electrically connected to the output terminal of the second inverter, and the output terminal of the current output module outputs a plurality of constant current signals.
8. The LED driving circuit according to claim 5, wherein the driving unit further comprises a first in-phase buffer and a second in-phase buffer, an input terminal of the first in-phase buffer is used for inputting the serial data, an output terminal of the first in-phase buffer is electrically connected to the first input terminal of the shift register, an input terminal of the second in-phase buffer is used for inputting the external clock signal, and an output terminal of the second in-phase buffer is electrically connected to the second input terminal of the shift register.
9. The LED driving circuit according to any of claims 2 to 8, wherein the detection module comprises a NOR gate.
10. A display device comprising an LED driving circuit according to any one of claims 1 to 9.
11. A display system comprising an LED driving circuit and a display screen, wherein the LED driving circuit is the LED driving circuit according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021713660.1U CN212342250U (en) | 2020-08-17 | 2020-08-17 | LED drive circuit, display device and display system |
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| CN202021713660.1U CN212342250U (en) | 2020-08-17 | 2020-08-17 | LED drive circuit, display device and display system |
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| CN212342250U true CN212342250U (en) | 2021-01-12 |
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| CN202021713660.1U Active CN212342250U (en) | 2020-08-17 | 2020-08-17 | LED drive circuit, display device and display system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111836427A (en) * | 2020-08-17 | 2020-10-27 | 北京集创北方科技股份有限公司 | LED drive circuit, display device and display system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111836427A (en) * | 2020-08-17 | 2020-10-27 | 北京集创北方科技股份有限公司 | LED drive circuit, display device and display system |
| WO2022037708A1 (en) * | 2020-08-17 | 2022-02-24 | 北京集创北方科技股份有限公司 | Led driving circuit, display device, and display system |
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