KR20110131709A - Level shifter - Google Patents

Level shifter Download PDF

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Publication number
KR20110131709A
KR20110131709A KR1020100051285A KR20100051285A KR20110131709A KR 20110131709 A KR20110131709 A KR 20110131709A KR 1020100051285 A KR1020100051285 A KR 1020100051285A KR 20100051285 A KR20100051285 A KR 20100051285A KR 20110131709 A KR20110131709 A KR 20110131709A
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KR
South Korea
Prior art keywords
buffer
node
voltage
level
driven
Prior art date
Application number
KR1020100051285A
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Korean (ko)
Inventor
김관언
최원준
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주식회사 하이닉스반도체
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Priority to KR1020100051285A priority Critical patent/KR20110131709A/en
Publication of KR20110131709A publication Critical patent/KR20110131709A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

The level shifter may include a first buffer driven by an internal voltage to buffer an input signal; A second buffer driven by the internal voltage to buffer an output signal to generate a control signal; A switch unit connected between an external voltage and a supply node and turned on in response to the control signal to drive the supply node to a level lower than the internal voltage; And a third buffer receiving the voltage of the supply node and buffering an output signal of the first buffer.

Figure P1020100051285

Description

Level shifter {LEVEL SHIFTER}

The present invention relates to a level shifter.

In general, the level shifter serves as an interface between circuits using different power supply voltages. For example, a word line driver of a semiconductor memory device uses a high voltage VPP at a level higher than an externally supplied external voltage VDD. The signal for driving the word line driver is an external voltage. The word line driver needs to swing between high voltage (VPP) and ground voltage (VSS) while swinging between (VDD) and ground voltage (VSS). Therefore, if the circuit is directly connected without level shifting between the two circuits, the leakage current may flow in the circuit using the high voltage (VPP) as the power supply voltage, so the level shifter is used to connect the two circuits.

Most level shifters have a fighting phenomenon in which NMOS transistors and PMOS transistors are turned on together and driven together when the level of the input signal is transitioned. Referring to the level shifter of the prior art illustrated in FIG. 1, when the input signal IN transitions from a low level to a high level, the NMOS transistor N11 is turned on while the PMOS transistor P11 is turned on. At this time, the NMOS transistor N11 is driven with a driving force larger than that of the PMOS transistor P11, so that the node nd11 is pulled down to a low level, and the output signal OUT is output to the external voltage VEXT.

However, when the NMOS transistor N11 and the PMOS transistor P11 are turned on at the same time, a current path is formed between the external voltage VEXT and the ground voltage VSS to generate a leakage current. Such leakage current increases as the level of the input signal IN increases, which acts as a factor that inhibits the operation speed of the level shifter.

The present invention discloses a level shifter which improves the operation speed by reducing the leakage current generated during the level transition.

To this end, the present invention is a first buffer driven by an internal voltage to buffer the input signal; A second buffer driven by the internal voltage to buffer an output signal to generate a control signal; A switch unit connected between an external voltage and a supply node and turned on in response to the control signal to drive the supply node to a level lower than the internal voltage; And a third buffer receiving the voltage of the supply node and buffering an output signal of the first buffer.

In addition, the present invention includes a first buffer driven by an internal voltage to buffer the input signal; A second buffer driven by an external voltage to buffer the output signal to generate a control signal; A switch unit connected between an external voltage and a supply node and turned on in response to the control signal to drive the supply node to a level lower than the internal voltage and a voltage of the supply node to receive an output signal of the first buffer. A level shifter is provided that includes a third buffer to buffer.

1 is a circuit diagram showing the configuration of a level shifter according to the prior art.
2 is a circuit diagram illustrating a configuration of a level shifter according to an embodiment of the present invention.
3 is a timing diagram for describing an operation of the level shifter illustrated in FIG. 1.
4 is a circuit diagram illustrating a configuration of a level shifter according to another embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

2 is a circuit diagram illustrating a configuration of a level shifter according to an embodiment of the present invention.

As shown in FIG. 2, the level shifter of the present embodiment includes a first buffer 20, a second buffer 21, a switch unit 22, a third buffer 23, a latch unit 24, and a fourth buffer. It consists of 25.

The first buffer 20 is connected between the internal voltage VPERI and the node nd20 to pull up and drive the node nd20 in response to the input signal IN and the node nd20. The NMOS transistor N20 is connected between the ground voltage VSS and pulls down the node nd20 in response to the input signal IN. The first buffer 20 having the above-described configuration has an internal voltage VPERI. And the buffered input signal IN is output to the node nd20, where the signal of the node nd20 swings between the internal voltage VPERI and the ground voltage VSS. VPERI) is lower than the external voltage VEXT.

The second buffer 21 receives the output signal OUT swinging between the external voltage VEXT and the ground voltage VSS and buffers the control signal swinging between the internal voltage VPERI and the ground voltage VSS. CON) is printed. Here, the control signal CON is generated as the internal voltage VPERI when the output signal OUT is the ground voltage VSS.

The switch unit 22 includes an NMOS transistor N21 connected between the external voltage VEXT and the supply node nd21. When the control signal CON is input to the internal voltage VPERI, the NMOS transistor N21 is turned on to drive the supply node nd21 to the level of the maximum internal voltage VPERI-Vth. Here, Vth is the threshold voltage of the NMOS transistor N21.

The third buffer 23 is connected between the supply node nd21 and the node nd22 to pull up and drive the node nd22 in response to the signal of the node nd20 (P22) and the node nd22. And an NMOS transistor (N22) connected between the ground voltage VSS and the pull-down drive of the node nd22 in response to the signal of the node nd20. The third buffer 23 having the above-described configuration includes the node ( The signal of node nd22 is buffered and output to node nd22, where the signal of node nd22 is driven to ground voltage VSS when the signal of node nd20 is driven by internal voltage VPERI, When the signal of nd20 is driven by the ground voltage VSS, it is driven by the voltage of the supply node nd21.

The latch unit 24 is composed of a fifth buffer 230 and a sixth buffer 231. The fifth buffer 230 includes a PMOS transistor P23 and an NMOS transistor N23, and buffers a signal of the node nd22 and outputs the buffered signal to the node nd23. The sixth buffer 231 includes a PMOS transistor P24 and an NMOS transistor N24, and buffers a signal of the node nd23 and outputs the buffered signal to the node nd22. The latch unit 24 having such a configuration latches the signals of the node nd22 and the node nd23.

The fourth buffer 25 buffers the signal of the node nd23 and outputs an output signal OUT swinging between the external voltage VEXT and the ground voltage VSS.

The operation of the level shifter configured as described above will be described with reference to FIG. 3.

First, when the input signal IN transitions from the low level to the high level, the node nd20 is driven with the ground voltage VSS, the node nd22 is driven with the level of the node nd21, and the node nd23 Since the voltage is driven by the ground voltage VSS, the output signal OUT is driven by the external voltage VEXT. At this time, since the control signal CON is driven by the ground voltage VSS, the NMOS transistor N21 of the switch unit 22 is turned off and the node nd21 is in a floating state.

The reason why the node nd21 is floating after the input signal IN transitions from the low level to the high level is that the PMOS transistor P22 is turned on by the node nd20 driven by the ground voltage VSS. Since the NMOS transistor N23 is turned on by the node nd22 driven at the level of the node nd21, the charge of the node nd21 is released through the turned-on PMOS transistor P22 and the NMOS transistor N23. To prevent this.

Next, when the input signal IN transitions from the high level to the low level, the node nd20 is driven by the internal voltage VPERI, the node nd22 is driven by the ground voltage VSS, and the node nd23 Since is driven by the external voltage VEXT, the output signal OUT is driven to the ground voltage (VSS). At this time, since the control signal CON is driven by the internal voltage VPERI, the NMOS transistor N21 of the switch unit 22 is turned on so that the node nd21 is driven to the maximum VPERI-Vth.

 Since the node nd21 is driven to the maximum VPERI-Vth, the PMOS transistor P22 and the PMOS transistor P22 and the node before the node nd21 becomes a floating state after the input signal IN transitions from the low level to the high level again. Even though all of the NMOS transistors N23 are turned on to form a current path, the current consumption is small. That is, since the level shifter of the present embodiment is formed between the node nd21 and the ground voltage VSS, the leakage current is reduced and the operating speed is faster than that of the conventional level shifter formed between the external voltage VEXT and the ground voltage VSS. It works.

Referring to FIG. 4, a configuration of a level shifter according to another embodiment of the present invention can be confirmed. In the case of the level shifter illustrated in FIG. 4, unlike the second buffer 21 included in the level shifter illustrated in FIG. 2, the buffer 31 that buffers the output signal OUT to generate the control signal CON has an external voltage. It operates by supplying (VEXT). Therefore, in the case of the level shifter shown in FIG. 4, when the input signal IN transitions from the low level to the high level, the node nd32 is driven to the voltage of the node nd31, that is, VEXT-Vth.

Claims (8)

A first buffer driven by an internal voltage to buffer an input signal;
A second buffer driven by the internal voltage to buffer an output signal to generate a control signal;
A switch unit connected between an external voltage and a supply node and turned on in response to the control signal to drive the supply node to a level lower than the internal voltage; And
And a third buffer configured to receive the voltage of the supply node and buffer the output signal of the first buffer.
The level shifter of claim 1, wherein the internal voltage is at a level lower than the external voltage.
The method of claim 1, wherein the switch unit is implemented as an NMOS transistor, and when the control signal is driven by the internal voltage to input the driving node to a level obtained by subtracting the level of the NMOS transistor from the level of the internal voltage. Level shifter.
The method of claim 1,
A latch unit for latching and outputting an output signal of the third buffer; And
And a fourth buffer driven by the external voltage to buffer and output the output signal of the latch unit.
A first buffer driven by an internal voltage to buffer an input signal;
A second buffer driven by an external voltage to buffer the output signal to generate a control signal;
A switch unit connected between an external voltage and a supply node and turned on in response to the control signal to drive the supply node to a level lower than the external voltage; And
And a third buffer configured to receive the voltage of the supply node and buffer the output signal of the first buffer.
6. The level shifter of claim 5, wherein the internal voltage is at a level lower than the external voltage.
The method of claim 5, wherein the switch unit is implemented as an NMOS transistor, and when the control signal is driven by the external voltage and is input, driving the supply node to a level obtained by subtracting the level of the NMOS transistor from the level of the external voltage. Level shifter.
The method of claim 5, wherein
A latch unit for latching and outputting an output signal of the third buffer; And
And a fourth buffer driven by the external voltage to buffer and output the output signal of the latch unit.
KR1020100051285A 2010-05-31 2010-05-31 Level shifter KR20110131709A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110297599A (en) * 2018-03-21 2019-10-01 爱思开海力士有限公司 Buffer circuits and memory device with the buffer circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110297599A (en) * 2018-03-21 2019-10-01 爱思开海力士有限公司 Buffer circuits and memory device with the buffer circuits
CN110297599B (en) * 2018-03-21 2023-11-07 爱思开海力士有限公司 Buffer circuit and memory device having the same

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