KR20110128663A - Printed circuit board and the method of manufacturing thereof - Google Patents

Printed circuit board and the method of manufacturing thereof Download PDF

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Publication number
KR20110128663A
KR20110128663A KR1020100048232A KR20100048232A KR20110128663A KR 20110128663 A KR20110128663 A KR 20110128663A KR 1020100048232 A KR1020100048232 A KR 1020100048232A KR 20100048232 A KR20100048232 A KR 20100048232A KR 20110128663 A KR20110128663 A KR 20110128663A
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South Korea
Prior art keywords
layer
metal substrate
photocatalyst
circuit
anodization
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KR1020100048232A
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Korean (ko)
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KR101148226B1 (en
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박성근
신상현
김광수
최석문
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삼성전기주식회사
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Priority to KR1020100048232A priority Critical patent/KR101148226B1/en
Priority to JP2010175295A priority patent/JP2011249744A/en
Priority to US12/868,071 priority patent/US20110284382A1/en
Publication of KR20110128663A publication Critical patent/KR20110128663A/en
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Publication of KR101148226B1 publication Critical patent/KR101148226B1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0256—Electrical insulation details, e.g. around high voltage areas
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C26/00—Coating not provided for in groups C23C2/00 - C23C24/00
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • C25D11/20—Electrolytic after-treatment
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • C25D11/24—Chemical after-treatment
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Ceramic Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE: A printed circuit board and a manufacturing method thereof are provided to form a sol-gel layer between circuit wires of a circuit layer, thereby preventing electrical disconnection. CONSTITUTION: A metal substrate(10) is prepared. An anode oxidizing layer(20) is formed by anodizing the frontal surface of the metal substrate. The anode oxidizing layer is formed on circuit layers(30,31). A photo catalyst is coated between circuit wires of the circuit layers which expose the anode oxidizing layer and the photo catalyst is hardened to form a first sol-gel layer(50).

Description

인쇄회로기판 및 그 제조방법{Printed circuit board and the method of manufacturing thereof}Printed circuit board and the method of manufacturing thereof

본 발명은 인쇄회로기판 및 그 제조방법에 관한 것이다.The present invention relates to a printed circuit board and a method of manufacturing the same.

최근 신호 처리에 필요한 반도체 기술의 급속한 발전으로 인하여 반도체 소자가 괄목할만한 성장을 이루고 있다. 이와 함께 반도체 소자 등의 전자소자를 인쇄회로기판에 미리 실장하여 패키지로 구성하는 SIP(System in package), CSP(Chip sized package), FCP(Flip chip package) 등의 반도체 패키지에 대한 개발이 활발히 이루어지고 있다. 최근에는, 반도체 기술의 발전으로 인해 다이(die)의 크기가 축소되고 있으며, 이로 인해 반도체 소자 등을 실장하기 위한 패키지용 기판의 크기 또한 축소되어, 전자소자와의 전기적 연결을 위해 기판에 형성되는 본드패드(Bond pad)를 구현할 수 있는 면적도 줄어 들고 있는 실정이다.Recently, due to the rapid development of semiconductor technology required for signal processing, semiconductor devices have made remarkable growth. In addition, active development of semiconductor packages such as SIP (System in package), CSP (Chip sized package), FCP (Flip chip package), etc., is performed by pre-mounting electronic devices such as semiconductor devices on printed circuit boards. ought. Recently, due to the development of semiconductor technology, the size of a die is reduced, and as a result, the size of a package substrate for mounting a semiconductor device is also reduced, which is formed on a substrate for electrical connection with an electronic device. Bond pads are also being reduced in area.

전력소자, 예를 들면, 실리콘 제어 정류기, 전력 트랜지스터, 절연된 게이트 바이폴라 트랜지스터, 모스 트랜지스터, 전력정류기, 전력 레귤레이터, 인버터, 컨버터, 또는 이들이 조합된 고전력 반도체 칩은 30V 내지 1000V 또는 그 이상의 전압에서 동작되도록 설계된다. 고전력 반도체 칩은 논리 소자 또는 메모리 소자와 같은 저전력 반도체 칩과 달리 고전압에서 동작하므로, 고전력 반도체 칩으로부터 발생하는 열의 우수한 방출능력과 고압에서의 절연능력이 요구된다.Power devices such as silicon controlled rectifiers, power transistors, insulated gate bipolar transistors, MOS transistors, power rectifiers, power regulators, inverters, converters, or combinations of high power semiconductor chips operate at voltages between 30V and 1000V or higher. It is designed to be. Unlike high-power semiconductor chips such as logic devices or memory devices, high-power semiconductor chips operate at high voltages, and thus require excellent heat dissipation and insulation at high voltages.

도 1은 종래의 고전력 반도체 패키지(100)의 구조를 도식적으로 나타낸 도면이다. 종래 고전력 반도체 패키지(100)의 구조는 기판(140)상에 고전력 반도체칩(150a) 또는 저전력 반도체칩(150b)이 탑재되고, 고전력 반도체칩(150a) 및 저전력 반도체칩(150b) 일면에 대응되는 회로층(130)에 전기적으로 연결되는 본딩패드(151)들이 형성된다. 고전력 반도체칩(150a) 또는 저전력 반도체칩(150b)의 본딩패드(151)는 일반적으로 와이어(170)에 의해 회로층(130)에 전기적으로 연결된다. 와이어 본딩 공정 후에 회로층(130)은 반도체 패키지의 외부 단자 역할을 하는 리드에 연결되고, EMC(epoxy molding process)와 같은 몰딩 부재의 주입공정에 의해 고전력 반도체 패키지(100)가 완성된다. 일반적으로, 고전력 반도체 패키지는 동작시 많은 열을 발생시키므로 기저 금속층(110) 상에 방열판(180)이 부착되어 사용된다. 방열판(180)은 통상적으로 열전도율이 우수한 금속으로 이루어진다. 방열판(180)은 내열 그리즈와 같은 접착부재(185)에 의해 기저 금속층(110)상에 부착될 수 있다. 이러한 방열판(180)을 구비한 종래의 고전력 반도체 패키지의 경우에는, 열방출을 위한 방열판(180)을 구비하기 위해 별도의 기저 금속층(110)이 필요하며, 방열판(180)이 구비됨으로써 구조상의 두께 제어가 쉽지 않고, 사이즈의 소형화를 구현하기 쉽지 않은 문제점이 있다. 또한, 제조공정상에서 리드 프레임을 이용해 칩을 실장하고, 와이어 본딩하는 공정 이외에, 기저 금속층(110)을 접착하고 주입하는 공정 등의 복잡한 공정이 추가되므로, 공정의 신속성 및 신뢰성에 문제가 발생될 수 있었다. 또한, 별도의 기저 금속층(110)의 구비 및 접착부재(185)의 필요성으로 인해 전체적인 제조 비용이 증가 되는 문제점이 있었다. 그리고, 기저 금속층(110)에 의한 방열효과만으로는 한계가 있어, 필요한 방열효과가 충분히 구현되지 못하는 문제점이 있었다. 1 is a diagram schematically illustrating a structure of a conventional high power semiconductor package 100. The structure of the conventional high power semiconductor package 100 includes a high power semiconductor chip 150a or a low power semiconductor chip 150b mounted on a substrate 140 and corresponding to one surface of the high power semiconductor chip 150a and the low power semiconductor chip 150b. Bonding pads 151 are electrically connected to the circuit layer 130. The bonding pad 151 of the high power semiconductor chip 150a or the low power semiconductor chip 150b is generally electrically connected to the circuit layer 130 by a wire 170. After the wire bonding process, the circuit layer 130 is connected to a lead serving as an external terminal of the semiconductor package, and the high power semiconductor package 100 is completed by an injection process of a molding member such as an epoxy molding process (EMC). In general, since the high power semiconductor package generates a lot of heat during operation, the heat sink 180 is attached to the base metal layer 110. The heat sink 180 is typically made of a metal having excellent thermal conductivity. The heat sink 180 may be attached onto the base metal layer 110 by an adhesive member 185 such as a heat resistant grease. In the case of the conventional high power semiconductor package having the heat sink 180, a separate base metal layer 110 is required to provide the heat sink 180 for heat dissipation, and the heat sink 180 is provided to provide a structural thickness. It is not easy to control, and there is a problem that it is not easy to realize the miniaturization of the size. In addition, in addition to the process of mounting the chip using a lead frame and wire bonding in the manufacturing process, a complicated process such as bonding and injecting the base metal layer 110 is added, which may cause problems in the speed and reliability of the process. there was. In addition, there is a problem that the overall manufacturing cost is increased due to the need for a separate base metal layer 110 and the need for the adhesive member 185. In addition, there is a limit only in the heat radiation effect by the base metal layer 110, there was a problem that the necessary heat radiation effect is not sufficiently implemented.

또한, 패키지용 인쇄회로기판의 경우, 종래에는 방열효과를 위해 알루미늄기판에 양극산화층을 절연층으로 형성하여 사용하였는데, 이 경우 회로층의 회로배선 간의 전기적 단락이 발생 되는 문제점이 있었다. 게다가, 회로층 형성을 위한 금속층의 잔류물 또는 양극 산화 공정에서 알루미늄기판의 첨가물(Mg, Si, Cu 등)이 석출되는 과정에서 발생하는 절연층의 불안정 상태로 인한 전기적 단락 등이 발생되는 문제점도 있었다.In addition, in the case of a printed circuit board for a package, conventionally, an anodizing layer was formed as an insulating layer on an aluminum substrate for a heat dissipation effect. In addition, there is a problem that an electrical short occurs due to an instability of the insulating layer that occurs during the deposition of an aluminum substrate additive (Mg, Si, Cu, etc.) in the residue of the metal layer for forming the circuit layer or in the anodization process. there was.

따라서, 본 발명은 상기와 같은 종래기술의 문제점을 해결하고자 안출된 것으로서, 본 발명의 목적은 인쇄회로기판에 형성되는 회로층의 회로배선 사이에 졸겔층을 형성하여 방열특성의 향상 및 회로층의 회로배선 사이에 발생 되는 전기적 단락을 방지할 수 있으며, 또한, 회로층이 형성되지 않는 금속기판 타면의 양극산화층을 제거함으로써 방열효과를 증가시킬 수 있는 인쇄회로기판 및 그 제조방법을 제공하기 위한 것이다.Accordingly, the present invention has been made to solve the problems of the prior art as described above, an object of the present invention is to form a sol-gel layer between the circuit wiring of the circuit layer formed on the printed circuit board to improve the heat dissipation characteristics and the The present invention provides a printed circuit board and a method of manufacturing the same, which can prevent electrical short circuits generated between circuit wiring lines, and increase the heat dissipation effect by removing the anodization layer on the other surface of the metal substrate on which the circuit layer is not formed. .

본 발명의 바람직한 실시예에 따른 인쇄회로기판은 금속기판, 상기 금속기판을 아노다이징하여 형성되는 양극산화층, 상기 양극산화층에 형성되는 회로층 및 상기 양극산화층을 노출시키는 상기 회로층의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 형성된 제1 졸겔층;을 포함한다.A printed circuit board according to a preferred embodiment of the present invention is a photocatalyst between a metal substrate, an anodization layer formed by anodizing the metal substrate, a circuit layer formed on the anodization layer, and a circuit wiring of the circuit layer exposing the anodization layer. And a first sol-gel layer formed by curing the coated photocatalyst after zero coating.

여기서, 상기 광촉매제는 알루미나 또는 이산화티타늄인 것을 특징으로 한다.Here, the photocatalyst is characterized in that the alumina or titanium dioxide.

또한, 상기 양극산화층은 상기 금속기판의 일면 및 양 측면에만 형성된 것을 특징으로 한다.
In addition, the anodization layer is formed on only one side and both side surfaces of the metal substrate.

본 발명의 바람직한 실시예에 따른 인쇄회로기판의 제조방법은 (A) 금속기판을 준비하는 단계, (B) 상기 금속기판 전면에 아노다이징 처리를 하여 양극산화층을 형성하는 단계, (C) 상기 금속기판 일면에 형성된 상기 양극산화층에 회로층을 형성하는 단계 및 (D) 상기 양극산화층을 노출시키는 상기 회로층의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제1 졸겔층을 형성하는 단계; 를 포함한다.A method of manufacturing a printed circuit board according to a preferred embodiment of the present invention includes the steps of (A) preparing a metal substrate, (B) anodizing the entire surface of the metal substrate to form an anodized layer, and (C) the metal substrate. Forming a circuit layer on the anodization layer formed on one surface, and (D) coating the photocatalyst between circuit wirings of the circuit layer exposing the anodization layer, and curing the coated photocatalyst to form a first sol-gel layer. Forming; It includes.

여기서, 상기 (B) 단계는 상기 금속기판 일면 및 양측면에만 아노다이징 처리하여 양극산화층을 형성하는 것을 특징으로 한다.Here, the step (B) is characterized by forming an anodization layer by anodizing only one surface and both sides of the metal substrate.

또한, 상기 (C) 단계는 (C-1) 상기 양극산화층에 시드층을 형성하는 단계, (C-2) 상기 시드층에 전해도금으로 회로도금층을 형성하는 단계, (C-3) 상기 회로도금층에 회로패턴 형성을 위해 에칭 레지스트를 도포한 후 에칭하는 단계 및 (C-4) 상기 에칭 레지스트를 제거하는 단계;를 포함하는 것을 특징으로 한다.(C) step (C-1) forming a seed layer on the anodization layer, (C-2) forming a circuit plating layer on the seed layer by electroplating, and (C-3) the circuit And coating and etching the etching resist to form a circuit pattern on the plating layer, and (C-4) removing the etching resist.

또한, 상기 (C) 단계는 (C-1) 상기 양극산화층에 시드층을 형성하는 단계, (C-2) 상기 시드층에 회로패턴을 위한 도금 레지스트를 도포하는단계, (C-3) 상기 시드층에 회로도금층을 형성하는 단계 및 (C-4) 상기 도금 레지스트를 제거하고, 노출된 상기 시드층을 에칭하는 단계를 포함하는 것을 특징으로 한다.In addition, (C) step (C-1) forming a seed layer on the anodization layer, (C-2) applying a plating resist for a circuit pattern on the seed layer, (C-3) the Forming a circuit plating layer on the seed layer and (C-4) removing the plating resist and etching the exposed seed layer.

또한, 상기 (D) 단계는 (D-1) 상기 금속기판 타면에 형성된 양극산화층에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제2 졸겔층을 형성하는 단계, (D-2) 상기 제2 졸겔층을 제거하는 단계 및 (D-3) 상기 금속기판 타면에 형성된 상기 양극산화층을 제거하는 단계;를 포함하는 것을 특징으로 한다.In addition, the step (D) (D-1) after the coating treatment with a photocatalyst on the anodization layer formed on the other surface of the metal substrate, curing the coated photocatalyst to form a second sol-gel layer, (D-2) Removing the second sol-gel layer and (D-3) removing the anodization layer formed on the other surface of the metal substrate.

또한, 상기 광촉매제는 알루미나 또는 이산화티타늄으로 형성되는 것을 특징으로 한다.In addition, the photocatalyst is characterized in that it is formed of alumina or titanium dioxide.

또한, 상기 광촉매제의 코팅처리는 스프레이 분사법, 디핑(dipping)법 또는 에어로졸 데포지션법으로 수행되는 것을 특징으로 한다.In addition, the coating treatment of the photocatalyst may be performed by a spray spraying method, a dipping method, or an aerosol deposition method.

또한, 상기 코팅처리된 광촉매제를 경화시키는 단계는 100℃ 내지 200℃의 온도에서 수행되는 것을 특징으로 한다.
In addition, the step of curing the coated photocatalyst is characterized in that it is carried out at a temperature of 100 ℃ to 200 ℃.

본 발명의 특징 및 이점들은 첨부도면에 의거한 다음의 상세한 설명으로부터 더욱 명백해질 것이다.The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

이에 앞서 본 명세서 및 청구범위에 사용된 용어나 단어는 통상적이고 사전적인 의미로 해석되어서는 아니 되며, 발명자가 그 자신의 발명을 가장 최선의 방법 으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여 본 발명의 기술적 사상에 부합되는 의미와 개념으로 해석되어야만 한다.Prior to this, the terms or words used in this specification and claims are not to be interpreted in a conventional and dictionary sense, and the inventors may appropriately define the concept of terms in order to best describe their invention. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that the present invention.

본 발명에 따르면, 금속기판에 아노다이징을 통한 양극산화층을 절연층으로 사용함으로써 방열특성을 향상시키는 효과가 있다.According to the present invention, an anodizing layer through anodizing is used as an insulating layer on a metal substrate, thereby improving heat dissipation characteristics.

또한, 회로층의 회로배선 사이에 졸겔층을 형성함으로써 종래 기판에서 적용이 불가능했던 고전압 패키지 인쇄회로기판의 구현이 가능한 효과가 있다.In addition, by forming a sol-gel layer between the circuit wiring of the circuit layer, there is an effect that can be implemented in a high voltage package printed circuit board that was not applicable to the conventional substrate.

또한, 회로층의 회로배선 사이에 졸겔층을 형성함으로써 회로층 형성을 위한 금속층의 잔류물 또는 양극산화공정에서 알루미늄기판의 첨가물(Mg, Si, Cu 등)이 석출되는 과정에서 발생하는 절연층의 불안정을 방지할 수 있는 효과가 있다.In addition, by forming a sol-gel layer between the circuit wiring of the circuit layer, the residue of the metal layer for forming the circuit layer or the insulating layer generated in the process of depositing the additives of the aluminum substrate (Mg, Si, Cu, etc.) in the anodization process It is effective to prevent instability.

또한, 양극산화층 형성을 위한 아노다이징처리의 공정조건의 변경 없이, 졸 코팅의 재료, 두께에 따라 절연전압을 향상시킬 수 있는 효과가 있다.In addition, there is an effect that can improve the insulation voltage according to the material, thickness of the sol coating, without changing the process conditions of the anodizing treatment for forming the anodization layer.

도 1은 종래의 고전력 반도체 패키지의 구조를 도식적으로 나타낸 도면;
도 2는 본 발명의 제1 실시예에 따른 인쇄회로기판의 단면을 나타내는 도면;
도 3은 본 발명의 제2 실시예에 따른 인쇄회로기판의 단면을 나타내는 도면;
도 4 내지 도 11은 본 발명의 제3 실시예에 따른 인쇄회로기판의 제조방법을 나타내는 도면; 및
도 12 내지 도 19는 본 발명의 제4 실시예에 따른 인쇄회로기판의 제조방법을 나타내는 도면이다.1 is a diagram showing the structure of a conventional high power semiconductor package;
2 is a cross-sectional view of a printed circuit board according to a first embodiment of the present invention;
3 is a cross-sectional view of a printed circuit board according to a second embodiment of the present invention;
4 to 11 illustrate a method of manufacturing a printed circuit board according to the third embodiment of the present invention; And
12 to 19 are views illustrating a method of manufacturing a printed circuit board according to the fourth embodiment of the present invention.

본 발명의 목적, 특정한 장점들 및 신규한 특징들은 첨부된 도면들과 연관되어지는 이하의 상세한 설명과 바람직한 실시예들로부터 더욱 명백해질 것이다. 본 명세서에서 각 도면의 구성요소들에 참조번호를 부가함에 있어서, 동일한 구성 요소들에 한해서는 비록 다른 도면상에 표시되더라도 가능한 한 동일한 번호를 가지도록 하고 있음에 유의하여야 한다. 또한, "제1", "제2" 등의 용어는 하나의 구성요소를 다른 구성요소로부터 구별하기 위해 사용되는 것으로, 구성요소가 상기 용어들에 의해 제한되는 것은 아니다. 그리고, 본 발명을 설명함에 있어서, 본 발명의 요지를 불필요하게 흐릴 수 있는 관련된 공지 기술에 대한 상세한 설명은 생략하도록 한다.
The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and the preferred embodiments associated with the accompanying drawings. It should be noted that, in the present specification, the reference numerals are added to the constituent elements of the drawings, and the same constituent elements are assigned the same number as much as possible even if they are displayed on different drawings. In addition, terms such as “first” and “second” are used to distinguish one component from another component, and the component is not limited by the terms. In the following description of the present invention, a detailed description of related arts which may unnecessarily obscure the gist of the present invention will be omitted.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 제1 실시예에 따른 인쇄회로기판을 나타내는 도면이다. 도 2에 도시된 바와 같이, 본 발명의 제1 실시예에 따른 인쇄회로기판은 금속기판(10), 상기 금속기판(10)을 아노다이징하여 형성되는 양극산화층(20), 상기 양극산화층(20)에 형성되는 회로층(30,31) 및 상기 양극산화층(20)을 노출시키는 상기 회로층(30, 31)의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 형성된 제1 졸겔층(50);을 포함한다.
2 is a view showing a printed circuit board according to a first embodiment of the present invention. As shown in FIG. 2, the printed circuit board according to the first embodiment of the present invention includes a metal substrate 10, an anodizing layer 20 formed by anodizing the metal substrate 10, and the anodizing layer 20. A first process formed by curing the coated photocatalyst after coating with a photocatalyst between the circuit layers 30 and 31 formed in the circuit wiring and the circuit wiring of the circuit layers 30 and 31 exposing the anodization layer 20. It includes a sol-gel layer (50).

금속기판(10)은 아노다이징 처리를 통해 양극산화층(20)을 형성할 수 있는 재질로 형성되며, 방열효과를 동시에 갖는다. 금속기판(10)은 알루미늄, 마그네슘 및 티타늄 등의 금속 재질로 형성될 수 있으며, 아노다이징처리에 의한 양극산화층(20)을 형성할 수 있고, 방열특성이 있는 재질의 것이라면 특별히 한정되지 않는다.
The metal substrate 10 is formed of a material capable of forming the anodization layer 20 through anodizing treatment, and has a heat dissipation effect. The metal substrate 10 may be formed of a metal material such as aluminum, magnesium, and titanium, and may form the anodization layer 20 by anodizing, and is not particularly limited as long as it is a material having heat dissipation characteristics.

양극산화층(20)은 아노다이징 처리에 의해 형성되며, 양극산화층(20)은 금속기판(10)을 황산 등의 특정 용액 내에서 양극으로 작용하게 하여 금속기판(10)의 표면에 산화 작용을 촉진시킴으로써 균일한 두께로 인위적인 산화막이 생성되도록 하여 형성된다. 여기서, 양극산화층(20)의 형성은 아노다이징의 처리시간 및 정도에 따라 양극산화층(20)의 형성 두께가 결정되며, 절연특성을 위한 양극산화층(20)을 형성하기 위해 필요한 범위에서 아노다이징 처리를 수행한다.
The anodization layer 20 is formed by anodizing, and the anodization layer 20 acts as an anode in a specific solution such as sulfuric acid to promote oxidation on the surface of the metal substrate 10. It is formed by causing an artificial oxide film to be produced with a uniform thickness. Here, in the formation of the anodization layer 20, the formation thickness of the anodization layer 20 is determined according to the processing time and degree of anodizing, and anodizing is performed in a range necessary to form the anodization layer 20 for insulating properties. do.

회로층(30, 31)은 양극산화층(20)에 형성된다. 회로층(30, 31)의 형성은 서브트랙티브(subtractive) 또는 에디티브(additive) 방식에 의해 형성될 수 있으며, 이외에도 다양한 방식으로 회로층(30, 31)을 형성할 수 있음은 물론이다.
The circuit layers 30 and 31 are formed on the anodization layer 20. The circuit layers 30 and 31 may be formed by a subtractive or additive method, and the circuit layers 30 and 31 may be formed in various ways.

졸겔층(50, 51)은 양극산화층(20)에 형성되는 회로층(30, 31) 및 양극산화층(20)을 노출시키는 회로층(30, 31)의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 형성된다. 여기서, 졸겔층(50, 51)은 졸겔(sol-gel)법에 의해 적층되는 층으로서, 졸겔법이란 "졸겔 세라믹스(sol-gel derived ceramics)"를 제조하는 방법을 의미한다. 특히, 졸겔법에서는 물과 알콕시드의 비율, 용액의 PH, 용매의 종류 및 양 등 여러가지 요소 등으로 반응속도의 변화 및 최종구조물의 구조변화가 일어나며, 이러한 졸겔법은 실험자에 따라 각각 다른 결과를 얻을 수 있을 만큼 민감한 반응이다. 졸겔층(50, 51)의 형성에서 중요한 것은 적당한 온도와 열처리시 알맞은 승온온도 및 냉각속도의 조절이 필요하다. 여기에서 졸(sol)은 알코올계열의 솔벤트에 나노 세라믹 분말을 분산시켜 코팅 후 열처리하는 공정을 거치게 되는데, 유기성분은 남지 않고 세라믹 분말만을 코팅하게 된다. 열처리 후 코팅 처리된 졸겔층(50, 51)은 일정한 밀착력을 가지게 되고, 최종 동작 진행시 금속기판(10)의 파손문제를 방지할 수 있다. 졸겔층(50, 51)의 코팅방법은 스프레이 분사법, 디핑(dipping)법 또는 에어로졸 데포지션법으로 수행할 수 있다. 졸겔층(50, 51)을 형성하는 경우의 용매로서 광촉매제를 이용하여 형성할 수 있으며, 광촉매제의 코팅 처리 후, 코팅된 광촉매제를 경화시킴으로써 졸겔층(50, 51)을 형성할 수 있다. 광촉매제는 이산화티타늄(TiO2) 또는 알루미나(Al2O3)의 재질로 형성될 수 있다. 졸 경화는 졸의 유기성분 제거를 위한 것으로, 경화는 약 100℃ 내지 200℃ 범위 내에서 진행되는 것이 바람직하다.
The sol-gel layers 50 and 51 are coated with a photocatalyst between the circuit layers 30 and 31 formed on the anodization layer 20 and the circuit wirings of the circuit layers 30 and 31 exposing the anodization layer 20. It is formed by curing the coated photocatalyst. Here, the sol-gel layers 50 and 51 are layers laminated by the sol-gel method, and the sol-gel method means a method of manufacturing "sol-gel derived ceramics". Particularly, in the sol-gel method, various factors such as the ratio of water and alkoxide, pH of the solution, type and amount of solvent, etc., change the reaction rate and change the structure of the final structure. It's sensitive enough to get that. What is important in the formation of the sol-gel layers 50 and 51 is to control the appropriate temperature and cooling rate at the appropriate temperature and heat treatment. Here, the sol is subjected to a process of dispersing the nano-ceramic powder in alcohol-based solvents and coating and heat-treating the organic solvent, thereby coating only the ceramic powder. After the heat treatment, the sol-gel layers 50 and 51 coated may have a constant adhesion, and may prevent a problem of breakage of the metal substrate 10 during the final operation. Coating of the sol gel layers 50 and 51 may be carried out by spray spraying, dipping, or aerosol deposition. It can be formed using a photocatalyst as a solvent in the case of forming the sol-gel layer (50, 51), the sol-gel layer (50, 51) can be formed by curing the coated photocatalyst after the coating treatment of the photocatalyst. . The photocatalyst may be formed of a material of titanium dioxide (TiO 2 ) or alumina (Al 2 O 3 ). Sol curing is for removing the organic component of the sol, the curing is preferably carried out in the range of about 100 ℃ to 200 ℃.

도 3은 본 발명의 제2 실시예에 따른 인쇄회로기판을 나타내는 도면이다. 도 3에 도시된 바와 같이, 본 발명의 제2 실시예에 따른 인쇄회로기판은 금속기판(10), 상기 금속기판(10)을 아노다이징하여 형성되는 양극산화층(20), 상기 양극산화층(20)에 형성되는 회로층(30, 31) 및 상기 양극산화층(20)을 노출시키는 상기 회로층(30, 31)의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 형성된 제1 졸겔층(50)을 포함하고, 상기 양극산화층(20)은 상기 금속기판(10)의 회로층(30,31)이 형성된 일면 및 양 측면에만 형성되는 것을 특징으로 한다. 따라서, 회로층(30,31)이 형성되지 않는 금속기판(10) 타면에 양극산화층(20)을 형성하지 않고 금속기판(10)을 노출시킴으로써 방열효과를 향상시킬 수 있다.
3 is a view showing a printed circuit board according to a second embodiment of the present invention. As shown in FIG. 3, the printed circuit board according to the second embodiment of the present invention includes an anodizing layer 20 formed by anodizing the metal substrate 10, the metal substrate 10, and the anodizing layer 20. A first process formed by curing the coated photocatalyst after coating with a photocatalyst between the circuit layers 30 and 31 formed in the circuit layer and the circuit wirings of the circuit layers 30 and 31 exposing the anodization layer 20. It includes a sol gel layer 50, the anodization layer 20 is characterized in that formed on only one side and both sides of the circuit layer (30, 31) of the metal substrate 10 is formed. Therefore, the heat dissipation effect can be improved by exposing the metal substrate 10 without forming the anodization layer 20 on the other surface of the metal substrate 10 on which the circuit layers 30 and 31 are not formed.

본 발명의 제2 실시예는 인쇄회로기판의 방열특성을 더욱 향상시키기 위해 회로층(30, 31)이 형성되지 않는 금속기판(10) 타면에 양극산화층(20)을 제거할 수 있다. 양극산화층(20)의 경우에도 일반적인 절연층 보다는 방열특성이 있지만, 이를 제거하여, 금속기판(10)의 타면을 그대로 노출시킴으로써, 방열특성을 더욱 향상시킬 수 있기 때문이다. 양극산화층(20) 이외의 구성에 따른 설명은 제1 실시예와 중복되므로 상세한 설명은 생략하기로 한다.
According to the second embodiment of the present invention, in order to further improve heat dissipation characteristics of the printed circuit board, the anodization layer 20 may be removed from the other surface of the metal substrate 10 on which the circuit layers 30 and 31 are not formed. The anodic oxidation layer 20 also has heat dissipation characteristics than a general insulating layer, but by removing the same, exposing the other surface of the metal substrate 10 as it is, the heat dissipation characteristics can be further improved. Since the description according to the configuration other than the anodization layer 20 overlaps with the first embodiment, detailed description thereof will be omitted.

도 4 내지 도 11은 본 발명의 제3 실시예에 따른 인쇄회로기판의 제조방법을 나타내는 도면이다. 특히 인쇄회로기판의 회로층(30, 31)을 서브트랙티브 방식에 의해 형성하여 인쇄회로기판을 제조하는 공정이다. 이하, 도면을 참조하여 본 발명의 제3 실시예에 따른 인쇄회로기판의 제조공정을 설명한다. 또한, 본 발명의 제1 실시예 및 제2 실시예에 따른 인쇄회로기판의 구성 및 작용과 중복되는 내용은 이하에서 생략하기로 한다.
4 to 11 illustrate a method of manufacturing a printed circuit board according to a third exemplary embodiment of the present invention. In particular, the circuit layers 30 and 31 of the printed circuit board are formed by a subtractive method to manufacture the printed circuit board. Hereinafter, a manufacturing process of a printed circuit board according to a third embodiment of the present invention will be described with reference to the drawings. In addition, descriptions overlapping with the configuration and operation of the printed circuit board according to the first and second embodiments of the present invention will be omitted below.

본 발명에 따른 제3 실시예의 인쇄회로기판의 제조공정은 (A) 금속기판(10)을 준비하는 단계, (B) 상기 금속기판(10) 전면에 아노다이징 처리를 하여 양극산화층(20)을 형성하는 단계, (C) 상기 금속기판(10) 일면에 형성된 상기 양극산화층(20)에 회로층(30, 31)을 형성하는 단계 및 (D) 상기 회로층(30,31)이 형성된 상기 양극산화층(20)을 노출시키는 상기 회로층(30, 31)의 회로배선사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제1 졸겔층(50)을 형성하는 단계를 포함한다. In the manufacturing process of the printed circuit board according to the third embodiment of the present invention, (A) preparing a metal substrate 10, (B) anodizing the entire surface of the metal substrate 10 to form an anodization layer 20. (C) forming circuit layers 30 and 31 on the anodization layer 20 formed on one surface of the metal substrate 10 and (D) the anodization layer on which the circuit layers 30 and 31 are formed. And coating the photocatalyst with the photocatalyst between the circuit wirings of the circuit layers 30 and 31 exposing (20), thereby curing the coated photocatalyst to form the first sol gel layer 50.

이하, 도면을 참조하여 인쇄회로기판의 제조공정을 설명한다.
Hereinafter, a manufacturing process of a printed circuit board will be described with reference to the drawings.

도 4는 (A) 금속기판(10)을 준비하는 단계 및 (B) 상기 금속기판(10) 전면에 아노다이징 처리를 하여 양극산화층(20)을 형성하는 단계를 나타낸 도면이다. 본 단계에서의 금속기판(10)은 아노다이징 처리에 의한 양극산화층(20)을 형성하며, 방열특성이 있는 재질로 형성하는 것이 바람직하다. 예를 들면, 금속기판(10)은 알루미늄, 마그네슘 및 티타늄 등의 금속 재질로 구성될 수 있다. (B) 단계는 금속기판(10)을 황산 등의 특정 용액 내에서 양극으로 작용하게 하여 금속기판(10)의 표면에 산화 작용을 촉진시켜 균일한 두께로 인위적인 산화막이 생성되도록 한다. 양극산화층(20)의 형성은 아노다이징의 처리시간 및 정도에 따라 양극산화층(20)의 형성 두께가 결정되며, 절연특성을 위한 양극산화층(20)을 형성하기 위해 필요한 범위에서 아노다이징 처리를 수행한다.
FIG. 4 is a view illustrating a step of preparing the metal substrate 10 and (B) forming an anodization layer 20 by anodizing the entire surface of the metal substrate 10. In this step, the metal substrate 10 forms the anodization layer 20 by anodizing and is preferably formed of a material having heat dissipation characteristics. For example, the metal substrate 10 may be made of a metal material such as aluminum, magnesium, and titanium. Step (B) causes the metal substrate 10 to act as an anode in a specific solution such as sulfuric acid to promote oxidation on the surface of the metal substrate 10 so that an artificial oxide film is formed with a uniform thickness. In the formation of the anodization layer 20, the formation thickness of the anodization layer 20 is determined according to the processing time and degree of anodizing, and anodizing is performed in a range necessary to form the anodization layer 20 for insulating characteristics.

도 5 내지 도 8은 (C) 양극산화층(20)에 회로층(30, 31)을 형성하는 공정을 나타내는 도면이다. 특히 본 실시에에서는 회로층(30, 31)을 서브트랙티브 방식에 의해 형성되므로, 이에 따른 인쇄회로기판의 제조공정을 설명한다. 이러한 회로층(30, 31)의 형성은 (C-1) 상기 양극산화층(20)에 시드층(31)을 형성하는 단계, (C-2) 상기 시드층(31)에 전해도금으로 회로도금층(30)을 형성하는 단계, (C-3) 상기 회로도금층(30)에 회로패턴을 위한 에칭 레지스트(40)를 도포한 후, 에칭을 하는 단계 및 (C-4) 상기 에칭 레지스트(40)를 제거하는 단계를 포함한다.
5 to 8 show the steps of forming the circuit layers 30 and 31 on the (C) anodization layer 20. In particular, in the present embodiment, since the circuit layers 30 and 31 are formed by the subtractive method, the manufacturing process of the printed circuit board will be described. The circuit layers 30 and 31 may be formed by (C-1) forming the seed layer 31 on the anodization layer 20, and (C-2) the circuit plating layer by electroplating on the seed layer 31. (30) forming (C-3) applying the etching resist 40 for the circuit pattern to the circuit plating layer 30, then etching and (C-4) the etching resist 40 Removing the step.

도 5는 (C-1) 상기 양극산화층(20)에 시드층(31)을 형성하는 단계 및 (C-2) 상기 시드층(31)에 전해도금으로 회로도금층(30)을 형성하는 단계를 나타내는 도면이다. 시드층(31)은 전해도금을 위한 인입선의 역할을 하는 것으로, 이후 회로도금층(30)의 적층을 위해 습식도금법(무전해) 또는 건식도금법(스퍼터링)으로 형성될 수 있다. 시드층(31)이 형성된 후에, 시드층(31)에 회로도금층(30)을 전해도금방식으로 형성함으로써 원하는 두께의 회로층(30,31)을 형성할 수 있다.
FIG. 5 illustrates the steps of (C-1) forming a seed layer 31 on the anodization layer 20 and (C-2) forming a circuit plating layer 30 by electroplating on the seed layer 31. It is a figure which shows. The seed layer 31 serves as a lead wire for electroplating, and may be formed by wet plating (electroless) or dry plating (sputtering) for laminating the circuit plating layer 30. After the seed layer 31 is formed, the circuit layer 30, 31 having a desired thickness can be formed by forming the circuit plating layer 30 on the seed layer 31 by electroplating.

도 6 및 도 7은 (C-3) 상기 회로도금층(30)에 회로패턴 형성을 위한 에칭 레지스트(40)를 도포한 후, 에칭하는 단계를 나타내는 도면이다. 도 6은 회로도금층(30)에 회로층(30, 31) 형성하기 위해 회로패턴에 따른 에칭 레지스트(40)를 도포하는 단계이다. 도 7은 에칭을 수행하여 회로패턴을 형성하는 단계이다. 이 경우 에칭은 습식에칭 또는 건식에칭에 의해 수행될 수 있으며, 이러한 에칭방식에 한정되는 것은 아니며, 이외의 방법으로 회로패턴을 형성할 수 있다.
6 and 7 (C-3) show the step of etching after applying the etching resist 40 for forming a circuit pattern on the circuit plating layer 30. FIG. 6 is a step of applying an etching resist 40 according to a circuit pattern to form the circuit layers 30 and 31 on the circuit plating layer 30. 7 is a step of forming a circuit pattern by performing an etching. In this case, the etching may be performed by wet etching or dry etching, and is not limited to such an etching method, and a circuit pattern may be formed by other methods.

도 8에서는 (C-4) 상기 에칭 레지스트(40)를 제거하는 단계이다. 에칭 레지스트(40)를 제거함으로써, 최종적으로 원하는 회로층(30, 31)이 양극산화층(20)에 형성되게 된다.
In FIG. 8, (C-4) is the step of removing the etching resist 40. By removing the etching resist 40, the desired circuit layers 30 and 31 are finally formed in the anodization layer 20.

도 9 내지 도 11은 (D) 상기 양극산화층(20)을 노출시키는 상기 회로층(30, 31)의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제1 졸겔층(50)을 형성하는 단계를 나타낸다. 여기서, (D) 단계는 (D-1) 상기 금속기판(10) 타면에 형성된 양극산화층(20)에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제2 졸겔층(51)을 형성하는 단계, (D-2) 상기 제2 졸겔층(51)을 제거하는 단계 및 (D-3) 상기 금속기판(10) 타면에 형성된 상기 양극산화층(20)을 제거하는 단계를 포함하여 수행될 수 있다.
9 to 11 (D) after the coating treatment with a photocatalyst between the circuit wiring of the circuit layers 30 and 31 exposing the anodization layer 20, the coated photocatalyst is cured to form a first sol-gel layer ( 50). Here, the step (D) (D-1) after the coating treatment with a photocatalyst on the anodization layer 20 formed on the other surface of the metal substrate 10, and curing the coated photocatalyst to form a second sol-gel layer 51 And (D-2) removing the second sol-gel layer 51 and (D-3) removing the anodization layer 20 formed on the other surface of the metal substrate 10. Can be.

도 9는 (D) 양극산화층(20)을 노출시키는 회로층(30, 31)의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제1 졸겔층(50)을 형성하는 단계 및 (D-1) 금속기판(10) 타면에 형성된 양극산화층(20)에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제2 졸겔층(51)을 형성하는 단계를 나타낸다. (D) 단계에서 공정이 마무리되어 인쇄회로기판을 형성할 수 있고, 공정에서 금속기판(10) 양면에 동시 또는 순차적으로 제1 졸겔층(50) 및 제2 졸겔층(51)을 부착하여 형성할 수 있다. 여기에서의 제1 졸겔층(50) 및 제2 졸겔층(51)의 형성 및 광촉매제의 코팅 및 경화에 대한 설명은 본 발명의 제1 실시예 및 제2 실시예에 따른 내용과 동일하므로 생략하기로 한다.
FIG. 9 illustrates that (D) a first photocatalyst is cured by coating a photocatalyst between the circuit wirings of the circuit layers 30 and 31 exposing the anodization layer 20 and then curing the coated photocatalyst to form the first sol gel layer 50. Step and (D-1) after the coating treatment with a photocatalyst on the anodization layer 20 formed on the other surface of the metal substrate 10, and curing the coated photocatalyst to form a second sol-gel layer 51. In step (D), the process may be completed to form a printed circuit board. In the process, the first sol-gel layer 50 and the second sol-gel layer 51 may be attached to both surfaces of the metal substrate 10 simultaneously or sequentially. can do. The description of the formation of the first sol-gel layer 50 and the second sol-gel layer 51 and the coating and curing of the photocatalyst are the same as those according to the first and second embodiments of the present invention and thus are omitted. Let's do it.

도 10에서는 (D-2) 상기 제2 졸겔층(51)을 제거하는 단계를 나타내는 도면이다. 이는 금속기판(10)의 타면에 제2 졸겔층(51)을 제거하여 방열특성을 향상시키기 위함이다. 또한, 도 11과 같이, (D-3) 상기 금속기판(10) 타면에 형성된 상기 양극산화층(20)을 제거하는 단계를 더 포함함으로써, 금속기판(10)이 직접 노출되어 방열특성 효과를 더욱 증진될 수 있다.
10 is a diagram illustrating a step of removing the second sol-gel layer 51 (D-2). This is to improve the heat dissipation characteristics by removing the second sol-gel layer 51 on the other surface of the metal substrate 10. In addition, as shown in Figure 11, (D-3) further comprises the step of removing the anodization layer 20 formed on the other surface of the metal substrate 10, the metal substrate 10 is directly exposed to further improve the heat radiation characteristics effect. Can be promoted.

도 12 내지 도 19는 본 발명의 제4 실시예에 따른 인쇄회로기판의 제조방법을 나타내는 도면이다. 특히 인쇄회로기판의 회로층(30, 31)을 에디티브 방식에 의해 형성하여 인쇄회로기판을 제조하는 공정이다. 이하, 도면을 참조하여 본 발명의 제4 실시예에 따른 인쇄회로기판의 제조공정을 설명한다. 또한, 제3 실시예에 따른 인쇄회로기판의 제조공정과 중복되는 내용은 이하에서 생략하기로 한다.
12 to 19 are views illustrating a method of manufacturing a printed circuit board according to the fourth embodiment of the present invention. In particular, the circuit layers 30 and 31 of the printed circuit board are formed by the additive method to manufacture the printed circuit board. Hereinafter, a manufacturing process of a printed circuit board according to a fourth embodiment of the present invention will be described with reference to the drawings. In addition, the description overlapping with the manufacturing process of the printed circuit board according to the third embodiment will be omitted below.

본 발명의 인쇄회로기판의 제조공정은 (A) 금속기판(10)을 준비하는 단계, (B) 상기 금속기판(10) 전면에 아노다이징 처리를 하여 양극산화층(20)을 형성하는 단계, (C) 상기 금속기판(10) 일면에 형성된 상기 양극산화층(20)에 회로층(30, 31)을 형성하는 단계 및 (D) 상기 회로층(30,31)이 형성된 상기 양극산화층(20)을 노출시키는 상기 회로층(30, 31)의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제1 졸겔층(50)을 형성하는 단계를 포함한다.
In the manufacturing process of the printed circuit board of the present invention, (A) preparing a metal substrate 10, (B) anodizing the entire surface of the metal substrate 10 to form an anodized layer 20, (C ) Forming circuit layers 30 and 31 on the anodization layer 20 formed on one surface of the metal substrate 10 and (D) exposing the anodization layer 20 on which the circuit layers 30 and 31 are formed. And coating the photocatalyst between the circuit wirings of the circuit layers 30 and 31 to cure the coated photocatalyst to form the first sol-gel layer 50.

이하, 도면을 참조하여 인쇄회로기판의 제조공정을 설명한다.Hereinafter, a manufacturing process of a printed circuit board will be described with reference to the drawings.

도 12는 (A) 금속기판(10)을 준비하는 단계 및 (B) 상기 금속기판(10) 전면에 아노다이징 처리를 하여 양극산화층(20)을 형성하는 단계를 나타낸 도면이다. 이에 대한 자세한 설명은 본 발명의 제3 실시예에 따른 인쇄회로기판의 제조공정과 동일하므로 생략한다.
FIG. 12 is a view illustrating a step of preparing the metal substrate 10 and (B) forming an anodization layer 20 by anodizing the entire surface of the metal substrate 10. Detailed description thereof will be omitted as it is the same as the manufacturing process of the printed circuit board according to the third embodiment of the present invention.

도 13 내지 도 16은 (C) 양극산화층(20)에 회로층(30, 31)을 형성하는 공정을 나타내는 도면이다. 특히 본 실시에에서는 회로층(30, 31)을 에디티브 방식에 의해 형성되므로, 이에 따른 인쇄회로기판의 제조공정을 설명한다. 이러한 회로층(30, 31)의 형성은 (C-1) 상기 양극산화층(20)에 시드층(31)을 형성하는 단계, (C-2) 상기 시드층(31)에 회로패턴을 위한 도금 레지스트(41) 도포단계, (C-3) 상기 시드층(31)에 회로도금층(30)을 형성하는 단계, (C-4) 상기 도금 레지스트(41)를 제거하고, 노출된 상기 시드층(31)을 에칭하는 단계를 나타내는 도면이다.
13 to 16 show the steps of forming the circuit layers 30 and 31 on the (C) anodization layer 20. In particular, in the present embodiment, since the circuit layers 30 and 31 are formed by the additive method, the manufacturing process of the printed circuit board will be described. The circuit layers 30 and 31 may be formed by (C-1) forming a seed layer 31 on the anodization layer 20, and (C-2) plating the circuit layer on the seed layer 31. (C-3) forming a circuit plating layer 30 on the seed layer 31, (C-4) removing the plating resist 41 and exposing the exposed seed layer ( 31 shows a step of etching.

도 13은 (C-1) 상기 양극산화층(20)에 시드층(31)을 형성하는 단계 및 (C-2) 상기 시드층(31)에 회로패턴을 위한 도금 레지스트(41) 도포단계를 나타내는 도면이다. 시드층(31)은 전해도금을 위한 인입선의 역할을 하는 것으로, 이후 회로도금층(30)의 형성을 위해 습식도금법(무전해) 또는 건식도금법(스퍼터링)으로 형성될 수 있다. 시드층(31)이 형성된 후에, 시드층(31)에 회로도금층(30)을 전해도금방식으로 형성하게 된다. 그리고 원하는 회로패턴 형성을 위해 도금 레지스트(41)를 도포한다.
FIG. 13 shows (C-1) forming a seed layer 31 on the anodization layer 20 and (C-2) applying a plating resist 41 to a circuit pattern on the seed layer 31. Drawing. The seed layer 31 serves as a lead wire for electroplating, and may be formed by wet plating (electroless) or dry plating (sputtering) to form the circuit plating layer 30. After the seed layer 31 is formed, the circuit plating layer 30 is formed on the seed layer 31 by electroplating. Then, the plating resist 41 is applied to form a desired circuit pattern.

도 14는 (C-3) 상기 시드층(31)에 회로도금층(30)을 형성하는 단계를 나타낸 도면이다. 도금 레지스트가 도포된 부분 이외에 회로도금층(30)이 형성된다.
14 illustrates a step of forming a circuit plating layer 30 on the seed layer 31 (C-3). In addition to the portion where the plating resist is applied, the circuit plating layer 30 is formed.

도 15는 (C-4) 상기 도금레지스트(41)를 제거하는 단계를 나타내며, 도 16은 (C-4) 노출된 상기 시드층(31)을 에칭하는 단계를 나타내는 도면이다. 도금 레지스트(41)를 제거한 후, 회로패턴 사이에 노출된 시드층(31)을 선택적으로 에칭함으로써 최종 회로층(30, 31)을 형성하게 된다.
FIG. 15 illustrates a step of removing the plating resist 41 (C-4), and FIG. 16 illustrates a step of etching the exposed seed layer 31 (C-4). After the plating resist 41 is removed, the final circuit layers 30 and 31 are formed by selectively etching the seed layer 31 exposed between the circuit patterns.

도 17은 (D) 상기 양극산화층(20)을 노출시키는 상기 회로층(30, 31)의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제1 졸겔층(50)을 형성하고, (D-1) 회로층(30,31)이 형성되지 않은 금속기판(10) 타면에 제2 졸겔층(51)을 형성하는 단계를 나타낸다. 이후에, 도 18과 같이 (D-2) 금속기판(10) 타면에 형성된 제2 졸겔층(51)을 제거하는 단계로서 인쇄회로기판이 완성될 수 있다. 또한, 더 나아가 도 19와 같이, (D-3) 상기 금속기판(10) 타면에 형성된 상기 양극산화층(20)을 제거하는 단계를 수행하여 금속기판(10) 타면을 노출시킴으로서 방열특성을 더욱 향상시킬 수 있다. 기타 상세한 설명은 상술한 제3 실시예에 따른 인쇄회로기판 제조공정의 도 9 내지 도 11의 공정과 동일하므로 여기서는 생략하기로 한다.
FIG. 17 illustrates a process of coating the first photocatalyst by curing the coated photocatalyst (D) after the photocatalyst is coated between the circuit wirings of the circuit layers 30 and 31 exposing the anodization layer 20. And the second sol-gel layer 51 is formed on the other surface of the metal substrate 10 on which the (D-1) circuit layers 30 and 31 are not formed. Thereafter, as shown in FIG. 18, the printed circuit board may be completed as a step of removing the second sol-gel layer 51 formed on the other surface of the metal substrate 10 (D-2). Further, as shown in FIG. 19, the heat treatment is further improved by exposing the other surface of the metal substrate 10 by performing the step of removing the anodization layer 20 formed on the other surface of the metal substrate 10 (D-3). You can. Other detailed description is the same as the process of Figures 9 to 11 of the manufacturing process of the printed circuit board according to the third embodiment described above will be omitted here.

이상 본 발명을 구체적인 실시예를 통하여 상세히 설명하였으나, 이는 본 발명을 구체적으로 설명하기 위한 것으로, 본 발명에 따른 인쇄회로기판 및 그 제조방법은 이에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당해 분야의 통상의 지식을 가진 자에 의해 그 변형이나 개량이 가능함은 명백하다고 할 것이다. 본 발명의 단순한 변형 내지 변경은 모두 본 발명의 영역에 속하는 것으로 본 발명의 구체적인 보호 범위는 첨부된 특허청구범위에 의하여 명확해질 것이다.
Although the present invention has been described in detail through specific embodiments, this is for explaining the present invention in detail, and the printed circuit board and the manufacturing method thereof according to the present invention are not limited thereto, and the technical field of the present invention is related to the present invention. It will be apparent that modifications and improvements are possible by those skilled in the art. All simple modifications and variations of the present invention fall within the scope of the present invention, and the specific scope of protection of the present invention will be apparent from the appended claims.

10: 금속기판 20: 양극산화층
30: 회로도금층 31: 시드층
30,31: 회로층 40: 에칭 레지스트
41: 도금 레지스트 50: 제1 졸겔층
51: 제2 졸겔층10: metal substrate 20: anodization layer
30: circuit plating layer 31: seed layer
30,31: circuit layer 40: etching resist
41: plating resist 50: first sol-gel layer
51: second sol-gel layer

Claims (11)

금속기판;
상기 금속기판을 아노다이징하여 형성되는 양극산화층;
상기 양극산화층에 형성되는 회로층; 및
상기 양극산화층을 노출시키는 상기 회로층의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 형성된 제1 졸겔층;을 포함하는 인쇄회로기판.
Metal substrate;
An anodization layer formed by anodizing the metal substrate;
A circuit layer formed on the anodization layer; And
And a first sol-gel layer formed by curing the coated photocatalyst after coating with a photocatalyst between circuit wirings of the circuit layer exposing the anodization layer.
청구항 1에 있어서,
상기 광촉매제는 알루미나 또는 이산화티타늄인 것을 특징으로 하는 인쇄회로기판.
The method according to claim 1,
The photocatalyst is a printed circuit board, characterized in that alumina or titanium dioxide.
청구항 1에 있어서,
상기 양극산화층은 상기 금속기판의 일면 및 양 측면에만 형성된 것을 특징으로 하는 인쇄회로기판.
The method according to claim 1,
The anodization layer is a printed circuit board, characterized in that formed on only one side and both sides of the metal substrate.
(A) 금속기판을 준비하는 단계;
(B) 상기 금속기판 전면에 아노다이징 처리를 하여 양극산화층을 형성하는 단계;
(C) 상기 금속기판 일면에 형성된 상기 양극산화층에 회로층을 형성하는 단계; 및
(D) 상기 양극산화층을 노출시키는 상기 회로층의 회로배선 사이에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제1 졸겔층을 형성하는 단계; 를 포함하는 인쇄회로기판의 제조방법.
(A) preparing a metal substrate;
(B) anodizing the entire surface of the metal substrate to form an anodization layer;
(C) forming a circuit layer on the anodization layer formed on one surface of the metal substrate; And
(D) coating the photocatalyst with the photocatalyst between the circuit wirings of the circuit layer exposing the anodization layer, and curing the coated photocatalyst to form a first sol gel layer; And a step of forming the printed circuit board.
청구항 4에 있어서,
상기 (B) 단계는 상기 금속기판 일면 및 양측면에만 아노다이징 처리하여 양극산화층을 형성하는 것을 특징으로 하는 인쇄회로기판의 제조방법.
The method of claim 4,
The step (B) is a method of manufacturing a printed circuit board, characterized in that to form an anodized layer by anodizing only one side and both sides of the metal substrate.
청구항 4에 있어서,
상기 (C) 단계는
(C-1) 상기 양극산화층에 시드층을 형성하는 단계;
(C-2) 상기 시드층에 전해도금으로 회로도금층을 형성하는 단계;
(C-3) 상기 회로도금층에 회로패턴 형성을 위해 에칭 레지스트를 도포한 후 에칭하는 단계; 및
(C-4) 상기 에칭 레지스트를 제거하는 단계;를 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.
The method of claim 4,
Step (C) is
(C-1) forming a seed layer on the anodization layer;
(C-2) forming a circuit plating layer on the seed layer by electroplating;
(C-3) applying an etching resist to the circuit plating layer to form a circuit pattern and then etching; And
(C-4) removing the etching resist; a printed circuit board manufacturing method comprising a.
청구항 4에 있어서,
상기 (C) 단계는
(C-1) 상기 양극산화층에 시드층을 형성하는 단계;
(C-2) 상기 시드층에 회로패턴을 위한 도금 레지스트를 도포하는단계;
(C-3) 상기 시드층에 회로도금층을 형성하는 단계; 및
(C-4) 상기 도금 레지스트를 제거하고, 노출된 상기 시드층을 에칭하는 단계;를 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.
The method of claim 4,
Step (C) is
(C-1) forming a seed layer on the anodization layer;
(C-2) applying a plating resist for a circuit pattern to the seed layer;
(C-3) forming a circuit plating layer on the seed layer; And
(C-4) removing the plating resist and etching the exposed seed layer.
청구항 4에 있어서,
상기 (D) 단계는
(D-1) 상기 금속기판 타면에 형성된 양극산화층에 광촉매제로 코팅처리 후, 코팅처리된 광촉매제를 경화시켜 제2 졸겔층을 형성하는 단계;
(D-2) 상기 제2 졸겔층을 제거하는 단계; 및
(D-3) 상기 금속기판 타면에 형성된 상기 양극산화층을 제거하는 단계;를 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.
The method of claim 4,
Step (D) is
(D-1) forming a second sol-gel layer by curing the coated photocatalyst after coating the photocatalyst on the anodization layer formed on the other surface of the metal substrate;
(D-2) removing the second sol-gel layer; And
(D-3) removing the anodization layer formed on the other surface of the metal substrate.
청구항 4에 있어서,
상기 광촉매제는 알루미나 또는 이산화티타늄으로 형성되는 것을 특징으로 하는 인쇄회로기판의 제조방법.
The method of claim 4,
The photocatalyst is a manufacturing method of a printed circuit board, characterized in that formed of alumina or titanium dioxide.
청구항 4에 있어서,
상기 광촉매제의 코팅처리는 스프레이 분사법, 디핑(dipping)법 또는 에어로졸 데포지션법으로 수행되는 것을 특징으로 하는 인쇄회로기판의 제조방법.
The method of claim 4,
The coating process of the photocatalyst is a method of manufacturing a printed circuit board, characterized in that performed by spray spraying, dipping (dipping) method or aerosol deposition method.
청구항 4에 있어서,
상기 코팅처리된 광촉매제를 경화시키는 단계는 100℃ 내지 200℃의 온도에서 수행되는 것을 특징으로 하는 인쇄회로기판의 제조방법.


The method of claim 4,
Curing the coated photocatalyst is a method of manufacturing a printed circuit board, characterized in that carried out at a temperature of 100 ℃ to 200 ℃.


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