KR20110128500A

KR20110128500A - Plasma display panel and multi plasma display panel

Info

Publication number: KR20110128500A
Application number: KR1020100047990A
Authority: KR
Inventors: 우승우
Original assignee: 엘지전자 주식회사
Priority date: 2010-05-24
Filing date: 2010-05-24
Publication date: 2011-11-30

Abstract

PURPOSE: A plasma display panel and a lower part address electrode and a multi plasma display panel are provided to reduce the size of a seam area by forming an address electrode, which is formed in the rear substrate, into a plurality of layered structures. CONSTITUTION: A front substrate is formed to arranging a scan electrode and a sustain electrode. A rear substrate is arranged to be face the front substrate. A lower address electrode(410) is arranged in the rear substrate. An upper address electrode(400) is arranged on the top of a first dielectric layer. The electrode(910) of a flexible substrate(900) is electrically connected to the upper address electrode.

Description

Plasma Display Panel and Multi Plasma Display Panel

The present invention relates to a plasma display panel and a multi-plasma display panel.

The plasma display panel includes a phosphor layer formed in a discharge cell divided by a partition wall, and also includes a plurality of electrodes.

When the drive signal is supplied to the electrode of the plasma display panel, the discharge is generated by the drive signal supplied in the discharge cell. Here, when discharged by a drive signal in the discharge cell, the discharge gas filled in the discharge cell generates vacuum ultraviolet rays, and the vacuum ultraviolet light emits the phosphor formed in the discharge cell to emit visible light. Generate. The visible light displays an image on the screen of the plasma display panel.

SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display panel and a multi-plasma display panel in which address electrodes formed on a rear substrate are formed in a multi-layer structure.

According to the present invention, a plasma display panel includes a front substrate on which scan and sustain electrodes are disposed, a rear substrate disposed to face the front substrate, a lower address electrode disposed on the rear substrate, and an upper portion of the lower address electrode. A first dielectric layer, an upper address electrode disposed on the first dielectric layer, and a second dielectric layer disposed on the upper address electrode may be included.

In addition, the upper address electrode and the lower address electrode may be connected.

In addition, a connection electrode may be formed between the upper address electrode and the lower address electrode to electrically connect the upper address electrode and the lower address electrode.

In addition, the connection electrode may penetrate the first dielectric layer.

In addition, the width of the upper address electrode in the connection portion between the upper address electrode and the connection electrode may be larger than the width in other portions.

In addition, the length of the connection electrode may be greater than or equal to the thickness of the first dielectric layer.

The upper address electrode and the lower address electrode may cross each other.

The lower address electrode may include a portion exposed to the outside of the first dielectric layer.

In addition, the length of the lower address electrode may be shorter than the length of the upper address electrode.

In addition, a partition wall may be further disposed between the front substrate and the rear substrate, and the upper address electrode and the lower address electrode may include a portion disposed in an area overlapping the discharge cell.

In addition, a seal portion may be further disposed between the front substrate and the back substrate, and the lower address electrode may include a portion overlapping the seal portion.

In addition, the upper address electrode may be disposed inside the seal portion.

The lower address electrode may extend further in the outward direction of the rear substrate than the upper address electrode.

In addition, the upper address electrode may be formed in a substantially straight line.

In addition, a distance between two adjacent lower address electrodes may include a portion smaller than a distance between two adjacent upper address electrodes.

In addition, another plasma display panel according to the present invention includes a front substrate on which scan electrodes and a sustain electrode are disposed, a rear substrate disposed to face the front substrate, a first dielectric layer disposed on the rear substrate, and an upper portion of the first dielectric layer. A second dielectric layer, wherein an address electrode is disposed between the first dielectric layer and the second dielectric layer in the first region of the rear substrate, and the first dielectric layer and the first dielectric layer in the second region of the rear substrate; An address electrode may be disposed between the two dielectric layers and between the first dielectric layer and the back substrate.

In addition, the second region may be disposed outside the first region.

In addition, the first area and the second area may include a portion overlapping with an active area where an image is displayed.

In addition, a third region in which the address electrode is exposed to the outside of the first dielectric layer may be positioned outside the second region of the rear substrate.

In addition, the first dielectric layer and the second dielectric layer may not be formed in the third region.

In addition, the multi-plasma display panel according to the present invention is a multi-plasma display panel comprising a plurality of plasma display panel disposed adjacent to each other, the plurality of plasma display panel is a front substrate, the scan electrode and the sustain electrode is disposed, respectively A rear substrate disposed to face the front substrate, a lower address electrode disposed on the rear substrate, a first dielectric layer disposed on the lower address electrode, an upper address electrode disposed on the first dielectric layer, and the upper address electrode It may include a second dielectric layer disposed on top of the.

In addition, another multi-plasma display panel according to the present invention is a multi-plasma display panel comprising a plurality of plasma display panel disposed adjacent, each of the plurality of plasma display panel is a front substrate, the scan electrode and the sustain electrode is disposed, A rear substrate disposed to face the front substrate, a first dielectric layer disposed on the rear substrate, and a second dielectric layer disposed on the first dielectric layer, wherein the first dielectric layer is formed in the first region of the back substrate; An address electrode is disposed between the second dielectrics, and an address electrode is disposed between the first dielectric layer and the second dielectric layer and between the first dielectric layer and the back substrate in the second region of the back substrate. Can be.

In the plasma display panel and the multi-plasma display panel according to the present invention, a bezel area and / or a seam area in which an image is not displayed by forming an address electrode formed on a rear substrate in a multi-layer structure is provided. The size of the area) can be reduced.

1 to 3 are views for explaining the structure and driving method of the plasma display panel;
4 to 15 are views for explaining the structure of the plasma display panel according to the present invention in more detail; And
17 to 24 illustrate a multi-plasma display panel according to the present invention.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. It is to be understood that the present invention is not intended to be limited to the specific embodiments but includes all changes, equivalents, and alternatives falling within the spirit and scope of the present invention.

In describing the present invention, terms such as first and second may be used to describe various components, but the components may not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

The term and / or may include a combination of a plurality of related items or any item of a plurality of related items.

When an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may be present in between Can be understood. On the other hand, when it is mentioned that an element is "directly connected" or "directly connected" to another element, it can be understood that no other element exists in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. The singular expressions may include plural expressions unless the context clearly dictates otherwise.

In the present application, the terms "comprises", "having", and the like are used interchangeably to designate one or more of the features, numbers, steps, operations, elements, components, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries can be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are, unless expressly defined in the present application, interpreted in an ideal or overly formal sense .

In addition, the following embodiments are provided to explain more fully to the average person skilled in the art. The shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity.

1 to 3 are views for explaining the structure and driving method of the plasma display panel.

The plasma display panel may implement an image in a frame including a plurality of subfields.

In detail, as illustrated in FIG. 1, the plasma display panel may include a rear substrate 211 on which a plurality of lower electrodes 213 and X intersect the plurality of upper electrodes 202 (Y) and 203 (Z). have.

Here, the upper electrodes 202 and 203 may include scan electrodes 202 and Y and sustain electrodes 203 and Z parallel to each other, and the lower electrode 211 may be referred to as an address electrode.

On the front substrate 201 where the scan electrodes 202 and Y and the sustain electrodes 203 and Z are formed, the discharge currents of the scan electrodes 202 and Y and the sustain electrodes 203 and Z are limited and the scan electrodes 202 and Y are restricted. ) And an upper dielectric layer 204 may be arranged to insulate between the sustain electrodes 203 and Z.

A protective layer 205 may be formed on the front substrate 201 where the upper dielectric layer 204 is formed to facilitate discharge conditions. The protective layer 205 may include a material having a high secondary electron emission coefficient, such as magnesium oxide (MgO) material.

Address electrodes 213 and X are formed on the rear substrate 211, and a first dielectric layer 215 and a second dielectric layer 216 are formed on the rear substrate 211 on which the address electrodes 213 and X are formed. Can be.

In addition, although not illustrated, the address electrode 213 may include a lower address electrode and an upper address electrode. This will be described in detail below.

Here, the first dielectric layer 215 and the second dielectric layer 216 may be referred to as a lower dielectric layer.

On top of the second dielectric layer 216, a partition space 212, such as a stripe type, a well type, a delta type, a honeycomb type, for partitioning a discharge cell, that is, a discharge cell, is formed. Can be. Accordingly, the first discharge cell emitting red (R) light, the second discharge cell emitting blue (B) light, and the green (Green) light between the front substrate 201 and the rear substrate 211. : G) A third discharge cell or the like that emits light can be formed.

In the discharge cell, the address electrode 213 may cross the scan electrode 202 and the sustain electrode 203. That is, the discharge cell is formed at the point where the address electrode 213 crosses the scan electrode 202 and the sustain electrode 203.

A predetermined discharge gas may be filled in the discharge cell partitioned by the partition wall 212.

In addition, a phosphor layer 214 that emits visible light for image display may be formed in the discharge cells partitioned by the partition wall 212. For example, a first phosphor layer that generates red light, a second phosphor layer that generates blue light, and a third phosphor layer that generates green light may be formed.

In addition, the address electrode 213 formed on the rear substrate 211 may have substantially the same width or thickness, but the width or thickness inside the discharge cell may be different from the width or thickness outside the discharge cell. . For example, the width or thickness inside the discharge cell may be wider or thicker than that outside the discharge cell.

When a predetermined signal is supplied to at least one of the scan electrode 202, the sustain electrode 203, and the address electrode 213, discharge may occur in the discharge cell. As such, when discharge is generated in the discharge cell, ultraviolet rays may be generated by the discharge gas filled in the discharge cell, and the ultraviolet rays may be irradiated onto the phosphor particles of the phosphor layer 214. Then, a predetermined image may be displayed on the screen of the plasma display panel 100 by the phosphor particles irradiated with ultraviolet rays to emit visible light.

An image frame for implementing gradation of an image in a plasma display panel is described below.

Referring to FIG. 2, a frame for implementing gray levels of an image may include a plurality of subfields SF1 to SF8.

In addition, the plurality of subfields may include a sustain period for implementing gradation according to an address period and a number of discharges for selecting discharge cells in which discharge cells will not occur or discharge cells in which discharge occurs. Period) may be included.

For example, in case of displaying an image with 256 gray levels, for example, one frame is divided into eight subfields SF1 to SF8 as shown in FIG. 2, and each of the eight subfields SF1 to SF8 is an address. It can include a period and a sustain period.

Alternatively, at least one subfield of the plurality of subfields of the frame may further include a reset period for initialization.

In addition, at least one subfield of the plurality of subfields of the frame may not include a sustain period.

Meanwhile, the weight of the corresponding subfield may be set by adjusting the number of sustain signals supplied in the sustain period. That is, a predetermined weight can be given to each subfield using the sustain period. For example, the weight of each subfield is 2 ⁿ by setting the weight of the first subfield to 2 ⁰ and the weight of the second subfield to 2 ¹ (where n = 0, 1, 2, 3, 4, 5, 6, 7) can be set to increase the ratio. As described above, gray levels of various images may be realized by adjusting the number of sustain signals supplied in the sustain period of each subfield according to the weight in each subfield.

In FIG. 2, only one image frame is composed of eight subfields. However, the number of subfields constituting one image frame may be variously changed. For example, one video frame may be configured with 12 subfields from the first subfield to the twelfth subfield, or one video frame may be configured with 10 subfields.

In addition, in FIG. 2, subfields are arranged in an order of increasing weight in one image frame. Alternatively, subfields may be arranged in an order of decreasing weight in one image frame. Subfields may be arranged regardless.

A driving waveform for driving the plasma display panel is as follows.

Referring to FIG. 3, in the reset period RP for initializing at least one subfield among a plurality of subfields of a frame, the reset signal RS is applied to the scan electrode Y. Can supply Here, the reset signal RS may include a rising ramp signal (Ramp-Up: RU) in which the voltage gradually rises and a falling ramp signal (Ramp-Down: RD) in which the voltage gradually falls.

For example, the rising ramp signal RU may be supplied to the scan electrode in the setup period SU of the reset period, and the falling ramp signal RD may be supplied to the scan electrode in the setdown period SD after the setup period. .

When the rising ramp signal is supplied to the scan electrode, a weak dark discharge, that is, setup discharge, occurs in the discharge cell by the rising ramp signal. By this setup discharge, the distribution of wall charges can be uniform in the discharge cells.

After the rising ramp signal is supplied, when the falling ramp signal is supplied to the scan electrode, a weak erase discharge, that is, a setdown discharge, occurs in the discharge cell. By this set-down discharge, wall charges such that address discharge can be stably generated can be uniformly retained in the discharge cells.

In the address period AP after the reset period, the scan reference signal Ybias having a voltage higher than the lowest voltage of the falling ramp signal may be supplied to the scan electrode.

In addition, in the address period, the scan signal Sc that falls from the voltage of the scan reference signal Ybias may be supplied to the scan electrode.

Meanwhile, the pulse width of the scan signal supplied to the scan electrode in the address period of at least one subfield may be different from the pulse width of the scan signal of another subfield. For example, the width of the scan signal in the subfield located later in time may be smaller than the width of the scan signal in the preceding subfield. In addition, the reduction of the scan signal width according to the arrangement order of the subfields can be made gradually, such as 2.6 Hz (microseconds), 2.3 Hz, 2.1 Hz, 1.9 Hz, or 2.6 Hz, 2.3 Hz, 2.3 Hz, 2.1 Hz. .... 1.9 ㎲, 1.9 ㎲ and so on.

As such, when the scan signal is supplied to the scan electrode, the data signal Dt may be supplied to the address electrode X corresponding to the scan signal.

When the scan signal and the data signal are supplied, an address discharge may be generated in the discharge cell to which the data signal is supplied while the voltage difference between the scan signal and the data signal and the wall voltage generated by the wall charges generated in the reset period are added. .

In addition, the sustain reference signal Zbias signal may be supplied to the sustain electrode in the address period in which the address discharge occurs so that the address discharge is effectively generated between the scan electrode and the address electrode.

In the sustain period SP after the address period, the sustain signal SUS may be supplied to at least one of the scan electrode and the sustain electrode. For example, a sustain signal may be alternately supplied to the scan electrode and the sustain electrode.

When such a sustain signal is supplied, the discharge cell selected by the address discharge is added with the wall voltage in the discharge cell and the sustain voltage Vs of the sustain signal, and a sustain discharge, i.e., display between the scan electrode and the sustain electrode when the sustain signal is supplied. Discharge may occur.

4 to 15 are views for explaining the structure of the plasma display panel according to the present invention in more detail. Hereinafter, the description of the parts described in detail above will be omitted.

Referring to FIG. 4, a first dielectric layer 215 and a second dielectric layer 216 may be formed on the back substrate 211, and a lower address electrode 410 and an upper address electrode 400 may be formed.

In detail, the lower address electrode 410 may be formed in a predetermined region of the rear substrate 211, and the first dielectric layer 215 may be formed on the lower address electrode 410. In addition, an upper address electrode 400 may be formed on the first dielectric layer 215.

Preferably, a lower address electrode 410 is formed in the second area A2 of the rear substrate 211, and a first portion 215a of the first dielectric layer 215 is formed on the lower address electrode 410. The first electrode 400a of the upper address electrode 400 is disposed on the first portion 215a of the first dielectric layer 215, and the first electrode 400a of the upper address electrode 400 is disposed. The second dielectric layer 216 may be formed on the upper portion.

In addition, the lower address electrode 410 may not be formed in the first region A1 of the rear substrate 211, and the second portion 215b of the first dielectric layer 215 may be formed. In addition, a second electrode 400b of the upper address electrode 400 is formed on the second portion 215b of the first dielectric layer 215, and an upper portion of the second electrode 400b of the upper address electrode 400 is formed. The second dielectric layer 216 may be formed thereon.

Here, the second area A2 of the rear substrate 211 may be disposed outside the first area A1.

In addition, the lower address electrode 410 may extend further in the outer direction of the rear substrate 211 than the upper address electrode 400.

In addition, the lower address electrode 410 may include a portion exposed to the outside of the first dielectric layer 215 in the third region A3 outside the second region A2. In this third area A3, a flexible substrate for electrically connecting the external driving circuit and the address electrode 213 may be connected to the lower address electrode 410.

In other words, in the first region A1 of the back substrate 211, an address electrode 213 is disposed between the first dielectric layer 215 and the second dielectric layer 216, and is formed outside the first region A1. In the second area A2, the address electrode 213 may be disposed between the first dielectric layer 215 and the back substrate 211 and between the first dielectric layer 215 and the second dielectric layer 216, respectively. .

In other words, the address electrode 213 disposed in the first area A1 of the rear substrate 211 may be divided into a plurality of parts of the second area A2 outside the first area A1. have.

Alternatively, the second dielectric layer A2 of the rear substrate 211 may include a portion in which the first dielectric layer 400 is disposed between the lower address electrode 410 and the upper address electrode 400.

In addition, an end of the upper address electrode 400 may be surrounded by the first dielectric layer 215 and / or the second dielectric layer 216.

In addition, the upper address electrode 400 and the lower address electrode 410 may be electrically connected. To this end, the address electrode 213 may further include a connection electrode 420 electrically connecting the upper address electrode 400 and the lower address electrode 410. The connection electrode 420 may pass through the first dielectric layer 215.

A method of manufacturing the first and second dielectric layers 215 and 216, the lower address electrode 410, and the upper address electrode 400 will be described below.

Referring to FIG. 5, as shown in (a), a second portion 215b of the first dielectric layer 215 may be formed in the first region A1 of the rear substrate 211. In this case, it is possible to have a structure as shown in Fig. 6A.

Subsequently, as shown in FIG. 5B, the lower address electrode 410, the connection electrode 420, and the upper address electrode 400 are formed on the rear substrate 211 on which the second portion 215b of the first dielectric layer 215 is formed. ) May form a second electrode 400b. Preferably, a second electrode 400b of the upper address electrode 400 is formed in the first area A1 of the rear substrate 211, and a second portion outside the first area A1 of the rear substrate 211 is formed. The lower address electrode 410 may be formed in the region A2 and the third region A3. In this case, it is possible to have a structure as shown in Fig. 6B.

Thereafter, as illustrated in FIG. 5C, the first portion 4215A of the first dielectric layer 215 may be formed on the lower address electrode 410 in the second area A2 of the rear substrate 211. have. In this case, it is possible to have a structure as shown in Fig. 7A.

Subsequently, as illustrated in FIG. 5D, the first electrode of the upper address electrode 400 is positioned on the first portion 215a of the first dielectric layer 215 in the second region A2 of the rear substrate 211. 400a may be formed. Here, the first electrode 400a of the upper address electrode 400 may be electrically connected to the second electrode 400b and / or the connection electrode 420 of the upper address electrode 400. In this case, it is possible to have a structure as shown in Fig. 7B.

Subsequently, although not illustrated, a second dielectric layer 216 may be formed on the upper address electrode 400.

In addition, as shown in FIG. 8, the upper address electrode 400 may include a portion crossing the lower address electrode 410. Preferably, the upper address electrode 400 may be disposed in parallel with the long side of the rear substrate 211, and a portion of the lower address electrode 410 may be disposed to intersect the upper address electrode 400. Do. For example, as in the second area A2 of FIG. 8, the lower address electrode 410 may be disposed to intersect the upper address electrode 400.

In addition, the upper address electrode 400 may be formed in a substantially straight line. In addition, the rear substrate 211 may include a portion where an interval between adjacent lower address electrodes 410 decreases toward the end of the rear substrate 211. For example, an interval between the lower address electrode 410 of the Xa address electrode and the lower address electrode 410 of the Xb address electrode may gradually decrease toward the short side SS of the rear substrate 211. Accordingly, the distance D3 between the lower address electrode 410 of the Xa address electrode and the lower address electrode 410 of the Xb address electrode in the second area A2 of the rear substrate 211 is outside the second area A2. The distance between the lower address electrode 410 of the Xa address electrode and the lower address electrode 410 of the Xb address electrode in the third region A3 may be greater than the distance D2.

In addition, an interval between adjacent address electrodes 213 in the first region A1 of the rear substrate 211 may be adjacent to each other in the second region A2 and the third region A3 of the rear substrate 211. It may be larger than the interval between (213). For example, in the second area A2 of the rear substrate 211, the distance D3 between the lower address electrode 410 of the Xa address electrode and the lower address electrode 410 of the Xb address electrode is the first area A1. It may be smaller than the distance D1 between the second electrode 400b of the upper address electrode 400 of the Xa address electrode and the second electrode 400b of the upper address electrode 400 of the Xb address electrode.

In addition, in the second area A2 of the rear substrate 211, the distance D3 between two adjacent lower address electrodes 410 may gradually decrease toward the end of the rear substrate 211.

In this structure, as in the case of Fig. 9, it is possible to form the upper address electrode 400 in a substantially straight line. In addition, the lower address electrode 410 disposed under the first dielectric layer 215 may be concentrated in an arbitrary area for electrical connection with the flexible substrate 900. Accordingly, the distance D2 between two adjacent lower address electrodes 410 may be smaller than the distance D1 between two adjacent upper address electrodes 400.

In addition, by attaching the flexible substrate 900 having the electrode 910 to the third region A3 of the rear substrate 211, the lower address electrode 410 and the electrode 910 of the flexible substrate 900 are electrically connected to each other. Can connect

In addition, although not shown, the flexible substrate 900 may be electrically connected to a driving circuit (not shown), so that a driving signal supplied by the driving circuit is supplied to the address electrode 213 through the lower address electrode 410. It is possible to be.

In addition, in the above structure, since the lower address electrode 410 is concentrated in a predetermined region, the upper address electrode 400 of the address electrode 213 may extend longer in a straight line. That is, the first electrode 400a of the upper address electrode 400 may extend longer. Accordingly, the size of the bezel area in which the image is not displayed can be reduced.

In addition, even if the bezel area BA is reduced, the flexible substrate 900 may be more easily connected to the address electrode 213.

In addition, the upper address electrode 400 and the lower address electrode 410 may include a portion disposed in an area overlapping with the discharge cells partitioned by the partition wall 212.

For example, as shown in FIG. 10, in the first area A1 of the rear substrate 211, the second electrode 400b of the upper address electrode 400 overlaps with the discharge cell partitioned by the partition wall 212. The first electrode 400a of the upper address electrode 400 in the second area A2 of the rear substrate 211 is disposed in an area overlapping with the discharge cell partitioned by the partition wall 212. Can be. In addition, the upper address electrode 400 may be formed to be substantially straight in an area overlapping the partition wall 212.

In addition, in the second area A2 of the rear substrate 211, the lower address electrode 410 is disposed in an area overlapping the partition 212, preferably in an area overlapping the discharge cell partitioned by the partition 212. It may include a portion to be.

As such, when the lower address electrode 410 includes a portion disposed in an area overlapping the partition wall 212, the size of the bezel area may be reduced by increasing the size of the area where the discharge cells are formed.

Referring to FIG. 11, the lower address electrode 410 is disposed between the front substrate 201 and the rear substrate 211 to seal the sealing portion 500 to seal the front substrate 201 and the rear substrate 211. Can be overlapped.

In addition, the lower address electrode 410 may be electrically connected to the flexible substrate 900 described above in the pad area PA outside the seal unit 500.

For example, the lower address electrode 410 may overlap the actual part 500 at the second long side (LS2) side of the rear substrate 211, and the second long side ( In the pad area PA of the LS2 side, the lower address electrode 410 may be exposed to the outside of the seal portion 400, and the lower address electrode 410 may be electrically connected to the flexible substrate 900. .

Meanwhile, as shown in FIG. 11, the lower address electrode 410 may not be formed on the first long side LS1 side corresponding to the second long side LS2 of the rear substrate 211. This structure may be a single scan structure. Unlike the case of FIG. 11, in the dual scan structure, the lower address electrode 410 may be formed on the first long side LS1 and the second long side LS2 of the rear substrate 211. Since the dual scan structure can be sufficiently inferred as a single scan structure, detailed description of the dual scan structure is omitted.

In addition, it may be disposed inside the seal portion 400 of the upper address electrode 400. Preferably, the upper address electrode 400 may be disposed in an area corresponding to the partition wall 212 disposed between the front substrate 201 and the rear substrate 211. Preferably, the upper address electrode 400 may be disposed in an area corresponding to the discharge cell partitioned by the partition 212, that is, in an area corresponding to an active area AA. Here, the effective area AA may be an area in which discharge cells are formed to display an image. In addition, the upper address electrode 400 may extend to a part of an area outside the effective area AA.

As such, since the upper address electrode 400 is disposed in the effective area AA, the length L2 of the upper address electrode 400 may be longer than the length L1 of the lower address electrode 410.

In addition, by forming the upper address electrode 400 between the first dielectric layer 215 and the second dielectric layer 216, it is possible to extend the upper address electrode 400 longer in the direction toward the seal portion 500, Accordingly, the size of the bezel area BA in which the image outside the effective area AA is not displayed can be reduced.

When the area where the discharge cells are partitioned by the partition 212 is referred to as the effective area AA, the first area A1 and the second area A2 are formed in the effective area AA as in the case of FIG. Can overlap. In other words, the first electrode 400a and the second electrode 400b of the upper address electrode 400 may include a portion overlapping the partition 212. In addition, a portion of the lower address electrode 410 may also include a portion overlapping the partition wall 212.

In another aspect, in the first region A1 of the rear substrate 211, an address electrode 213 may be disposed between the first dielectric layer 215 and the second dielectric layer 216, and the rear substrate 211. Address electrode 213 may be disposed between the first dielectric layer 215 and the second dielectric layer 216 and between the first dielectric layer 215 and the back substrate 211 in the second region A2 of FIG. It is.

In addition, a third region A3 in which the address electrode 213 is exposed to the outside of the first dielectric layer 215 is positioned outside the second region A2 of the rear substrate 211, and the third region A3 is located. In the first dielectric layer 215 and the second dielectric layer 216 is not formed.

In addition, as shown in FIG. 13, the connection electrode 420 electrically connecting the upper address electrode 400 and the lower address electrode 410 may be formed in an oblique direction with respect to the rear substrate 211. In this case, the length L3 of the connection electrode 420 penetrating the first dielectric layer 215 may be larger than the thickness T1 of the first dielectric layer 215. In the case of FIG. 4, the length of the connection electrode 420 penetrating the first dielectric layer 215 may be substantially the same as the thickness T1 of the first dielectric layer 215. That is, the length L3 of the connection electrode 420 penetrating the first dielectric layer 215 may be greater than or substantially equal to the thickness T1 of the first dielectric layer 215.

In addition, the first electrode 400a and the second electrode 400b of the upper address electrode 400 may be formed in different processes as in the case of FIG. 5. Accordingly, as in the case of FIG. 14, the width W10 at the connection portion between the first electrode 400a and the second electrode 400b may be larger than the widths W20 and W30 of the other portions.

In addition, since the upper address electrode 400 and the connection electrode 420 are connected at the connection portion between the first electrode 400a and the second electrode 400b, the connection between the upper address electrode 400 and the connection electrode 420 is performed. The width W10 of the upper address electrode 400 in the portion may also be considered to be larger than the widths W20 and W30 of the upper address electrode 400 in the other portion.

In addition, at least one of the first dielectric layer 215 and the second dielectric layer 216 may overlap the seal 500.

For example, as in the case of FIG. 15, the first dielectric layer 215 and the second dielectric layer 216 may overlap the seal 500. In this case, the size of the bezel area BA in which an image is not displayed may be further reduced.

Alternatively, although not illustrated, the first dielectric layer 215 of the first dielectric layer 215 and the second dielectric layer 216 overlaps the seal 500, and the second dielectric layer 216 does not overlap the seal 500. It is also possible.

Alternatively, it is possible to vary the thickness of the second dielectric layer 216 according to the position. For example, as shown in FIG. 16, the thickness T10 of the second dielectric layer 216 is formed in the first region A1 of the rear substrate 211, and the thickness of the second dielectric layer 216 is formed in the second region A2. It is possible to make it thicker than thickness T11. In other words, the thickness T10 of the second dielectric layer 216 at the position where the second electrode 400b of the upper address electrode 400 is formed is the position where the first electrode 400a of the upper address electrode 400 is formed. It may be larger than the thickness T11 of the second dielectric layer 216.

In this case, the distance S1 from the rear substrate 211 to the second electrode 400b of the upper address electrode 400 is from the rear substrate 211 to the first electrode 400a of the upper address electrode 400. It may be less than the distance (S2) of.

17 to 24 illustrate a multi-plasma display panel according to the present invention. Hereinafter, a description thereof will be omitted for the parts described above in detail. For example, all of the features of the plasma display panel described above with reference to FIGS. 1 to 16 may be applied to the following multi-plasma display panel.

Referring to FIG. 17, the multi-plasma display panel 10 according to the present invention may include a plurality of plasma display panels 100, 110, 120, and 130 disposed adjacent to each other.

The first-first driving unit 101 and the second-first driving unit 102 may supply driving signals to the first panel 100 among the plurality of plasma display panels 100 to 130. Here, the first-first driving unit 101 and the first-second driving unit 102 may be merged into one integrated driving unit.

In addition, the 2-1 driving unit 111 and the 2-2 driving unit 112 may supply driving signals to the second panel 110.

As described above, it is possible to set different driving units to supply driving signals to the plasma display panels 100, 110, 120, and 130, respectively.

Each driving unit may be a driving board.

In addition, a seam area SA, 140, 150 may be formed between two adjacent plasma display panels. The core regions 140 and 150 may be referred to as a region between two adjacent plasma display panels.

In the multi-plasma display panel 10, since the individual plasma display panels 100 to 130 are disposed adjacent to each other, an image is formed between the two adjacent plasma display panels 100 to 130. Can be formed.

The manufacturing method of the multi-plasma display panel is as follows.

Referring to FIG. 18, as shown in (a), a seal 500 is formed at an edge of at least one of the rear substrate 211 having the front substrate 201 and the exhaust hole 200 formed therein, as shown in (b). The front substrate 201 and the rear substrate 211 may be bonded to each other.

Thereafter, as illustrated in (c), an exhaust tip 220 may be connected to the exhaust hole 200, and an exhaust pump 230 may be connected to the exhaust tip 220.

In addition, by using the exhaust pump 230, the impurity gas remaining in the discharge space between the front substrate 201 and the rear substrate 211 can be discharged to the outside, and argon (Ar), neon (Ne), xenon Discharge gas such as (Xe) can be injected into the discharge space.

In this way, the discharge space between the front substrate 201 and the rear substrate 211 may be sealed.

Thereafter, as shown in (a) of FIG. 19, a portion of the front substrate 201 and the rear substrate 211 is cut along a predetermined cutting line CL in a state where the front substrate 201 and the rear substrate 211 are bonded together. Can be. Here, it is possible to perform grinding along with cutting. For example, one long side and one short side of the front substrate 201 and the rear substrate 211 may be cut and ground.

Then, at least one of the front substrate 201 and the rear substrate 211 may be prevented from excessively protruding from the cut portion as illustrated in FIGS. 19B and 19C, thereby displaying an image. It can reduce the size of the parts that are not.

In addition, as shown in (b) and (c) of FIG. 19, it is also possible to cut the seal 500 together in a process of cutting a part of the front substrate 201 and the rear substrate 211. As such, when the actual portion 500 is cut, the size of the portion where the image is not displayed may be further reduced.

A multi-plasma display panel may be manufactured by arranging a plurality of plasma display panels manufactured by the method of FIGS. 18 to 19 adjacent to each other.

For example, as in the case of FIG. 20, the first panel 100, the second panel 110, the third panel 120, and the fourth panel 130 may be arranged in a 2 × 2 matrix form. Do.

In addition, it may be preferable to arrange the first panel 100, the second panel 110, the third panel 120, and the fourth panel 130 so that the cutting surfaces are adjacent to each other.

For example, in the first panel 100, the second panel 110, the third panel 120, and the fourth panel 130, the front side of the second short side SS2 and the second long side LS2, respectively. A cutting and grinding process such as 19 may be performed.

In addition, the first panel 100 and the second panel 110 are disposed such that the second short side SS2 of the first panel 100 and the second short side SS2 of the second panel 110 are adjacent to each other. The third panel 120 and the fourth panel 130 may be disposed such that the second short side SS2 of the third panel 120 and the second short side SS2 of the fourth panel 130 are adjacent to each other.

In addition, the first panel 100 and the third panel 120 are disposed such that the second long side LS2 of the first panel 100 and the second long side LS2 of the third panel 120 are adjacent to each other. It is possible to arrange the second panel 110 and the fourth panel 130 such that the second long side LS2 of the second panel 110 and the second long side LS2 of the fourth panel 130 are adjacent to each other. .

In the multi-plasma display panel according to a comparative example different from the present invention, the observer may recognize that the image implemented in the multi-plasma display panel 10 appears discontinuously by the seam areas 140 and 150.

On the other hand, as in the case of FIG. 20 of the present invention, when the first panel 100, the second panel 110, the third panel 120 and the fourth panel 130 are disposed so that the cutting surface is adjacent to each other In addition, the size of the core regions 140 and 150 of the multi-plasma display panel 10 may be reduced, thereby realizing a more natural image. 1 to 16, the first dielectric layer is formed on the rear substrate 211 in the first panel 100, the second panel 110, the third panel 120, and the fourth panel 130. 215 and a second dielectric layer 216 are formed, an upper address electrode 400 is formed between the first dielectric layer 215 and the second dielectric layer 216, and the first dielectric layer 215 and the rear substrate ( If the lower address electrode 410 is formed between 211, the core region 140 of the multi-plasma display panel according to the present invention can be reduced because the size of the region where no image is displayed in each panel 100 to 130 can be reduced. , It is possible to further reduce the size. In addition, even if the bezel area BA is reduced in each of the panels 100 to 130, the flexible substrate 900 may be more easily connected to the address electrode 213.

Accordingly, the plasma display panel described in detail with reference to FIGS. 1 to 16 may be applied to the multi-plasma display panel.

The relationship between the first panel 100 and the third panel 120 is the same as the case of FIG. 21.

Referring to FIG. 21, the lower address electrode 410C is disposed on the first long side LS1 of the rear substrate 211C of the third panel 120, and the lower address electrode 410C extends to the outside of the seal 500C. Can be extended. Accordingly, the address electrode 213C of the third panel 120 may be connected to the flexible substrate (not shown) on the first long side LS1 side of the rear substrate 211C.

In addition, the lower address electrode 410A may be disposed on the second long side LS2 side of the rear substrate 211A of the first panel 100, and the lower address electrode 410A may extend to the outside of the seal 500A. have. Accordingly, the address electrode 213A of the first panel 100 may be connected to the flexible substrate (not shown) on the second long side LS2 side of the rear substrate 211A.

In addition, the cutting and grinding processes of FIG. 19 may be applied to the first long side LS1 of the first panel 100 and the second long side LS2 of the third panel 120.

Accordingly, while reducing the size of the core area SA between the first panel 100 and the third panel 120, the address electrodes 213A and 213C and the flexible substrate of the first and third panels 100 and 120 may be reduced. The connection process of (not shown) can be made easy.

Here, the case in which the first panel 100, the second panel 110, the third panel 120, and the fourth panel 130 are arranged in a 2 × 2 matrix form is described. It is possible to arrange a plurality of panels in various forms such as 1 × 2 matrix form or 2 × 1 matrix form.

For example, or as in the case of Fig. 22, it is possible to arrange the panels in the form of a 4x4 matrix. An example of a 4x4 matrix form is described here, but a matrix form of 3x3 or more may be applied substantially the same.

As such, when configuring a multi-plasma display panel using a larger number of panels, it is possible to arrange the panels in substantially the same pattern.

Of the first panel 1000, the second panel 1010, the fifth panel 1100, and the sixth panel 1110 of the first to sixteenth panels 1000 to 1330 arranged in a 4 × 4 matrix form in FIG. 22. The case will be described as an example of FIG. 23.

Referring to FIG. 23, the first panel 1000 and the second panel 1010 are disposed adjacent to each other in the first direction, and the first panel 1000 and the fifth panel 1100 intersect the first direction. The sixth panel 1110 and the second panel 1010 are disposed adjacent to each other in two directions, and the sixth panel 1110 and the fifth panel 1100 are disposed adjacent to each other in the second direction. It can be arranged adjacent to each other.

In addition, in the first panel 1000, the second panel 1010, the fifth panel 1100, and the sixth panel 1110, the first and second short sides SS1 and SS2, and the first and second long sides LS1, LS2) may perform the cutting and grinding process as shown in FIG. 19.

In addition, the first panel 1000 and the second panel 1010 are disposed such that the second short side SS2 of the first panel 1000 and the first short side SS1 of the second panel 1010 are adjacent to each other. The fifth panel 1100 and the sixth panel 1110 may be disposed such that the second short side SS2 of the fifth panel 1100 and the first short side SS1 of the sixth panel 1110 are adjacent to each other.

In addition, the first panel 1000 and the fifth panel 1100 are disposed such that the second long side LS2 of the first panel 1000 and the first long side LS1 of the fifth panel 1100 are adjacent to each other. It is possible to arrange the second panel 1010 and the sixth panel 1110 such that the second long side LS2 of the second panel 1010 and the first long side LS1 of the sixth panel 1110 are adjacent to each other. .

Even in this structure, the first and second dielectric layers and the upper and lower address electrodes may be disposed on the rear substrate of each panel 1000 to 1330.

The relationship between the first panel 1000 and the fifth panel 1100 will be described with reference to FIG. 24.

Referring to FIG. 24, the lower address electrode 410F is disposed on the first long side LS1 of the rear substrate 211F of the fifth panel 1100, and the lower address electrode 410F overlaps the seal 500F. Can be. Accordingly, the address electrode 213F of the fifth panel 1100 may be connected to the flexible substrate (not shown) on the first long side LS1 of the rear substrate 211F.

In addition, a cutting and grinding process may also be applied to the first long side LS1 of the fifth panel 1100. Accordingly, as shown in FIG. 24, the first long side of the rear substrate 211F of the fifth panel 1100 may be applied. A flexible substrate (not shown) may be connected to the side of the lower address electrode 410F at the LS1 side. In addition, a cutting and grinding process may be applied to the second long side LS2 of the fifth panel 1100.

In addition, the lower address electrode 410A may be disposed on the first long side LS1 of the rear substrate 211E of the first panel 1000, and the lower address electrode 410A may overlap the seal 500A. Accordingly, the address electrode 213A of the first panel 1000 may be connected to the flexible substrate (not shown) on the first long side LS1 side of the rear substrate 211A.

In addition, a cutting and grinding process may also be applied to the first long side LS1 of the first panel 1000. Accordingly, as shown in FIG. 24, the first long side of the rear substrate 211A of the first panel 1000 may be applied. A flexible substrate (not shown) may be connected to the side of the lower address electrode 410A at the LS1 side.

In addition, a cutting and grinding process may be applied to the first long side LS1 of the first panel 1000.

Here, the first long side LS1 of the first panel 1000 and the second long side LS2 of the fifth panel 1100 may be disposed adjacent to each other. Accordingly, the size of the core area SA between the first panel 1000 and the fifth panel 1100 may be further reduced.

As described above, it is to be understood that the technical structure of the present invention can be embodied in other specific forms without departing from the spirit and essential characteristics of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

Claims

A front substrate on which scan electrodes and sustain electrodes are disposed;
A rear substrate disposed to face the front substrate;
A lower address electrode disposed on the rear substrate;
A first dielectric layer disposed on the lower address electrode;
An upper address electrode disposed on the first dielectric layer; And
A second dielectric layer disposed over the upper address electrode;
Plasma display panel comprising a.

The method of claim 1,
And the upper address electrode and the lower address electrode are connected to each other.

The method of claim 2,
And a connection electrode formed between the upper address electrode and the lower address electrode to electrically connect the upper address electrode and the lower address electrode.

The method of claim 3, wherein
And the connection electrode penetrates through the first dielectric layer.

The method of claim 3, wherein
And a width of the upper address electrode at a connection portion between the upper address electrode and the connection electrode is larger than a width at another portion.

The method of claim 1,
The length of the connection electrode is greater than or equal to the thickness of the first dielectric layer.

The method of claim 1,
And a portion where the upper address electrode and the lower address electrode cross each other.

The method of claim 1,
The lower address electrode includes a portion exposed to the outside of the first dielectric layer.

The method of claim 1,
And a length of the lower address electrode is shorter than a length of the upper address electrode.

The method of claim 1,
Between the front substrate and the rear substrate, a partition wall for partitioning the discharge cell is further disposed,
And the upper address electrode and the lower address electrode include a portion disposed in an area overlapping the discharge cell.

The method of claim 1,
A seal portion is further disposed between the front substrate and the rear substrate.
And the lower address electrode includes a portion overlapping the seal portion.

The method of claim 11,
And the upper address electrode is disposed inside the seal portion.

The method of claim 11,
And the lower address electrode extends in an outer direction of the rear substrate more than the upper address electrode.

The method of claim 1,
And the upper address electrode is formed in a substantially straight line.

The method of claim 1,
And a portion of the gap between two adjacent lower address electrodes is smaller than a distance between two adjacent upper address electrodes.

A front substrate on which scan electrodes and sustain electrodes are disposed;
A rear substrate disposed to face the front substrate;
A first dielectric layer disposed on the back substrate; And
A second dielectric layer disposed over the first dielectric layer;
Including,
In the first region of the rear substrate, an address electrode is disposed between the first dielectric layer and the second dielectric layer.
And an address electrode disposed between the first dielectric layer and the second dielectric layer and between the first dielectric layer and the back substrate in the second region of the rear substrate.

17. The method of claim 16,
The second region is a plasma display panel disposed outside the first region.

The method of claim 17,
And the first area and the second area overlap a portion of an active area in which an image is displayed.

The method of claim 17,
And a third region in which the address electrode is exposed to the outside of the first dielectric layer is disposed outside the second region of the rear substrate.

The method of claim 19,
And wherein the first dielectric layer and the second dielectric layer are not formed in the third region.

A multi-plasma display panel comprising a plurality of plasma display panels disposed adjacent to each other,
Each of the plurality of plasma display panels
A front substrate on which scan electrodes and sustain electrodes are disposed;
A rear substrate disposed to face the front substrate;
A lower address electrode disposed on the rear substrate;
A first dielectric layer disposed on the lower address electrode;
An upper address electrode disposed on the first dielectric layer; And
A second dielectric layer disposed over the upper address electrode;
Multi-plasma display panel comprising a.

A multi-plasma display panel comprising a plurality of plasma display panels disposed adjacent to each other,
Each of the plurality of plasma display panels
A front substrate on which scan electrodes and sustain electrodes are disposed;
A rear substrate disposed to face the front substrate;
A first dielectric layer disposed on the back substrate; And
A second dielectric layer disposed over the first dielectric layer;
Including,
In the first region of the rear substrate, an address electrode is disposed between the first dielectric layer and the second dielectrics,
And an address electrode disposed between the first dielectric layer and the second dielectric layer and between the first dielectric layer and the back substrate in the second region of the rear substrate.