KR20110119610A - Silicon wafer having proximity gettering ability at low-temperature processes and manufacturing method therefor - Google Patents

Abstract

PURPOSE: A silicon wafer with an adjacent gathering ability in a low temperature process and a manufacturing method thereof are provided to perform annealing processing after rapid thermal processing on the silicon wafer, thereby easily arranging high density BMD(Bulk Micro Defects) in a surface adjacent region with a low thermal history. CONSTITUTION: A silicon wafer with a front surface, a rear surface, a boundary edge part, and an area between the front surface and rear surface is prepared. The density and distribution of bit defects are controlled by rapid thermal processing for 1 second to 2 minutes with respect to the silicon wafer. An oxygen precipitates nucleus is grown by annealing 2 to 8 hours at a temperature lower than the temperature of rapid thermal processing.

Description

Silicon Wafer Having Proximity Gettering Capability in Low Temperature Process and Manufacturing Method therefor {Silicon Wafer Having Proximity Gettering Ability at Low-Temperature Processes and Manufacturing Method Therefor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon wafer used in the manufacture of a semiconductor device and a method of manufacturing the same, and more particularly to a technique for controlling the concentration and distribution of BMDs (Bulk Micro Defects) produced in a semiconductor device manufacturing process.

Generally, a silicon wafer is manufactured through a process of growing a silicon single crystal ingot, a slicing process of slicing the ingot into a disk-shaped wafer, and a polishing (polishing) process of mirror-mirroring the wafer surface to provide a semiconductor device. Will be. However, in the growth process of the silicon single crystal, oxygen is included in the silicon single crystal, in particular, as crystal defects and unwanted impurities in accordance with the growth history. This impregnated oxygen grows into oxygen precipitates due to the heat applied in the manufacturing process of the semiconductor device. The oxygen precipitates reinforce the strength of the silicon wafer and capture metal contaminants, such as internal gettering. It also shows beneficial properties, such as acting as a c-site, but also shows harmful properties that cause leakage current and failure of semiconductor devices.

Accordingly, a wafer that exists at a predetermined density and distribution in a bulk region of a predetermined depth is required while substantially no oxygen deposit is present in a denuded zone from a wafer surface on which a semiconductor element is to be formed to a predetermined depth. do. In the semiconductor device manufacturing process, these are commonly referred to as bulk micro-defects (BMDs) including oxygen deposits and bulk stacking faults generated in the bulk region. Hereinafter, the oxygen deposits in the bulk region and BMD are not distinguished. I will use it.

As a technique for providing a wafer in which the concentration and distribution of the BMD is controlled, process variables such as seed rotation speed, crucible rotation speed, melt surface and heat shield when growing a silicon single crystal ingot The initial oxygen concentration and crystal defect concentration can be determined by the melt gap, the gap between the ingot, the pull speed, the hot zone design change, and the third element doping such as nitrogen or carbon. Techniques for controlling BMD concentration by regulating have been proposed.

In addition, the following techniques are known as techniques for controlling BMD concentration and distribution through heat treatment during a wafer processing process in addition to the method of controlling the growth process variable or the growth history.

First, in Korean Patent No. 395391, the center surface (bulk region) of the wafer through a rapid thermal process (RTP) or rapid thermal annealing (RTA) for several seconds to several tens of seconds at a temperature exceeding 1150 ° C for the wafer. There is provided a wafer having a crystal lattice vacancy concentration profile that peaks at and decreases generally in the front direction of the wafer. In addition, Republic of Korea Patent No. 450676, through a rapid heat treatment for 5 seconds to several tens of seconds at a temperature of 1100 ~ 1200 ℃, as shown in Figure 1, to provide a wafer having a concentration profile of the oxygen precipitate of approximately M shape Doing. In addition, the Republic of Korea Patent No. 531552, through the two-step rapid heat treatment for 1 to 5 seconds and 1 to 10 seconds at a temperature of 1120 ~ 1180 ℃ and 1200 ~ 1230 ℃, respectively, containing oxygen deposits and bulk deposition defects The concentration of BMD provides a wafer with a profile as shown in FIG. 2.

It should be noted that the distribution and concentration of the BMDs shown in FIGS. 1 and 2 do not appear immediately after wafer fabrication, but rather the heat applied by the process of manufacturing a semiconductor element on the wafer (exposed by active heat treatment). Thermal budget, which includes heat and heat that is loaded onto the wafer by performing a particular process at a predetermined temperature, hereinafter referred to as 'following thermal history'. Thus, the wafer manufacturer has sampled the manufactured wafers to simulate the subsequent thermal history to verify that the manufactured wafers meet the BMD requirements of the semiconductor device manufacturer (equivalent to 800 ° C 4 hours + 1000 ° C 16 hours). Will be performed. The BMD concentrations and distributions of FIGS. 1 and 2 are only results confirmed by such an equivalent heat treatment. If the subsequent thermal history applied during fabrication of the semiconductor device changes, a totally different result may be obtained.

On the other hand, there is an increasing demand for miniaturization, high speed, large capacity, low power, and low price of semiconductor devices, and semiconductor device manufacturing technologies have been miniaturized and highly integrated through device structure, material change, and process condition change. For example, the technique of forming the metal wiring of a semiconductor element from copper or a copper alloy instead of the conventional aluminum or aluminum alloy is employ | adopted, and process temperature is changing with the low thermal history of about 800-900 degreeC or less. In addition, mobile devices such as personal digital assistants (PDAs), MP3s, Portable Multimedia Players (PMPs), and 3G mobile phones are designed for small size, high speed, large capacity, low power, and low cost. Multi-Chip Package (MCP), which stacks and packages different types of semiconductor chips, such as flash and mobile DRAM, is adopted.As a result, the wafer is finished after back grinding in the semiconductor device manufacturing process. The thickness is reduced to 50 μm or less.

As a result of the increase of metal impurity contaminants, the subsequent thermal history lowering, and the final thickness reduction of the device due to the adoption of such copper wiring, the silicon wafer used as the substrate of the semiconductor device has physical characteristics such as flatness and particles. In addition, new quality features are required, called proximity gettering capability in low temperature processes.

The foregoing prior arts are techniques that use a conventional high temperature process (high thermal history) and provide a wafer for use in the fabrication of devices having a thick thickness of the denude zone and the final thickness of the device. It is difficult to cope with the changed device fabrication process and thinner device thickness, such as the adoption, the lowering of the subsequent heat history. That is, when the wafer according to the above-described prior arts is used in the above-described process and fabrication of the device, the BMD serving as a gettering site is not generated or is insufficiently generated, and the gettering capability is very insufficient.

Therefore, in order to meet the above-described needs, the technical problem to be solved by the present invention is not only to generate a high density BMD in the vicinity of the surface in a semiconductor device manufacturing process having a low thermal history, but also to easily generate a BMD even at a low thermal history. A silicon wafer and its manufacturing method are provided.

In order to achieve the above technical problem, in the present invention, an annealing treatment is performed in which an oxygen precipitation nucleus is grown from the point defect, followed by a rapid heat treatment to control the point defect which becomes a BMD by a subsequent heat history.

That is, the method of manufacturing a silicon wafer according to an aspect of the present invention comprises the steps of preparing a silicon wafer having a front, rear, edge edge portion and the area between the front and rear; Rapidly heat treating the silicon wafer for 1 second to 2 minutes to control the density and distribution of point defects that become BMDs by subsequent thermal history; And annealing for 2 to 8 hours at a temperature lower than the temperature during the rapid heat treatment to grow an oxygen precipitate nucleus from the point defects.

Here, the rapid heat treatment, the low temperature rapid heat treatment step of rapid heat treatment for 1 to 60 seconds at the first temperature (1100 ~ 1200 ℃); And a high temperature rapid heat treatment step of rapid heat treatment for 1 to 60 seconds at a second temperature (1200 to 1300 ° C.) higher than the first temperature.

The annealing may include a low temperature annealing step of annealing for 1 to 4 hours at a third temperature (700 to 900 ° C.); And a high temperature annealing step of annealing for 1 to 4 hours at a fourth temperature (900 to 1100 ° C.) higher than the third temperature.

Furthermore, the method may further include heat treating the silicon wafer subjected to the rapid heat treatment and annealing at 800 ° C. for 2 hours and at 1000 ° C. for 4 hours.

According to another aspect of the present invention, a silicon wafer includes: a silicon wafer having a front surface, a rear surface, an edge edge portion, and an area between the front surface and the rear surface, the silicon wafer comprising: a first denude zone formed to a predetermined depth from a surface of the front surface; A second denude zone formed from a surface of the rear surface to a predetermined depth; And a bulk region formed between the first and second dinude zones, wherein a BMD having a size of 30 nm or more is generated in the bulk region by thermal history within 2 hours at 800 ° C. and 4 hours at 1000 ° C. It is characterized by.

In addition, a silicon wafer according to another aspect of the present invention has a front surface, a back surface, an edge edge portion, and a region between the front surface and the rear surface, wherein the silicon wafer is predetermined from a surface of the front surface in a silicon wafer before being put into manufacture of a semiconductor device. A first denude zone formed to a depth; A second denude zone formed from a surface of the rear surface to a predetermined depth; And a bulk region formed between the first and second denude zones, wherein a BMD having a size of 30 nm or more is generated in the bulk region.

Here, it is preferable that the density of BMD generated in the bulk region is greater than or equal to ⁴ × ^{10 8} ea / cm ³ by the heat history of 2 hours at 800 ° C. and 4 hours at 1000 ° C., and the first and second di The depth of the nude zone is preferably within 30 μm from the front and rear surfaces, respectively.

As described above, according to the present invention, the silicon wafer is subjected to annealing followed by annealing, so that a high density BMD can be easily generated in the vicinity of the surface even by a low thermal history, and thus, the silicon wafer is introduced into a semiconductor device manufacturing process. It is possible to provide a silicon wafer previously produced with a BMD. Therefore, the wafer of the present invention is particularly suitably used for the manufacture of semiconductor devices in which the subsequent thermal history is being lowered (low temperature process), which can contribute to the improvement of the yield of the semiconductor devices, and furthermore, excellent in the initial contamination of the semiconductor device manufacturing process. Can get gettering ability

1 is a graph illustrating an oxygen precipitate concentration profile of a silicon wafer subjected to rapid heat treatment according to the prior art.
FIG. 2 is a graph showing a concentration profile of a bulk micro-defect (BMD) including an oxygen precipitate and a bulk deposition defect of a wafer subjected to a two-step rapid heat treatment according to another conventional technology.
3 is an overall process flow diagram illustrating a manufacturing process of a wafer according to an embodiment of the present invention.
4 is a process diagram of a heat treatment process during fabrication of a wafer according to an embodiment of the present invention.
5 is a micrograph of the BMD distribution after the rapid heat treatment according to the prior art to generate the BMD.
6 is a photomicrograph of the BMD distribution after the rapid heat treatment and annealing according to an embodiment of the present invention after generating the BMD.

Hereinafter, a silicon wafer and a method of manufacturing the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

3 is an overall process flow diagram illustrating a manufacturing process of a wafer according to an embodiment of the present invention. Referring to FIG. 3, the silicon wafer manufacturing method of this embodiment is largely a process of preparing a wafer (S110 and S120), a heat treatment process (S130 and S140) to control a BMD, a process of generating a BMD and inspecting it as necessary. (S150) and post-processing and shipping steps (S160) such as polishing and washing. Here, the main part of the present invention is the process S130-S150, which process is explained in detail with the process diagram shown in FIG. On the other hand, the remaining processes (S110, S120 and S160) will be described briefly because it can be carried out according to a conventional method known in the art.

First, as a step of preparing a silicon wafer, an ingot-type silicon single crystal is grown by a method such as a Czochralski (CZ) method (S110). That is, a seed crystal is immersed in the melted silicon melt in the crucible, and the silicon single crystal is grown by pulling while adjusting the crystal pulling rate V and the temperature gradient G in the growth direction at the melt interface.

At this time, the single crystal silicon grown by the Czochralski method has a vacancy-rich region and interstitial according to the point defect characteristics according to the result of controlling the pulling speed (V) and the temperature gradient (G) at the melt interface. It is divided into a defective area such as an interstitial rich region, a vacancy pure region, an interstitial pure region, and the like. Ingots grown in the double vacancy-rich region and the interstitial rich region have a semiconductor originated precipitate (COP) and dislocation loops after wafer fabrication. It is desirable to grow so that mainly only the vacancy-pure region and the interstitial pure region exist. However, the control of such a defect area is not easy and the defect area becomes uneven along the length and radial direction of the ingot (wafer), so that the BMD is not uniform in the longitudinal direction of the ingot (per wafer depending on the sliced position) and also BMD is not uniform in the radial direction of the wafer, there is a problem that the density is formed low. In addition, the denude zone of the wafer is deeply formed at about 30 to 50 µm or more, and the vertical distribution of the BMD has a peak at the center of the wafer, thereby showing low proximity gettering efficiency. Therefore, heat treatment for BMD control described later is required.

Next, the grown silicon single crystal ingot is processed into a disk-shaped wafer (S120). That is, the ingot is sliced into a disk shape, and a lapping process is performed to mechanically polish the wafer to remove defects caused by the slicing process and to control thickness and flatness. It also undergoes an etching process to chemically remove the defects due to the lapping process.

Subsequently, the heat treatment process (S130, S140) for controlling the BMD in accordance with an embodiment of the present invention, but may be performed as a separate process, it is preferably performed in the so-called donor killing (Donor Killing) step. . Donor killing, according to the Republic of Korea Patent No. 450676 described above, is to prevent the oxygen contained in the ingot in the form of ions to act as a donor to the impurities injected during the manufacturing of semiconductor devices, usually about 700 ℃ Rapid heat treatment at 30 seconds or diffusion heat treatment at about 750 ℃ for about 30 minutes to make oxygen in the form of oxygen precipitates.

Heat treatment processes (S130 and S140) for BMD control according to the present embodiment are specifically performed as follows.

First, rapid heat treatment (S130) is performed. The pre-processed wafer is loaded into a rapid heat treatment apparatus preheated to room temperature or T ₀ (500-700 ° C.), and the first stage low temperature (here, low temperature means that the wafer is performed at a lower temperature than the two stage rapid heat treatment described later). The temperature is increased to a predetermined temperature increase rate (eg 5 ° C./sec) up to T ₁ (1100˜1200 ° C.) for rapid heat treatment. When the temperature in the equipment reaches T ₁ relatively short predetermined time t _1, and maintaining T ₁ for a (e.g. 1 to 60 seconds and more preferably from 1 to about 10 seconds), the nitrogen-containing gas and / or argon or helium, etc. Flow inert gas of.

The temperature is then increased at a predetermined rate of increase (eg 5 ° C./sec) to T ₂ (1200-1300 ° C., preferably 1200-1230 ° C.) higher than T ₁ for a two-step high temperature rapid heat treatment. When the temperature in the equipment reaches T ₂ a relatively short predetermined period of time t ₂ and kept at the T ₂ while (e.g. 1 to 60 seconds and more preferably from 1 to 20 seconds), the nitrogen-containing gas and / or argon or helium, etc. Flow inert gas of.

Subsequently, the density and distribution of the bacon defect, which is a point defect that becomes a BMD, are controlled by subsequent heat history. That is, by adjusting the temperature, time, atmospheric gas, etc. of the first and second stages of rapid heat treatment, point defects can be distributed in a high density in an area close to the wafer surface, and uniform in the wafer vertical direction, that is, from the front surface of the wafer to the rear surface and in the radial direction of the wafer. Can be distributed.

Subsequently, annealing (S140) for relatively long heat treatment is performed as compared to rapid heat treatment. In general, rapid heat treatment and annealing are performed in other heat treatment equipment. Thus, unloading the wafer after rapid heat treatment in the rapid heat treatment equipment and preheating to room temperature or T ₃ (700 to 900 ° C., more preferably 750 to 850 ° C.) The wafer is loaded into annealing equipment such as a diffusion furnace. Subsequently, one-step low temperature annealing is performed by holding T ₃ for a relatively long predetermined time t ₃ (eg 1-4 hours, more preferably 1.5-3 hours).

The temperature in the annealing equipment is then raised to T ₄ (900-1100 ° C., more preferably 950-1050 ° C.), followed by a relatively long predetermined time t ₄ (eg 1-4 hours, more preferably 1.5-3). by keeping the holding time T ₄ for a) performs a 2-step high-temperature annealing.

Then, the point defects (baconcies) whose density and distribution are controlled in the bulk region of the wafer by the rapid heat treatment (S130) are grown and stabilized as oxygen precipitation nuclei by annealing (S140).

Subsequently, the BMD generation and inspection process S150 is performed. In the BMD generation and inspection process S150, first, a heat treatment that simulates a subsequent thermal history in a semiconductor device manufacturing process is performed. At this time, the heat treatment that simulates the subsequent heat history is performed in a shorter time than that of a conventional general subsequent heat treatment (usually, 800 ° C. 4 hours + 1000 ° C. 16 hours). This heat treatment proceeds, for example, about 800 degreeC 2 hours + 1000 degreeC 4 hours.

5 and 6, in order to confirm the effect of the present invention, the wafer and the rapid heat treatment + annealing according to the present invention, which performs only the conventional rapid heat treatment, respectively, and the subsequent heat treatment of 800 ℃ 2 hours + 1000 ℃ 4 hours Next, a micrograph of the result of confirming the actual BMD generation and its density and distribution. Specifically, in the wafer of the prior art and the present invention shown in Figures 5 and 6, respectively, first of all, two steps of rapid heat treatment (about 5 seconds at 1120-1180 ° C + about 20 seconds at 1200-1230 ° C) Was performed. Subsequently, two steps of annealing (about 2 hours at about 800 ° C. plus about 2 hours at about 1000 ° C.) were performed on only the wafer of the present invention shown in FIG. 6. Subsequently, a subsequent heat treatment was performed to simulate the subsequent thermal history of 800 DEG C 2 hours + 1000 DEG C 4 hours in common for both wafers, and then the wafer was cut in the vertical direction for 5 minutes with a bright etching solution for the cross section. After etching, the cross section was observed with an optical microscope.

As a result, as shown in FIG. 5, in the case of the wafer subjected to the rapid heat treatment, the wafer is very insufficiently formed in a small size (about 30 nm or less) that BMD is hardly produced or observed, and thus very low gettering in the low temperature process. It can be predicted to have only ability. On the other hand, in the case of a wafer subjected to rapid heat treatment and annealing according to the present invention, as shown in Figure 6, uniformly 30nm or more (more preferably 50nm or more) at a high density (4x10 ⁸ ea / cm ³ or more) in the bulk region It can be seen that the BMD having the size of) is generated. In other words, it can be seen that the wafers subjected to rapid heat treatment and annealing according to the present invention easily generate BMDs even with low thermal history in the semiconductor device manufacturing process.

On the other hand, as the thickness of the device decreases, the depth of the denude zone (thickness of a layer without defects such as BMD) should also be smaller than in the related art, and the wafers of FIG. 5 and FIG. The depth of this denude zone can be adjusted to 30 micrometers or less (more preferably 15 micrometers or less) by adjusting process conditions, such as temperature, time, and atmospheric gas, in the rapid heat processing process (S130) mentioned above.

This BMD generation and inspection step (S150) is an optional step that can confirm the effect of the present invention, omitting this step and immediately polishing, cleaning, etc. of the wafer after the rapid heat treatment (S130) and annealing (S140) After the post-treatment, the product may be shipped as a product (S160) and provided to a semiconductor device manufacturing process. This silicon wafer shipped with the BMD generation and inspection process S150 omitted, is a wafer in which BMDs can be easily generated even by the low subsequent thermal history of the semiconductor device manufacturing process, as described above.

It is also possible to ship the wafer on which the BMD is generated as a product by performing the subsequent heat treatment of the low thermal history described above. Since such wafers have already produced a BMD having a size of 30 nm or more (more preferably, 50 nm or more) uniformly at a high density (4x10 ⁸ ea / cm ³ or more) in the bulk region before being introduced into the semiconductor device manufacturing process, It is possible to getter the source of contamination from the beginning of the manufacturing process. Further, in consideration of the thermal history of the semiconductor device manufacturing process, the temperature and / or time of the above-described subsequent heat treatment (2 hours at 800 ° C + 2 hours at 1000 ° C) may be reduced. That is, as much as a part of the heat history applied in the semiconductor device manufacturing process may be performed as a subsequent heat treatment (S150) for generating the above-described BMD can be shipped as a product.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

For example, in the above-described embodiment, the rapid heat treatment (S130) and the annealing (S140) were performed in two steps, respectively, but may be performed in one step, respectively, any one of the rapid heat treatment (S130) and annealing (S140) You can do it in two steps and the other in one step. Furthermore, a rapid heat treatment step of another temperature may be inserted between the first and second steps of the rapid heat treatment performed in two steps. In addition, the time or temperature of the above-described rapid heat treatment (S130) and annealing (S140) may be adjusted outside the above-described range as long as the object of the present invention is achieved.

Claims (11)

Preparing a silicon wafer having a front surface, a back surface, an edge edge portion, and an area between the front surface and the back surface;
Rapidly heat treating the silicon wafer for 1 second to 2 minutes to control the density and distribution of point defects that become BMDs by subsequent thermal history; And
And annealing at a temperature lower than the temperature during the rapid heat treatment for 2 to 8 hours to grow an oxygen precipitated nucleus from the point defects. A silicon wafer having a front side, a back side, an edge edge portion, and an area between the front side and the back side,
A first denude zone formed from a surface of the front surface to a predetermined depth;
A second denude zone formed from a surface of the rear surface to a predetermined depth; And
And a bulk region formed between the first and second denude zones.
A silicon wafer, wherein a BMD having a size of 30 nm or more is produced in the bulk region by thermal history within 2 hours at 800 ° C. and within 4 hours at 1000 ° C. The method of claim 2,
The silicon wafer, characterized in that the density of the BMD generated in the bulk region is more than 4x10 ⁸ ea / cm ³ by the heat history of 2 hours at 800 ℃ and 4 hours at 1000 ℃. The method according to claim 2 or 3,
And a BMD having a size of 50 nm or more in the bulk region by thermal history within 2 hours at 800 ° C. and within 4 hours at 1000 ° C. The method according to claim 2 or 3,
And the depths of the first and second denude zones are within 30 μm from the front and rear surfaces, respectively. The method according to claim 2 or 3,
And the depths of the first and second denude zones are less than 15 μm from the front and rear surfaces, respectively. A silicon wafer having a front surface, a back surface, an edge edge portion, and an area between the front surface and the back surface, wherein the silicon wafer before being put into manufacture of the semiconductor device,
A first denude zone formed from a surface of the front surface to a predetermined depth;
A second denude zone formed from a surface of the rear surface to a predetermined depth; And
And a bulk region formed between the first and second denude zones.
A BMD having a size of 30 nm or more is formed in the bulk region. The method of claim 7, wherein
The silicon wafer, characterized in that the density of the BMD is 4x10 ⁸ ea / cm ³ or more. The method according to claim 7 or 8,
A silicon wafer having a size of 50 nm or more in said bulk region by thermal history within 2 hours at 800 ° C and within 4 hours at 1000 ° C. The method according to claim 7 or 8,
And the depths of the first and second denude zones are within 30 μm from the front and rear surfaces, respectively. The method according to claim 7 or 8,
And the depths of the first and second denude zones are less than 15 μm from the front and rear surfaces, respectively.

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