KR20110118336A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

According to the present invention, in forming a metal line and a word line of a sub word line driver, a wide metal is formed to form a contact at both ends of the narrow metal wire so as to replace the narrow metal wire and to be connected to the contact. By forming a plurality of metal wirings having wirings, a semiconductor device and a method of manufacturing the same can be stably manufactured in a lithography process of the metal wirings.

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a layout of a metal wiring corresponding to a unit cell array of a DRAM (Dynamic Random Access Memory (DRAM)).

BACKGROUND With the rapid spread of information media such as computers, semiconductor memory devices are also rapidly developing. In terms of its function, the semiconductor memory device must operate at a high speed and have a large storage capacity. In order to meet these demands, it is required to develop process equipment or process technology for manufacturing semiconductor memory devices having low manufacturing atoms, and having improved integration, reliability, and electrical characteristics for accessing data.

Photolithography is one of the methods for improving the degree of integration of semiconductor memory devices. Photolithography is a technique for exposing and developing a photoresist material with a deep ultra violet (DUV) light source, which is a short wavelength chemically amplified type such as ArF (193 nm) or VUV (157 nm), to form a fine pattern.

As semiconductor device sizes become smaller and smaller, controlling critical dimensions of pattern line widths has become an important issue when applying photolithography technology. In general, the speed of the semiconductor device is faster as the critical dimension of the pattern line width, that is, the pattern line size is smaller, and the performance of the device is also improved. However, it is difficult to form a line and space pattern of 40 nm or less in a single exposure process due to the limitation of photolithography technology using ArF exposure equipment having a numerical aperture of 1.2 or less. Accordingly, double patterning technology has been developed as part of resolution enhancement and process margin expansion of photolithography technology. Double patterning is a technique for exposing and developing two masks on a photoresist-coated wafer, respectively, to form complex patterns, dense patterns, and isolated patterns. .

On the other hand, since the double patterning technique uses two different masks for patterning, the manufacturing cost and turn-around-time are lower than the patterning technique using the single mask, resulting in lower throughput. . In addition, when forming a pattern having a pitch smaller than the resolution of the exposure equipment in the cell region, the aerial images are overlapped to obtain a pattern of a desired shape, and overlay misalignment at the time of alignment. There are several disadvantages such as this occurring.

In order to improve this disadvantage, double exposure etch technology (DEET) and spacer patterning technology (SPT) has been developed and applied to the semiconductor device mass production process. DEET is a technique of forming a first pattern having a line width twice as large as a desired pattern line width, and then forming a second pattern having the same line width period as the first pattern between neighboring first patterns.

However, since the DEET method uses two kinds of masks or one mask to form a pattern having a desired resolution, the process step is complicated, manufacturing costs are increased, and the alignment of the pattern when forming the second photoresist pattern is achieved. Misalignment is likely to occur in the process.

Another technique, the SPT method, is a technique in which a self-align method is applied to prevent misalignment by performing a mask process only once to form a pattern of a cell region. However, the process step is complicated because an additional mask process is required to form a pattern in the core and peri regions or to separate the pattern portion of the mini cell block region. Since it is difficult to control the line width, the uniformity of the fine pattern line width in the semiconductor device determined by the line width of the spacer is low.

Here, in the case of highly integrated semiconductor memory devices, a metal wiring of not only a cell transistor array but also a word line driving device for driving the same or a sense amplifier (sense amplifier) for directly amplifying a signal stored in the cell is smaller than the resolution of the exposure apparatus. Although it is necessary to implement a pattern, since the metal wiring of the core circuit generally has a geometrically complicated shape, there is a problem that it is difficult to implement using the double patterning technique or the spacer patterning described above.

1 is a layout showing a semiconductor device according to the prior art. Referring to FIG. 1, a word line 100 and a metal line 110 of a sub-word line driver in a core region are illustrated. Here, the sub word line driver selects a sub word line to which a specific memory cell of a unit cell array is connected, and the sub word line driver is composed of a plurality of CMOS inverter circuits. The word line 100 of the sub word line driver is connected to the metal line 110, wherein the metal line 110 is connected to the source / drain region of the transistor and the word line signal output terminal.

Here, the metal wire 110 connected to the word line 100 is implemented as a wire having a narrow width such as 'A'. That is, when the width of the word line 100 is reduced in order to form a highly integrated cell transistor, the width of the metal line 110 should also be reduced. However, due to the limitations of the current exposure apparatus, there is a problem in that the metal wiring 110 having a narrow width cannot be formed by exposing and patterning at one time.

In order to solve the above-mentioned conventional problems, the present invention, in forming the word line and the metal wiring of the sub word line driver, contacts are formed at both ends of the narrow metal wiring so as to replace the narrow metal wiring. And forming a plurality of metal wires having a wide metal wire to be connected to the contact, thereby providing a semiconductor device and a method for manufacturing the device stably during a lithography process of the metal wire.

The present invention includes a metal wire connected to a plurality of different layers on a semiconductor substrate, wherein the metal wire includes a first metal wire connected to a word line and a second metal wire connected to both ends of the first metal wire. A sub word line driver is provided.

Preferably, the width of the second metal wiring is larger than the width of the first metal wiring.

Preferably, it is connected to the second metal wire by using a contact at both ends of the first metal wire.

In addition, the present invention includes the step of forming a metal wiring connected to a plurality of different layers on the semiconductor substrate, the metal wiring is a first metal wiring connected to the word line and a second connected to both ends of the first metal wiring Provided is a method of manufacturing a sub word line driver, comprising a metal wiring.

The forming of the metal interconnection may include forming a first intermetallic insulation layer on the semiconductor substrate, etching the first intermetallic insulation layer using the first metal interconnection mask, and then forming a conductive material. Forming a first metal wire by filling the second metal wire; forming a second intermetallic insulating film on the entire surface including the first metal wire; and using the contact mask until both ends of the first metal wire are exposed. After etching the intermetallic insulating film, depositing a conductive material to form a contact, forming a third intermetallic insulating film on the entire surface including the contact, and using a second metal wiring mask until the contact is exposed. After etching the third intermetallic insulating layer, depositing a conductive material to form a second metal wiring.

Preferably, the width of the second metal wiring is larger than the width of the first metal wiring.

Preferably, the contact is connected to both ends of the narrowest region of the width of the first metal wiring.

According to the present invention, in forming a metal line and a word line of a sub word line driver, a wide metal is formed to form a contact at both ends of the narrow metal wire so as to replace the narrow metal wire and to be connected to the contact. By forming a plurality of metal wirings having wirings, there is an advantage in that the device can be stably manufactured during a lithography process of the metal wirings.

1 is a layout showing a semiconductor device according to the prior art.
2 and 3 are layout views showing a semiconductor device according to the present invention.
4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the present invention.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

2 and 3 are layout views showing a semiconductor device according to the present invention. Referring to FIG. 2, a first metal line 200 of a sub-word line driver in a core region is shown. Here, the sub word line driver selects a sub word line to which a specific memory cell of a unit cell array is connected. The word line (not shown) of the sub word line driver is connected to the first metal line 200, wherein the first metal line 200 is connected to the source / drain region of the transistor and the word line signal output terminal.

Here, the first metal wire 200 is a complicated structure having both a wide width and a narrow width. At this time, the patterning process cannot be performed by the conventional double patterning method or the spacer patterning method because of the narrow width of the first metal wiring 200. However, in the present invention, the first metal wiring 200 Stable contact by forming the contact 210 at both ends of the region of the first metal wiring 200 having the narrowest width and having the second metal wiring 220 having a wide width so as to be connected to the contact 210. In this case, the width of the second metal wire 220 may be wider than the width of the first metal wire 200.

4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the present invention. Referring to FIG. 4, a first intermetal dielectric 40 is formed on the semiconductor substrate 20. After the first intermetallic insulating layer 40 is etched using the first metal wiring mask, the conductive material is embedded to form the first metal wiring 200 spaced apart from each other at regular intervals. In this case, the first metal wire 200 is a complicated structure having both a narrow width and a wide width. In addition, it is preferable to use a silicon-based conductor such as a metal alloy, a metal compound, or a doped polysilicon as the conductive material.

Next, after forming the second intermetallic insulating film 60 on the entire surface including the first metal wiring 200, a photosensitive film pattern (not shown) is formed by an exposure and development process using a contact mask. The second intermetallic insulating layer 60 is etched using the photoresist pattern as an etch mask until both ends of the first metal wire 200 are exposed to form a contact region (not shown).

Next, after the conductive material is filled in the contact region, the contact 210 is formed by chemical mechanical polishing until the second intermetallic insulating layer 60 is exposed. In this case, the contact 210 may be connected to both ends of the narrowest area of the first metal wire 200.

Next, the third intermetallic insulating film 80 is formed on the entire surface including the second intermetallic insulating film 60 in the same manner as the process of forming the first metal wiring 200, and then using the second metal wiring mask. After etching the third intermetallic insulating layer 80, a conductive material is embedded to form a second metal wire 220 connected to the contact 210. In this case, it is preferable to use a silicon-based conductor such as a metal alloy, a metal compound, or a doped polysilicon as the embedded conductive material. In addition, the first and second metal wires 200 and 220 may be formed using a damascene process.

As described above, in the present invention, in forming the word line and the metal wiring of the sub word line driver, a contact is formed at both ends of the narrow metal wiring so as to replace the narrow metal wiring and connected to the contact. By forming a plurality of metal wires having metal wires as wide as possible, there is an advantage that the device can be stably manufactured during a lithography process of the metal wires.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (7)

A metal wire connected to a plurality of different layers on the semiconductor substrate, wherein the metal wire includes a first metal wire connected to a word line and a second metal wire connected to both ends of the first metal wire. Sub wordline driver. The method of claim 1,
And the width of the second metal wire is larger than the width of the first metal wire. The method of claim 1,
And a sub word line driver connected to both ends of the first metal wire by using a contact. Forming a metal wire connected to a plurality of different layers on the semiconductor substrate, wherein the metal wire includes a first metal wire connected to a word line and a second metal wire connected to both ends of the first metal wire. A method of manufacturing a sub wordline driver, characterized in that. The method of claim 4, wherein
Forming the metal wiring
Forming a first intermetallic insulating film on the semiconductor substrate;
Etching the first intermetallic insulating layer using the first metal wiring mask, and then filling a conductive material to form a first metal wiring;
Forming a second intermetallic insulating film on the entire surface including the first metal wire;
Etching the second intermetallic insulating layer using a contact mask until both ends of the first metal wiring are exposed, and then depositing a conductive material to form a contact;
Forming a third intermetallic insulating film on the entire surface including the contact; And
And etching the third intermetallic insulating layer using a second metal wiring mask until the contact is exposed, and depositing a conductive material to form a second metal wiring. Manufacturing method. The method of claim 5, wherein
And the width of the second metal wire is larger than the width of the first metal wire. The method of claim 5, wherein
And connecting the contacts to both ends of the narrowest region of the width of the first metal wiring.

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