KR20110117354A - Bottom emission organic light emitting display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a bottom-emitting organic light-emitting display device and a method of manufacturing the same, by manufacturing a substrate of a bottom-emitting organic light-emitting display device with six masks, thereby reducing manufacturing costs and processing time of the bottom-emitting organic light-emitting display device. Forming a semiconductor layer on the substrate; Forming a gate insulating film on an entire surface of the substrate including the semiconductor layer; Forming a gate electrode on the gate insulating layer so as to correspond to the semiconductor layer; Forming an interlayer insulating film on the gate insulating film including the gate electrode; Selectively removing the insulating interlayer to form contact holes exposing both sides of the semiconductor layer; Stacking a first electrode, a metal layer, and a second electrode on the interlayer insulating layer in order to form a source electrode and a drain electrode connected to both sides of the semiconductor layer through the contact hole; Selectively removing the second electrode and the metal layer to expose the first electrode to form an anode electrode; And forming a bank and a spacer to have an opening that exposes a portion of the anode electrode.

Description

Back-emitting organic light emitting display device and method for manufacturing same {BOTTOM EMISSION ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bottom emission type organic light emitting display device, and more particularly, to a bottom emission type organic light emitting display device and a method of manufacturing the same, which reduce manufacturing cost and processing time by reducing the number of masks for manufacturing a substrate.

Video display devices that implement a variety of information as screens are core technologies of the information and communication era, and are being developed in a direction of thinner, lighter, portable and high performance. BACKGROUND ART As a flexible display that can be bent in pursuit of space and convenience is demanded, an organic light emitting display device that controls the amount of light emitted from the organic light emitting layer as a flat panel display device has recently been in the spotlight.

The organic light emitting diode display uses an electroluminescence phenomenon in which light is emitted by binding energy when the electrons and holes are injected into and transferred to the organic light emitting layer by applying an electric field to the cathode and the anode formed at both ends of the organic light emitting layer. Electrons and holes are paired in the organic light emitting layer, and then emit light while falling from the excited state to the ground state.

Such an organic light emitting display device can be thinned and can be formed on a flexible transparent substrate, such as plastic, and is lower than that of a plasma display panel or an inorganic electroluminescence (EL) display. It can drive at a voltage (about 10V or less), resulting in relatively low power consumption. In addition, the light weight and color have excellent characteristics have attracted the attention of many people.

Meanwhile, the organic light emitting diode display may be classified into a top emission type and a bottom emission type according to a direction in which light generated from the emission layer is emitted. The top emission type emits light in a direction opposite to the substrate on which the pixels are arranged, and the bottom emission type emits light toward the lower substrate. The top emission type is configured to direct the light emitted from the organic emission layer downward.

Hereinafter, a conventional bottom emission type organic light emitting diode display will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a conventional bottom emission type organic light emitting display substrate.

First, the buffer layer 105 is formed on the substrate 100. The semiconductor layer 110 is patterned on the buffer layer 105 by using a first mask.

A gate electrode 120 is formed on the semiconductor 110 layer, a metal is deposited on the gate insulating layer 120, and patterned using a second mask to correspond to a center portion of the semiconductor 110 layer. 130 is formed.

Impurities are implanted into the semiconductor layer 110 using a third mask to form source and drain regions 110a and 110c of the semiconductor layer 110, and the source region 110a and the drain region 110c. The area in between is defined as the channel area 110b.

An interlayer insulating layer 150 is formed over the entire upper surface of the gate electrode 130. A first contact hole 140H is formed in the interlayer insulating layer 150 to expose the source and drain regions 110a and 110c of the semiconductor layer 110 by using a fourth mask.

Subsequently, the source electrode and the drain electrode 160 may be in contact with the source and drain regions 110a and 110c of the semiconductor layer 110 using a fifth mask on the first contact hole 140H and the interlayer insulating layer 150. ) Is formed by patterning, and a protective layer 170 is formed over the entire upper surface of the source electrode and the drain electrode 160.

The second contact hole 180H exposing the source electrode and the drain electrode 160 is etched in the passivation layer 170 by using a sixth mask, and the second contact hole 180H is formed by etching the second mask. The anode electrode 190 is formed to contact the source electrode and the drain electrode 160 through the contact hole 180H.

A bank and spacer 195 having an opening exposing a part of the surface of the anode electrode 190 is formed over the entire substrate including the anode electrode 190 by using an eighth mask.

As described above, a substrate of a bottom emission type organic light emitting display device is manufactured using eight masks, and an anode electrode 190, an organic emission layer (not shown), and a cathode electrode (not shown) are formed on the substrate. A sealing agent (not shown) and a glass cap (not shown) are used to encapsulate an organic light emitting display device (not shown) including an anode electrode 190, an organic light emitting layer (not shown), and a cathode electrode (not shown). To form more.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the substrate of the bottom emission type organic light emitting display device is manufactured with six masks, thereby reducing the manufacturing cost and the process time of the bottom emission type organic light emitting display device. There is this.

The manufacturing method of the bottom emission organic light emitting display device of the present invention for achieving the above object, Forming a semiconductor layer on the substrate; Forming a gate insulating film on an entire surface of the substrate including the semiconductor layer; Forming a gate electrode on the gate insulating layer so as to correspond to the semiconductor layer; Forming an interlayer insulating film on the gate insulating film including the gate electrode; Selectively removing the insulating interlayer to form contact holes exposing both sides of the semiconductor layer; Stacking a first electrode, a metal layer, and a second electrode on the interlayer insulating layer in order to form a source electrode and a drain electrode connected to both sides of the semiconductor layer through the contact hole; Selectively removing the second electrode and the metal layer to expose the first electrode to form an anode electrode; And forming a bank and a spacer to have an opening that exposes a portion of the anode electrode.

Forming an organic light emitting layer in the opening; Forming a cathode on the bank, the spacer, and the organic light emitting layer; And encapsulating the glass cap on the substrate by interposing a sealing agent on an outer side of the substrate.

The forming of the source electrode and the drain electrode and the forming of the anode electrode may include using a halftone mask.

The halftone mask is divided into a light blocking region, a transmission region, and a halftone region, wherein the halftone region corresponds to the anode electrode forming portion, and the light blocking region is aligned to correspond to the source electrode and the drain electrode.

In addition, according to another embodiment of the present invention, there is provided a method of manufacturing a bottom emission organic light emitting display device, the method comprising: forming a semiconductor layer on a substrate; Forming a gate insulating film on an entire surface of the substrate including the semiconductor layer; Forming a gate electrode on the gate insulating layer so as to correspond to the semiconductor layer; Forming an interlayer insulating film on the gate insulating film including the gate electrode; Selectively removing the insulating interlayer to form contact holes exposing both sides of the semiconductor layer; Sequentially stacking a first electrode and a metal layer on the interlayer insulating layer to form a source electrode and a drain electrode connected to both sides of the semiconductor layer through the contact hole; Selectively removing the metal layer to expose the first electrode to form an anode electrode; And forming a bank and a spacer to have an opening that exposes a portion of the anode electrode.

The forming of the source electrode and the drain electrode and the forming of the anode electrode may include using a halftone mask, wherein the halftone region of the halftone mask corresponds to the anode electrode forming region, and the light blocking region is It is characterized in that aligned with the source electrode and the drain electrode.

In addition, the bottom emission organic light emitting display device of the present invention for achieving the same object, the substrate; A buffer layer formed on the substrate; A semiconductor layer including a source, a drain region, and a channel region formed on the buffer layer; A gate insulating film formed on an entire surface of the substrate including the semiconductor layer; A gate electrode corresponding to the channel region and formed on the gate insulating layer; An interlayer insulating film covering the gate insulating film including the gate electrode; A contact hole for exposing a source and a drain region of the semiconductor layer in the interlayer insulating film; A source electrode and a drain electrode connected to the source and drain regions of the semiconductor layer through the contact hole, wherein a first electrode, a metal layer, and a second electrode are stacked; An anode formed on said interlayer insulating film integrally with said first electrode; And a bank and a spacer having an opening exposing a portion of the anode electrode.

The thin film transistor including the semiconductor layer, the gate electrode, the source electrode, and the drain electrode includes an oxide thin film transistor (Oxide TFT), an organic thin film transistor (Organic TFT), an amorphous silicon thin film transistor (Amorphous Silicon TFT), and a polysilicon thin film transistor ( Poly Silicon TFT).

The first electrode and the second electrode are any one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO), respectively.

The metal layer is a metal selected from aluminum (Al), aluminum alloy, silver (Ag), silver alloy, molybdenum (Mo), titanium (Ti) and copper (Cu).

The first electrode is ITO, the metal layer is a silver alloy, the second electrode is characterized in that the ITO.

The thickness of the first electrode and the second electrode is 100 kPa ~ 1500 kPa.

The bank and the spacer may be at least one polymer material of polyimide, polyacrylic and polystyrene.

As described above, the bottom emission type organic light emitting diode display and the manufacturing method thereof have the following effects.

The source electrode, the drain electrode, and the anode electrode are formed into one halftone mask, thereby reducing the number of masks by one. In addition, since the source electrode, the drain electrode, and the anode electrode are formed with one mask, the insulating film and the protective film existing between the source electrode, the drain electrode, and the anode electrode can be formed with only one protective film, thereby forming the insulating film. By eliminating the process, one mask can be further reduced.

Accordingly, by manufacturing the substrate of the bottom emission type organic light emitting diode display of the present invention with a total of six masks, the number of two masks is reduced compared to the eight masks of the related art, thereby reducing the manufacturing cost of the bottom emission type organic light emitting diode display. In addition, the process can be simplified to improve productivity and manufacturing yield.

1 is a cross-sectional view of a conventional bottom emission type organic light emitting display substrate.
2 to 8 are cross-sectional views illustrating a method of manufacturing a bottom emission type organic light emitting diode display according to the present invention.
9 is a cross-sectional view of a bottom emission type organic light emitting display substrate according to the present invention.

Hereinafter, a bottom emission type organic light emitting diode display and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

2 to 8 are cross-sectional views illustrating a method of manufacturing a bottom emission organic light emitting device according to the present invention.

As shown in FIG. 2, a buffer layer 205 is formed on the substrate 200. The semiconductor layer 210 is formed in a predetermined region on the substrate 200 by using a first mask on the buffer layer 205.

A gate insulating layer 220 is formed on the semiconductor 210 layer, and the gate electrode 230 is patterned on the gate insulating layer 220 by using a second mask so as to correspond to a central portion of the semiconductor 210 layer. Form. The gate electrode 230 is formed and a gate line (not shown) in one direction is integrally formed with the gate electrode 230.

Impurities are implanted into the semiconductor layer 210 using a third mask to define source, drain regions 210a and 210c and channel region 210b of the semiconductor layer 210. In this case, the third mask may be omitted, and impurities may be implanted using the gate electrode 230 as a mask.

In addition, an interlayer insulating film 250 is formed over the entire gate insulating film including the gate electrode 230, and the source and drain regions of the semiconductor layer 210 are formed in the interlayer insulating film 250 using a fourth mask. First contact holes 240H exposing 210a and 210c are formed, respectively.

Subsequently, the first electrode 290a and the metal layer are buried in the first contact hole 240 to contact the source and drain regions 210a and 210c of the semiconductor layer 210. 291a and the 2nd electrode 292a are laminated | stacked in order. Here, the first electrode 290a, the metal layer 291a, and the second electrode 292a form a multilayer 260a, and are stacked in this order without interposing an insulating film therebetween.

The metal layer 291a and the first electrode 290a are preferably selected from materials having different etching selectivity.

The first electrode 290a and the second electrode 292a are each selected from materials of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO), respectively, and the metal layer 291a ) Is selected from aluminum (Al), aluminum alloy, silver (Ag), silver alloy, molybdenum (Mo), titanium (Ti) and copper (Cu).

Preferably, the first electrode 290a is made of ITO, the metal layer 291a is made of silver alloy, and the second electrode 292a is made of ITO. In addition, the thickness of the first electrode 290a and the second electrode 292a may be 100 kPa to 1500 kPa, most preferably, the thickness of the first electrode 290a is 100 ± 30 kPa and the second electrode 292a ) Should be 500 ± 200Å.

On the other hand, the multilayer 260a later forms a source / drain integrated pattern 260c shown in FIG. 8, wherein the first electrode 290b is relatively the second electrode 292a and the metal layer 291a. It is formed over a pixel area with a larger area than that, and functions as an anode electrode (not shown).

In the present invention, since the first electrode 290b and the anode electrode (not shown) are integrally formed, a separate forming process of the anode electrode (not shown) is not required.

First, a half-tone mask is prepared as a fifth mask to form the source / drain integrated pattern 260c and an anode electrode (not shown). In some cases, the halftone mask may be replaced with a diffraction exposure mask.

As shown in FIG. 3, a photoresist 296 is coated on the multilayer 260a. Subsequently, a halftone mask 297 having a light blocking region a, a transmission region b, and a halftone region c is positioned on the multilayer 260a to which the photoresist 296 is applied.

Here, the light blocking region a corresponds to an upper portion of the source and drain regions 210a and 210c of the semiconductor layer 210, and the halftone region c is a position to form an anode electrode corresponding to the pixel region. To match. The transmissive area b is aligned to be positioned at a portion that does not correspond to the light blocking area a and the halftone area c.

When the photoresist 296 is exposed and developed by using the halftone mask, as shown in FIG. 4, the first photoresist pattern 296a remains at a full thickness corresponding to the light blocking region a. Only a part of the portion corresponding to the halftone region c remains compared to the light blocking region a.

In the illustrated embodiment, the photoresist 296 has been described as an example having positive photosensitive characteristics. If the photoresist 296 has negative photosensitive properties, the transmissive region of the halftone mask is illustrated. If the light shielding area is inverted with the halftone mask of FIG. 3, the same patterning effect as shown is obtained.

Subsequently, when the multilayer 260a is etched using the first patterned photoresist pattern 296a, a portion of the multilayer 260a corresponding to the transmission region b as shown in FIG. 5. Is removed.

After the first patterning using the halftone mask, the multilayer pattern 260b including the first electrode 290b, the metal layer 291b, and the second electrode 292b is formed as shown in FIG. 5.

Subsequently, in an ashing process using an oxygen (O 2) plasma or the like, the first photoresist pattern 296a corresponding to the halftone region c is removed, and as shown in FIG. 6, the second photoresist pattern ( 296b) is formed. In this case, a portion of the second photoresist pattern 296b corresponding to the light blocking region a remains thin. That is, compared to the first photoresist pattern 296a of FIG. 5, the thickness of the second photoresist pattern 296b corresponding to the light blocking region a of FIG. 6 is thinner.

In addition, when the second photoresist pattern 296b is used as a mask, the metal layer 291b and the second electrode 292b are selectively etched while leaving only the first electrode 290b of the multilayer pattern 260b. As illustrated in FIG. 7, the metal layer 291c and the second electrode 292c are patterned to form a triple layer source / drain integrated pattern 260c.

The source / drain integrated pattern 260c includes a source electrode s, a drain electrode d, and an anode electrode (not shown). In this case, a data line (not shown) in a direction crossing the gate line (not shown) is formed simultaneously with the source electrode s.

Here, the first electrode 290b below the source / drain integrated pattern 260c remains over the pixel area and functions as an anode electrode.

Next, as shown in FIG. 8, the second photoresist 296b is removed.

And, as shown in Figure 9, on the substrate 200 including the source / drain integrated pattern 260c and the anode electrode, a polymer material of at least one of polyimide, polyacrylic, and polystyrene is applied, and the sixth A bank and spacer 295 having an opening that selectively removes it by using a mask to expose a portion (pixel area) of the first electrode 290b of the source / drain integrated pattern 260c. To form.

Here, the bank is a pattern dividing a plurality of pixel areas for displaying an image, and the spacer formed integrally with the bank is protruded on the bank to prevent physical damage caused by pressure from the outside. do.

As described above, a substrate of a bottom emission type organic light emitting display device is manufactured using six masks, an organic emission layer (not shown) is formed in an opening defined by the bank and the spacer 295, and the organic emission layer (not shown). ) And a cathode (not shown) is formed on the bank and the spacer 295.

Subsequently, an encapsulation is performed by facing a glass cap (not shown) on the substrate with a sealing agent (not shown) outside the substrate.

Meanwhile, the multilayer 260a may be formed of only the first electrode 290a and the metal layer 291a. In this case, the first electrode 290a is selected from materials such as indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO), and the metal layer 291a includes aluminum (Al), Aluminum alloy, silver (Ag), silver alloy, molybdenum (Mo), titanium (Ti) and copper (Cu) is selected.

It is preferable that the first electrode 290a is made of ITO, and the metal layer 291a is made of silver alloy.

In addition, the thickness of the first electrode 290a may be 100 kPa to 1500 kPa, and most preferably, the thickness of the first electrode 290a may be 500 ± 200 kPa.

In this case, the multilayer 260a later forms a source / drain integrated pattern 260c by using a halftone mask divided into a light blocking region, a transmission region, and a halftone region, among which the first electrode 290a is formed. Is formed over the pixel area with a relatively larger area than the metal layer 291a, and functions as an anode electrode (not shown).

In the substrate of the bottom emission type organic light emitting diode display of the present invention, the source electrode s, the drain electrode d, and the anode electrode (not shown) may be formed as one mask to reduce the number of masks. The source electrode s, the drain electrode d, and the anode electrode (not shown) may be formed as a mask to form the source electrode s, the drain electrode d, and the anode electrode (not shown). By eliminating the process of forming the protective layer existing between the layers, and forming only the interlayer insulating film 250, one mask is further reduced to provide a bottom emission type in comparison with the conventional bottom emission type organic light emitting display device. The eight masks required to make the substrate of the organic light emitting diode display can be reduced to six masks.

Hereinafter, a bottom emission organic light emitting device according to the present invention is as follows.

9 is a cross-sectional view of a bottom emission organic light emitting device substrate according to the present invention.

Referring to FIG. 9, the bottom emission type organic light emitting display device is The semiconductor layer 210 including the substrate 200, the buffer layer 205 formed on the substrate 200, the source, the drain regions 210a and 210c and the channel region 210b formed on the buffer layer 205, and A gate insulating layer 220 formed on the entire surface of the substrate including the semiconductor layer 210, corresponding to the channel region 210b, and including a gate electrode 230 and the gate electrode 230 formed on the gate insulating layer 220. An interlayer insulating layer 250 covering the gate insulating layer 220, a first contact hole 240H for exposing source and drain regions 210a and 210c of the semiconductor layer 210 in the interlayer insulating layer 250, and The first electrode 290b, the metal layer 291c, and the second electrode 292c are connected to the source and drain regions 210a and 210c of the semiconductor layer 210 through the first contact hole 240H. The source / drain integrated pattern 260c, the semiconductor layer 210, the gate electrode 230, the source electrode s, and the drain An opening for exposing a portion of the anode electrode (not shown) and a portion of the anode electrode (not shown) formed integrally with the first electrode 290b and the interlayer insulating film 250 integrally with the electrode (d). And a bank and a spacer 295 formed thereon.

In addition, the bottom emission type organic light emitting display device includes an organic light emitting layer (not shown) and a cathode electrode (not shown), and the anode electrode (not shown), the organic light emitting layer (not shown), and a cathode electrode (not shown) It may include a sealing agent (not shown) and a glass cap (not shown) for encapsulating the organic light emitting display device consisting of.

The substrate 200 may be an insulating glass, a plastic, or a conductive substrate. In addition, the substrate 200 may have a top gate structure in which the gate electrode 230 is positioned on the semiconductor layer 210, and a bottom (the gate electrode 230 is positioned below the semiconductor layer 210). bottom) may be a gate structure.

In addition, the thin film transistor including the semiconductor layer 210, the gate electrode 230, the source electrode s, and the drain electrode d may include: Oxide TFT, which is a thin film transistor using an oxide such as IGZO (Indium Galium Zinc Oxide), ZnO (Zinc Oxide), TiO (Titanum Oxide), etc. in the active layer channel, Organic thin film transistor (Organic TFT) using organic material in active layer channel, Amorphous Silicon TFT (Amorphous Silicon TFT) fabricating thin film transistor substrate using amorphous silicon in active layer channel and Thin film transistor substrate using polycrystalline silicon in active layer channel The polysilicon TFT is selected from polysilicon thin film transistors.

The first electrode 290b and the second electrode 292b of the source electrode s and the drain electrode d are made of indium tin oxide (ITO) having high resistance. However, since the source electrode s and the drain electrode d have a low resistance to process a signal quickly due to a high speed of current, in order to lower the high resistance of the source electrode s and the drain electrode d, A metal layer 291b is formed between the first electrode 290b and the second electrode 292b. The metal layer 291b is a metal selected from aluminum (Al), aluminum alloy, silver (Ag), silver alloy, molybdenum (Mo), titanium (Ti), and copper (Cu), and the first electrode 290b and the In order to protect the metal layer 291b, the second electrode 292b made of ITO is once again formed on the metal layer 291b.

Most preferably, the multilayer pattern 260b has a structure of ITO, silver alloy, or ITO, and the thickness of the first electrode 290b and the second electrode 292b is between 100 kV and 1500 kV, most preferably, It is preferable that the thickness of the first electrode 290a is 100 ± 30 mm and the thickness of the second electrode 292b is 500 ± 200 mm.

In addition, the anode electrode is formed integrally with the first electrode 290a.

In addition, the bank and the spacer 295 is a polymer material of any one of polyimide, polyacrylic, and polystyrene.

In the above-described bottom emission type organic light emitting display device and a method of manufacturing the same, a substrate of a conventional bottom emission type organic light emitting display device is manufactured using eight masks, whereas a source electrode, a drain electrode, and an anode electrode are formed. The substrate may be manufactured using a total of six masks by removing the process of forming one layer and forming a protective layer between the source electrode, the drain electrode, and the anode electrode.

In particular, by reducing the number of masks, the photo process of the exposure and development required for each mask, the etching process, the etching process, and the like can be omitted, thereby reducing the number of steps by 10, thereby improving the yield. As a result, it is possible to reduce the manufacturing cost of the bottom emission type organic light emitting display device, simplify the process, reduce the process time, and improve productivity and manufacturing yield.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

200: substrate 205: buffer layer
210a: source region 210b: channel region
210c: drain region 210: semiconductor layer
220: gate insulating film 230: gate electrode
240H: first contact hole 250: interlayer insulating film
290b: first electrode 291c: metal layer
292c: second electrode 260c: source / drain integrated pattern 260c
295: bank and spacer s: source electrode
d: drain electrode

Claims (13)

Forming a semiconductor layer on the substrate;
Forming a gate insulating film on an entire surface of the substrate including the semiconductor layer;
Forming a gate electrode on the gate insulating layer so as to correspond to the semiconductor layer;
Forming an interlayer insulating film on the gate insulating film including the gate electrode;
Selectively removing the insulating interlayer to form contact holes exposing both sides of the semiconductor layer;
Stacking a first electrode, a metal layer, and a second electrode on the interlayer insulating layer in order to form a source electrode and a drain electrode connected to both sides of the semiconductor layer through the contact hole;
Selectively removing the second electrode and the metal layer to expose the first electrode to form an anode electrode; And
And forming a bank and a spacer so as to have an opening exposing a part of the anode electrode. The method of claim 1,
Forming an organic light emitting layer in the opening;
Forming a cathode on the bank, the spacer, and the organic light emitting layer; And
And encapsulating the glass cap on the substrate by interposing a sealing agent on an outer surface of the substrate. The method of claim 1,
The forming of the source electrode and the drain electrode and the forming of the anode electrode include using a halftone mask. The method of claim 3, wherein
The halftone mask is divided into a light blocking region, a transmission region, and a halftone region,
The halftone region corresponds to the anode electrode forming portion,
And wherein the light blocking area is aligned to correspond to the source electrode and the drain electrode. Forming a semiconductor layer on the substrate;
Forming a gate insulating film on an entire surface of the substrate including the semiconductor layer;
Forming a gate electrode on the gate insulating layer so as to correspond to the semiconductor layer;
Forming an interlayer insulating film on the gate insulating film including the gate electrode;
Selectively removing the insulating interlayer to form contact holes exposing both sides of the semiconductor layer;
Sequentially stacking a first electrode and a metal layer on the interlayer insulating layer to form a source electrode and a drain electrode connected to both sides of the semiconductor layer through the contact hole;
Selectively removing the metal layer to expose the first electrode to form an anode electrode; And
And forming a bank and a spacer so as to have an opening exposing a part of the anode electrode. The method of claim 5, wherein
Forming the source electrode and the drain electrode and forming the anode electrode, using a halftone mask,
The halftone region of the halftone mask corresponds to the anode electrode formation region,
And wherein the light blocking area is aligned to correspond to the source electrode and the drain electrode. Board;
A buffer layer formed on the substrate;
A semiconductor layer including a source, a drain region, and a channel region formed on the buffer layer;
A gate insulating film formed on an entire surface of the substrate including the semiconductor layer;
A gate electrode corresponding to the channel region and formed on the gate insulating layer;
An interlayer insulating film covering the gate insulating film including the gate electrode;
A contact hole for exposing a source and a drain region of the semiconductor layer in the interlayer insulating film;
A source electrode and a drain electrode connected to the source and drain regions of the semiconductor layer through the contact hole, wherein a first electrode, a metal layer, and a second electrode are stacked;
An anode formed on said interlayer insulating film integrally with said first electrode; And
And a bank and a spacer formed with an opening for exposing a portion of the anode electrode. The method of claim 7, wherein
The thin film transistor including the semiconductor layer, the gate electrode, the source electrode, and the drain electrode includes an oxide thin film transistor (Oxide TFT), an organic thin film transistor (Organic TFT), an amorphous silicon thin film transistor (Amorphous Silicon TFT), and a polysilicon thin film transistor ( Poly Silicon TFT) is a bottom emission type organic light emitting display device. The method of claim 7, wherein
The first electrode and the second electrode are any one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO), respectively. The method of claim 7, wherein
And the metal layer is a metal selected from among aluminum (Al), aluminum alloy, silver (Ag), silver alloy, molybdenum (Mo), titanium (Ti), and copper (Cu). The method of claim 7, wherein
And wherein the first electrode is ITO, the metal layer is a silver alloy, and the second electrode is ITO. The method of claim 7, wherein
And a thickness of the first electrode and the second electrode is 100 kW to 1500 kW. The method of claim 7, wherein
The bank and the spacer are at least one polymer material of polyimide, polyacryl, and polystyrene.

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