KR20110115780A - Pcb, package on package substrate and the manufacturing method thereof - Google Patents

Pcb, package on package substrate and the manufacturing method thereof Download PDF

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Publication number
KR20110115780A
KR20110115780A KR1020100035297A KR20100035297A KR20110115780A KR 20110115780 A KR20110115780 A KR 20110115780A KR 1020100035297 A KR1020100035297 A KR 1020100035297A KR 20100035297 A KR20100035297 A KR 20100035297A KR 20110115780 A KR20110115780 A KR 20110115780A
Authority
KR
South Korea
Prior art keywords
bump
substrate
package
insulating layer
dam
Prior art date
Application number
KR1020100035297A
Other languages
Korean (ko)
Inventor
장용순
최원
Original Assignee
삼성전기주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
Priority to KR1020100035297A priority Critical patent/KR20110115780A/en
Publication of KR20110115780A publication Critical patent/KR20110115780A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Disclosed are a printed circuit board, a package on package substrate, and a method for manufacturing a package on package substrate. Bum pad is formed on the substrate, the insulating layer is formed on the substrate to expose the bump pad, the insulating layer is formed in the insulating layer, and the dam surrounding the window to form a charging space to be formed inside, the charging space is filled in the bump pad A printed circuit board including a supported bump base may mount solder bumps to a desired height even on a substrate on which fine pitches are formed.

Description

Printed Circuit Board, Package on Package Substrate and Package on Package Substrate

The present invention relates to a printed circuit board, a package on package substrate and a method for manufacturing a package on package substrate.

With the development of the electronic industry, the demand for high functionalization and miniaturization of electronic components is increasing rapidly. In order to cope with such a demand, a stack package substrate, in which a plurality of electronic devices are stacked and mounted on a single substrate, has appeared.

In the evolution of package board design, SiP (System in Package) was created in response to the demand for high speed and high integration.SiP has been developed in various forms such as Package in Package (PIP) and Package on Package (PoP). I'm going.

In particular, R & D on a method for realizing a high performance and high density package substrate required in the market, and as the demand for it increases, a package on package that stacks the package substrate on the package substrate among various methods of forming the package substrate on Package, hereinafter referred to as POP) has emerged as an alternative.

On the other hand, the number of I / O connection terminals has increased due to the increase in the number of mounted ICs, and accordingly, fine pitch demands have also increased.

Accordingly, in order to cope with the fine pitch while maintaining a constant gap between the upper substrate and the lower substrate required for mounting the parts in the POP, the size of the solder ball to be bonded to the lower surface of the upper substrate should be kept the same as the existing size, which is fine There is a problem that the result is that the pitch does not correspond.

That is, the conventional POP technology has a limitation in realizing a fine pitch while securing a gap between substrates.

The present invention provides a printed circuit board, a package-on-package substrate, and a package-on-package substrate manufacturing method for realizing a fine pitch while securing a gap between the substrates.

According to an aspect of the present invention, a substrate having bump pads formed thereon, an insulating layer stacked on the substrate, and having a window exposing the bump pads formed therein, the insulating layer being formed on the inside of the window to form a charging space therein. There is provided a printed circuit board including a bump surrounding the dam, the charging space being filled in the charging pad, and supported by the bump pad.

At least one of the insulating layer and the dam may include a solder resist.

It may further include a solder bump laminated on the bump base.

The bump base may include a conductive material.

In addition, according to another aspect of the invention, the lower substrate having a bump pad formed on the upper surface, an insulating layer laminated on the upper surface of the lower substrate, the window formed to expose the bump pad, formed on the insulating layer, the inner side A dam surrounding the window, a charge base filled with the bump space, a bump base supported by the bump pad, a solder bump stacked on the bump base, and a lower surface of the lower substrate, A package on package substrate including an upper substrate to which the solder bumps are coupled is provided.

At least one of the insulating layer and the dam may include a solder resist.

The bump base may include a conductive material.

Further, according to another aspect of the invention, the step of providing a lower substrate with a bump pad formed on the upper surface, laminating an insulating layer having a window for exposing the bump pad on the upper surface of the lower substrate, the insulating layer Forming a dam surrounding the window so as to form a filling space therein, filling the filling space to form a bump base supported on the bump pad, laminating solder bumps on the bump base, Provided is a method for manufacturing a package-on-package substrate comprising stacking an upper substrate on the lower substrate such that a lower surface thereof is coupled to the solder bumps.

The dam forming step may include applying a solder resist to the insulating layer corresponding to the window, and selectively removing the solder resist such that a dam surrounding the window is formed.

The bump base forming step may include filling a conductive material in the filling space.

According to the present invention, solder bumps may be mounted at a desired height even on a substrate on which fine pitch is formed.

In addition, by adjusting the mounting height of the solder bump, it is possible to secure the gap between the substrate required for the component mounting in the package-on-package structure.

1 is a cross-sectional view showing a package on package substrate according to an embodiment of the present invention.
2 is a flowchart illustrating a method of manufacturing a package on package substrate according to another embodiment of the present invention.
3 to 6 illustrate a method of manufacturing a package on package substrate according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a package on package substrate according to an exemplary embodiment of the present invention.

The package on package substrate according to an exemplary embodiment of the present invention includes a printed circuit board having a lower substrate 10, a solder bump 50, and an upper substrate 60. The printed circuit board may include a lower substrate 10, an insulating layer 20, a dam 30, and a bump base 40 to secure a desired distance from the upper substrate 60.

The lower substrate 10 is a portion in which the bump base 40 and the bump pad 12 on which the solder bumps 50 are to be supported are formed. The circuit board (not shown) necessary for the package is formed on the lower substrate 10. Can be. In this embodiment, the bump pad 12 for coupling the upper substrate 60 is formed on the upper surface of the lower substrate 10.

In addition, an electrode pad 14 may be formed on the lower substrate 10 to be connected to the chip 18 to be mounted. The electrode pad 14 may be electrically connected to the chip 18 mounted through the solder ball 15 or the like.

The insulating layer 20 covers the circuit pattern of the lower substrate 10 while exposing the bump pads 12. To this end, the insulating layer 20 of the present embodiment is stacked on the upper surface of the lower substrate 10, and a window 22 (see FIG. 3) exposing the bump pad 12, that is, a through hole is formed.

Specifically, the insulating layer 20 of the present embodiment may be formed by selectively removing the solder resist applied to the bump pad 12 after the solder resist is applied to the lower substrate 10.

The dam 30 is a portion that forms a space filled with the bump base 40 to be described later. The dam 30 is formed in the insulating layer 20 in a form surrounding the window 22 (see FIG. 3) to form the charging space 32 therein. Is formed. As a result, the charging space 32 (see FIG. 4) is opened while being connected to the bump pad 12. In addition, the bump base 40 formed inside the dam 30 may be supported on its side by the dam 30.

At this time, the dam 30 can be formed by laminating a solder resist around the window 22.

The bump base 40 is a portion on which the solder bumps 50 are supported, and is formed by being filled in the filling space 32 (see FIG. 4) of the dam 30 and supported by the bump pads 12. In particular, the bump base 40 serves to adjust the height at which the solder bumps 50 are supported, thereby securing a gap between the upper substrate 60 and the lower substrate 10 to be described later coupled by the solder bumps 50. It plays a role.

Due to the fine pitch, a small solder bump cannot be supported on the bump pad 12 formed small, and it is difficult to secure the gap between the upper substrate 60 and the lower substrate 10 using only the solder bumps 50. In this embodiment, the bump base 40 may be further stacked on the bump pad 12 to compensate for the reduction in the gap due to the smaller solder bumps 50. Accordingly, the gap G between the chip 18 and the upper substrate 60 may be secured so that the chip 18 may be mounted on the lower substrate 10.

At this time, the bump base 40 is made of a conductive material such as solder or metal, thereby electrically connecting the bump pad 12 and the solder bumps 50.

The solder bump 50 is a portion that couples the upper substrate 60 to the printed circuit board including the lower substrate 10. As described above, the solder bumps 50 of the present embodiment may be adjusted by being stacked on the bump base 40.

The upper substrate 60 is a portion laminated and bonded on the printed circuit board including the lower substrate 10. The upper substrate 60 of the present embodiment is stacked on the upper surface of the lower substrate 10, the lower surface of the upper substrate 60 is solder bump 50 is coupled. In this case, the upper substrate 60 and the lower substrate 10 may be electrically connected through the conductive solder bumps 50.

In the above, the package-on-package substrate that can secure the gap between the substrates required for mounting the chip 18 by adjusting the mounting height of the solder bumps 50 has been described. Hereinafter, a method of manufacturing a package on package substrate will be described.

2 is a flowchart illustrating a method of manufacturing a package on package substrate according to another embodiment of the present invention, and FIGS. 3 to 6 are views illustrating a method of manufacturing a package on package substrate according to another embodiment of the present invention.

Method for manufacturing a package on package substrate according to an embodiment of the present invention, the lower substrate providing step (S110), insulating layer stacking step (S120), dam forming step (S130), bump base forming step (S140), solder bump The lamination step S150 and the upper substrate laminating step S160 are included.

In the lower substrate providing step S110, the lower substrate 10 having the bump base 40 and the bump pad 12 on which the solder bumps 50 are to be supported will be provided. As shown in FIG. 3, bump pads 12 for coupling the upper substrate 60 are formed on the upper surface of the lower substrate 10 in the present embodiment.

In addition, the lower substrate 10 may be formed with an electrode pad 14 for connection with the chip to be mounted. The electrode pad 14 may be electrically connected to the chip mounted through the solder ball 15 or the like.

In the insulating layer stacking step (S120), the insulating layer 20 having the window 22 exposing the bump pads 12 is formed on the upper surface of the lower substrate 10. The insulating layer 20 covers the circuit pattern of the lower substrate 10 and exposes the bump pad 12. As shown in FIG. 3, in this embodiment, the insulating layer 20 is stacked on the upper surface of the lower substrate 10, and the window 22, that is, the through-holes exposing the bump pad 12 to the insulating layer 20. To form.

Specifically, after the solder resist is applied to the lower substrate 10, the solder resist applied corresponding to the bump pad 12 may be selectively removed.

In the dam forming step (S130), a dam 30 is formed to surround the window 22 of the insulating layer 20. The dam 30 is a portion forming a space in which the bump base 40 to be described later will be filled. As shown in FIG. 4, the dam 30 has a shape surrounding the window 22 so that the filling space 32 is formed therein. ). As a result, the charging space 32 that is connected to the bump pad 12 and opened upward is formed. In addition, the bump base 40 formed inside the dam 30 may be supported on its side by the dam 30.

Specifically, the dam 30 may be formed using the solder resist in the present embodiment. After applying the solder resist to the window 22 and its periphery corresponding to the window 22, the solder resist may be selectively removed to form the dam 30 so that the dam 30 surrounding the window 22 is formed. Can be.

In the bump base forming step (S140), the filling space 32 is filled to form the bump base 40 supported by the bump pad 12. As shown in FIG. 5, the bump base 40 is a portion in which the solder bumps 50 are supported, and is formed by being filled in the filling space 32 of the dam 30 and supported by the bump pads 12. In particular, the bump base 40 serves to adjust the height at which the solder bumps 50 are supported, thereby securing a gap between the upper substrate 60 and the lower substrate 10 to be described later coupled by the solder bumps 50. It plays a role.

Due to the fine pitch, the small bump bumps 12 may not be supported by the small bump pads 12. Therefore, it is difficult to secure the gap between the upper substrate 60 and the lower substrate 10 using only the solder bumps 50. In this embodiment, the bump base 40 may be further stacked on the bump pad 12 to compensate for the reduction in the gap due to the smaller solder bumps 50. Accordingly, the gap between the chip and the upper substrate 60 may be secured so that the chip may be mounted on the lower substrate 10.

At this time, the filling space 32 is filled with a conductive material such as solder or metal to form the bump base 40, so that the bump base 40 electrically connects the bump pad 12 and the solder bump 50. Can be.

In the solder bump stacking step (S150), the solder bumps 50 are stacked on the bump base 40. The solder bump 50 is a portion that couples the upper substrate 60 to the printed circuit board including the lower substrate 10. As described above, the solder bumps 50 of the present embodiment may be adjusted by being stacked on the bump base 40.

In the upper substrate stacking step (S160), the upper substrate 60 is laminated on the lower substrate 10 such that the upper substrate 60 is coupled to the solder bumps 50. The upper substrate 60 is a portion laminated and bonded on the printed circuit board including the lower substrate 10.

As shown in Figure 6, the upper substrate 60 of the present embodiment is laminated on the upper surface of the lower substrate 10, the lower surface of the upper substrate 60 is solder bump 50 is coupled. In this case, the upper substrate 60 and the lower substrate 10 may be electrically connected through the conductive solder bumps 50.

Although the above has been described with reference to embodiments of the present invention, those skilled in the art may variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. And can be changed.

Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

10: lower substrate
12: bump pad
20: insulation layer
30: dam
40: bump base
50: solder bump
60: upper substrate

Claims (10)

A substrate on which bump pads are formed;
An insulating layer stacked on the substrate and having a window exposing the bump pads;
A dam formed in the insulating layer and surrounding the window to form a charging space therein; And
And a bump base filled in the charging space and supported by the bump pad.
The method of claim 1,
At least one of the insulating layer and the dam is a printed circuit board comprising a solder resist.
The method of claim 1,
The printed circuit board further comprises a solder bump laminated on the bump base.
The method of claim 1,
The bump base is a printed circuit board comprising a conductive material.
A lower substrate having bump pads formed on an upper surface thereof;
An insulating layer stacked on an upper surface of the lower substrate and having a window exposing the bump pads;
A dam formed in the insulating layer and surrounding the window to form a charging space therein;
A bump base filled in the charging space and supported by the bump pad;
A solder bump stacked on the bump base; And
The package on package substrate stacked on an upper surface of the lower substrate, the lower surface comprises an upper substrate coupled to the solder bumps.
The method of claim 5,
At least one of the insulating layer and the dam comprises a solder resist package on package substrate.
The method of claim 5,
And the bump base comprises a conductive material.
Providing a lower substrate having bump pads formed on an upper surface thereof;
Stacking an insulating layer having a window exposing the bump pads on an upper surface of the lower substrate;
Forming a dam in the insulating layer, the dam surrounding the window to form a charging space therein;
Filling the filling space to form a bump base supported by the bump pad;
Stacking solder bumps on the bump bases; And
And stacking an upper substrate on the lower substrate such that a lower surface thereof is coupled to the solder bumps.
The method of claim 8,
The dam forming step,
Applying solder resist to the insulating layer corresponding to the window; And
And selectively removing the solder resist such that a dam surrounding the window is formed.
The method of claim 8,
The bump base forming step,
And filling a conductive material in the filling space.
KR1020100035297A 2010-04-16 2010-04-16 Pcb, package on package substrate and the manufacturing method thereof KR20110115780A (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100035297A KR20110115780A (en) 2010-04-16 2010-04-16 Pcb, package on package substrate and the manufacturing method thereof

Publications (1)

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KR20110115780A true KR20110115780A (en) 2011-10-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11742294B2 (en) 2020-09-22 2023-08-29 Samsung Electronics Co., Ltd. Interposers and semiconductor packages including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11742294B2 (en) 2020-09-22 2023-08-29 Samsung Electronics Co., Ltd. Interposers and semiconductor packages including the same

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