KR20110097493A - Method for forming the fine pattern of semiconductor devices - Google Patents

Method for forming the fine pattern of semiconductor devices Download PDF

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KR20110097493A
KR20110097493A KR1020100017355A KR20100017355A KR20110097493A KR 20110097493 A KR20110097493 A KR 20110097493A KR 1020100017355 A KR1020100017355 A KR 1020100017355A KR 20100017355 A KR20100017355 A KR 20100017355A KR 20110097493 A KR20110097493 A KR 20110097493A
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pattern
etching
forming
protective film
etched
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오창일
복철규
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
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Abstract

본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로,
피식각층이 형성된 반도체기판 상부에 감광막을 도포하고 상기 감광막 표면에 라인형태의 홈을 형성하여 라인/스페이스 패턴을 형성한 다음, 상기 스페이스 패턴을 매립하는 내에칭 보호막 패턴을 형성하고 상기 내에칭 보호막 패턴을 마스크로 하여 상기 감광막을 식각하여 내에칭 보호막 패턴 및 감광막패턴의 적층구조를 형성한 다음, 상기 적층구조를 마스크로 하여 피식각층을 식각함으로써 미세패턴을 형성하여 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a fine pattern of a semiconductor device,
Applying a photoresist film on top of the semiconductor substrate on which the etched layer is formed, forming a line-shaped groove on the surface of the photoresist film to form a line / space pattern, then forms an etch-resistant protective film pattern to fill the space pattern and the etching-resistant protective film pattern The photoresist is etched using a mask as a mask to form a laminated structure of an etching resistant protective film pattern and a photoresist pattern, and then a fine pattern is formed by etching the etched layer using the laminated structure as a mask to enable high integration of semiconductor devices. to be.

Description

반도체소자의 미세패턴 형성방법{METHOD FOR FORMING THE FINE PATTERN OF SEMICONDUCTOR DEVICES}METHOD FOR FORMING THE FINE PATTERN OF SEMICONDUCTOR DEVICES

본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로서, 특히 포토레지스트의 상부에 스페이스 패턴 형성만으로 피식각층의 패터닝이 가능하도록 하여 반도체소자의 고집적화에 따른 미세패턴이 쓰러지는 현상을 방지하는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a micropattern of a semiconductor device, and more particularly, to a method of preventing a pattern falling down due to high integration of a semiconductor device by enabling patterning of an etched layer only by forming a space pattern on the photoresist. .

반도체 소자를 형성하는데 있어서 가장 중요한 요소로는 증착(deposition) 공정과 식각(etch) 공정을 들 수 있으며, 이 중에서도, 반도체 소자의 집적도가 증가함에 따라 식각 공정의 중요도가 더욱 증가하고 있다. The most important elements in forming a semiconductor device include a deposition process and an etch process, and among these, as the degree of integration of semiconductor devices increases, the importance of the etching process increases.

특히, 식각 공정 중에서 패터닝(pattering) 공정은 반도체 소자의 집적도 증가에 직접적인 영향을 주는 공정이라 할 수 있으며, 패터닝 공정에 따라 반도체 제조 공정의 수율 및 반도체 소자의 신뢰도가 달라질 수도 있다. 이에 대하여, 예를 들어 설명하면 다음과 같다. In particular, the patterning process in the etching process may be a process directly affecting the increase in the integration degree of the semiconductor device, and the yield and reliability of the semiconductor device may vary depending on the patterning process. This will be described below with an example.

반도체 소자에 포함되는 다수의 금속배선들의 형성 공정을 예를 들어 설명하면, 반도체 기판 상에 금속배선들 간을 전기적으로 격리시키기 위한 절연막을 형성한다. 절연막을 패터닝(patterning)하기 위해서는, 절연막의 상부에 하드 마스크 패턴을 형성하는데, 하드 마스크 패턴은 포토레지스트 패턴에 따라 식각 공정을 실시하여 형성할 수 있다. 특히, 포토레지스트 패턴은 노광 및 현상 공정을 실시하여 형성하는데, 이때 실시하는 노광 공정에 의해 패턴의 폭이 주로 결정된다.For example, a process of forming a plurality of metal wires included in a semiconductor device will be described. An insulating film for electrically isolating metal wires is formed on a semiconductor substrate. In order to pattern the insulating film, a hard mask pattern is formed on the insulating film, and the hard mask pattern may be formed by performing an etching process according to the photoresist pattern. In particular, the photoresist pattern is formed by performing an exposure and development process, and the width of the pattern is mainly determined by the exposure process performed at this time.

노광 공정의 해상도(resolution; R)는 패턴의 폭을 결정하는 주요 요소가 될 수 있는데, 해상도(R)는 다음의 수학식 1과 같이 나타낼 수 있다.The resolution R of the exposure process may be a major factor in determining the width of the pattern, and the resolution R may be expressed by Equation 1 below.

Figure pat00001
Figure pat00001

수학식 1을 참조하면, 'R'은 해상도(resolution)이며, 'Ki'는 공정능력 변수(coherence <6> factor)로써 일반적으로 0.5 내지 0.8의 값을 가진다. 'λ'는 노광 공정에 사용되는 광원의 파장(wavelength)이며, 'NA'는 노광 장비의 렌즈 개구수(numerical aperture)를 나타낸다.Referring to Equation 1, 'R' is the resolution, and 'Ki' is a coherence factor, and generally has a value of 0.5 to 0.8. 'λ' is the wavelength of the light source used in the exposure process, and 'NA' represents the lens numerical aperture of the exposure equipment.

이 중에서, 공정능력 변수(Ki)는 제조 공정상 임의로 조절하기가 매우 어렵기 때문에 광원의 파장(λ)을 낮추거나 렌즈 개구수(NA)를 증가시켜 해상도를 조절하는 것이 바람직하다.Among these, since the process capability variable Ki is very difficult to be arbitrarily adjusted in the manufacturing process, it is preferable to adjust the resolution by lowering the wavelength? Of the light source or increasing the lens numerical aperture NA.

한편, 상술한 바와 같이 광원 또는 렌즈 개구수를 바꾸기 위해서는 노광 장비의 교체가 이루어져야 하지만, 이는 고가의 설비 및 제조 비용을 필요로 한다.On the other hand, in order to change the light source or lens numerical aperture as described above, the replacement of the exposure equipment must be made, but this requires expensive equipment and manufacturing cost.

하여, 최근에는 하드마스크 및 유기 반사방지막을 이용하여 반도체소자의 미세패턴을 형성하였다. In recent years, fine patterns of semiconductor devices have been formed using hard masks and organic antireflection films.

도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도이다. 1A to 1C are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art.

도 1a 을 참조하면, 반도체기판(미도시) 상부에 피식각층(10)을 형성하고 그 상부에 제1 하드마스크층(12), 제2 하드마스크층(14), 반사방지막(16) 및 감광막패턴(18)을 형성한다. 여기서, 제1 및 제2 하드마스크층(12,14)은 질화막, 산화막 또는 질화산화막으로 형성한 것이다. Referring to FIG. 1A, an etched layer 10 is formed on a semiconductor substrate (not shown), and a first hard mask layer 12, a second hard mask layer 14, an anti-reflection film 16, and a photoresist film are formed on the etched layer 10. The pattern 18 is formed. Here, the first and second hard mask layers 12 and 14 are formed of a nitride film, an oxide film, or a nitride oxide film.

이때, 감광막패턴(18)은 반사방지막(16) 상부에 감광막을 도포하고, 미세패턴을 형성하기 위한 노광마스크를 이용한 노광 및 현상 공정으로 형성한 것이다. At this time, the photoresist pattern 18 is formed by an exposure and development process using an exposure mask for coating a photoresist on the anti-reflection film 16 and forming a fine pattern.

그리고, 반사방지막(16)은 유기막으로 형성한 것이다. The antireflection film 16 is formed of an organic film.

도 1b 를 참조하면, 감광막패턴(18)을 마스크로 하여 반사방지막(16)을 식각하여 제2 하드마스크층(16)을 노출시킨다.Referring to FIG. 1B, the anti-reflection film 16 is etched using the photoresist pattern 18 as a mask to expose the second hard mask layer 16.

연속적으로, 남아있는 감광막패턴(18)과 반사방지막(16)을 마스크로 하여 제2 하드마스크층(16)을 식각함으로써 제2 하드마스크층(16)패턴을 형성한다. Subsequently, the second hard mask layer 16 pattern is formed by etching the second hard mask layer 16 using the remaining photoresist pattern 18 and the antireflection film 16 as a mask.

이때, 식각물질의 상부에 존재하는 물질이 마스크로 작용하여 하부층의 식각시 동시에 식각되고, 과도식각공정을 수반하여 피식각 물질, 도 1b 의 제2 하드마스크층(14) 패턴 상부에는 반사방지막(16) 및 감광막패턴(18)이 남지 않는다. 물론, 식각공정은 각 층간의 식각선택비 차이를 이용하여 습식 또는 건식 방법으로 실시한다. At this time, the material existing on the upper portion of the etching material acts as a mask and is simultaneously etched during the etching of the lower layer, and the anti-etching film (on the second hard mask layer 14 pattern of FIG. 16) and the photosensitive film pattern 18 remain. Of course, the etching process is performed by a wet or dry method using the difference in the etching selectivity between the layers.

도 1c 를 참조하면, 제2 하드마스크층(16) 패턴을 마스크로 하여 노출된 제1 하드마스크층(14)을 식각하여 피식각층(10)을 노출시킨다. Referring to FIG. 1C, the exposed first hard mask layer 14 is etched using the second hard mask layer 16 pattern as a mask to expose the etched layer 10.

이때, 제2 하드마스크층(16)은 완전히 제거된 상태이다. 여기서, 제2 하드마스크층(16)은 제1 하드마스크층(14)과의 식각선택비 차이를 이용하여 제거한 것이다. At this time, the second hard mask layer 16 is completely removed. In this case, the second hard mask layer 16 is removed by using an etching selectivity difference from the first hard mask layer 14.

도시되지 않았으나, 후속 공정으로 제1 하드마스크층(12)을 마스크로 하여 피식각층(10)을 식각함으로써 미세패턴을 형성한다. Although not shown, a fine pattern is formed by etching the etched layer 10 using the first hard mask layer 12 as a mask in a subsequent process.

상기한 바와 같이 종래기술에 따른 반도체소자의 미세패턴 형성방법은 다음과 같은 문제점이 있다. As described above, the method for forming a fine pattern of a semiconductor device according to the prior art has the following problems.

1. 하드마스크층을 형성하기 위하여 하드마스층의 층수만큼 CVD 형성 공정을 수반하여야 함.1. In order to form the hard mask layer, the number of layers of the hard mask layer must be accompanied by the CVD forming process.

2. 미세패턴의 해상도를 증가시키기 위하여 반사방지막을 사용.2. Use anti-reflection film to increase the resolution of fine pattern.

3. 상기한 구조물 사용에 따른 비용 증가3. Increased cost of using the above structure

4. 감광막을 한계 선폭으로 패터닝하기 위하여 리소그래피 공정의 현상 공정지 감광막패턴의 쓰러짐 현상이 유발.4. Developing process of lithography to pattern the photoresist to the limit line width.

5. 1-4 의 공정에 따른 파티클 유발 등으로인한 오염도 증가.5. Contamination increases due to particle generation following 1-4 process.

본 발명은 공정을 단순화시켜 반도체소자의 고집적화에 충분한 미세패턴을 형성할 수 있도록 하는 반도체소자의 미세패턴 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a micropattern of a semiconductor device which simplifies the process so that a micropattern sufficient for high integration of the semiconductor device can be formed.

본 발명에 따른 반도체소자의 미세패턴 형성방법은, Method for forming a fine pattern of a semiconductor device according to the present invention,

피식각층이 형성된 반도체기판 상부에 감광막을 도포하는 공정과,Applying a photoresist film on the semiconductor substrate on which the etched layer is formed;

상기 감광막 표면에 라인형태의 홈을 형성하여 라인/스페이스 패턴을 형성하는 공정과,Forming a line / space pattern by forming a groove in a line shape on the surface of the photosensitive film;

상기 스페이스 패턴을 매립하는 내에칭 보호막 패턴을 형성하는 공정과,Forming a etching-resistant protective film pattern filling the space pattern;

상기 내에칭 보호막 패턴을 마스크로 하여 상기 감광막을 식각하여 내에칭 보호막 패턴 및 감광막패턴의 적층구조를 형성하는 공정과,Etching the photosensitive film using the etched protective film pattern as a mask to form a laminated structure of the etched protective film pattern and the photosensitive film pattern;

상기 적층구조를 마스크로 하여 피식각층을 식각함으로써 미세패턴을 형성하는 공정을 포함하는 것과,Forming a fine pattern by etching the layer to be etched using the laminated structure as a mask;

상기 내에칭 보호막 패턴은 실리콘이 20 퍼센트 이상 함유된 절연막인 것과,The etching-resistant protective film pattern is an insulating film containing more than 20 percent of silicon,

상기 내에칭 보호막 패턴은 실리콘이 10 퍼센트 이상 함유된 절연막인 것과,The etching resistance protective film pattern is an insulating film containing at least 10 percent of silicon,

상기 내에칭 보호막 패턴은 BPSG, PSG, USG, SOG 및 이들의 조합으로 이루어지 적층구조 중에서 선택된 임의의 한가지로 형성하는 것과,The etching-resistant protective film pattern is formed of any one selected from a laminated structure consisting of BPSG, PSG, USG, SOG, and a combination thereof,

상기 내에칭 보호막 패턴은 상기 스페이스 패턴을 매립하는 내에칭 보호막을 전체표면상부에 형성하는 공정과, 상기 내에칭 보호막을 평탄화 식각하는 공정을 포함하는 공정으로 형성한 것과,The etching-resistant protective film pattern is formed by forming a etching-resistant protective film filling the space pattern on the entire surface, and forming a process including flattening etching the etching-resistant protective film;

상기 평탄화 식각공정은 에치백 공정이나 CMP 공정으로 실시하는 것과,The planarization etching process is performed by an etch back process or a CMP process,

상기 에치백 공정은 CxFy 계 가스를 주식각 가스로 사용하고 산소가스를 첨가가스로 사용하여 실시하는 것과,The etch back process is performed using CxFy-based gas as the stock angle gas and oxygen gas as the additive gas,

상기 감광막 식각공정은 질소 및 산소 ( N2/O2 ) 가스를 베이스로 하는 플라즈마를 이용하여 실시하는 것을 특징으로 한다.The photoresist etching process may be performed using a plasma based on nitrogen and oxygen (N 2 / O 2) gases.

본 발명에 따른 반도체소자의 미세패턴 형성방법은, 종래기술에 사용되는 하드마스크층 및 반사방지막의 형성, 식각 및 제거 공정을 생략할 수 있으므로, 그에 따른 반도체소자의 오염을 방지하고 비용을 절감할 수 있도록 하는 효과를 제공한다. In the method of forming a micropattern of a semiconductor device according to the present invention, the process of forming, etching and removing the hard mask layer and the anti-reflection film used in the prior art can be omitted, thereby preventing contamination of the semiconductor device and reducing costs. It provides the effect of making it possible.

도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art.
2A to 2D are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

이하, 첨부한 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하고자 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도이다. 2A to 2D are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

도 2a 를 참조하면, 반도체기판(미도시) 상부에 피식각층(30)을 형성한다. Referring to FIG. 2A, an etched layer 30 is formed on a semiconductor substrate (not shown).

그 다음, 피식각층(30) 상에 감광막(32)을 형성한다. 이때, 감광막(32)은 후속 공정인 피식각층(30) 식각시 식각 베리어로 작용하는 것으로서, 일반적으로 상용화된 포지티브형 혹은 네가티브형 제품을 모두 선택적으로 사용하는것이 가능하다. 여기서, 감광막(32)의 도포 두께는 특별히 한정하지 않는다.Next, a photosensitive film 32 is formed on the etched layer 30. In this case, the photoresist layer 32 acts as an etching barrier during the subsequent etching of the layer 30 to be etched, and it is possible to selectively use both commercially available positive type or negative type products. Here, the coating thickness of the photosensitive film 32 is not specifically limited.

그리고, 노광 및 현상 공정을 수행하여 포토레지스트 상부에 라인 형태의 홈 구조로 스페이스 패턴(34)을 형성함으로써 홈과 이웃하는 감광막 표면이 라인/스페이스 패턴 형태를 이룬다. 상기 노광 공정은 I-Line(365nm), KrF(248nm), ArF(193nm), EUV(13.5nm)의 파장을 기본 광원으로 한다. 이때, 본 명세서에 도시된 바와 같이 포토레지스트 스페이스 패턴(21) 하부에는 유기반사방지막이 개재되지 않는다. The photoresist surface adjacent to the grooves forms a line / space pattern by forming a space pattern 34 in a line-shaped groove structure on the photoresist by performing exposure and development processes. The exposure process uses a wavelength of I-Line (365 nm), KrF (248 nm), ArF (193 nm), and EUV (13.5 nm) as a basic light source. In this case, as shown in the present specification, an organic antireflection film is not interposed below the photoresist space pattern 21.

여기서, 감광막(32) 표면에 형성되는 라인/스페이스 패턴의 라인/스페이스 비는 특별히 한정하지 않으며, 스페이스 패턴(34)의 높이는 포토레지스트의 두께 미만으로 한정한다. 이때, 스페이스 패턴(34)은 라인/스페이스가 정의된 노광 마스크를 이용하여 진행하며, 감광막(32)이 패터닝될 때 사용되는 노광 에너지보다 적은 에너지를 사용하여 감광막(32) 표면에 라인형태의 홈이 형성되도록 한다. Here, the line / space ratio of the line / space pattern formed on the surface of the photosensitive film 32 is not particularly limited, and the height of the space pattern 34 is limited to less than the thickness of the photoresist. At this time, the space pattern 34 proceeds using an exposure mask in which lines / spaces are defined, and a line-shaped groove is formed on the surface of the photoresist 32 using less energy than the exposure energy used when the photoresist 32 is patterned. To be formed.

도 2b 를 참조하면, 감광막(32) 표면에 형성된 스페이스 패턴(34)을 매립하는 내에칭 보호막(36)을 전체표면상부에 형성한다. 이때, 내에칭 보호막(36)은 실리콘 함유 박막을 코팅 및 베이크하여 형성한 것이다. Referring to FIG. 2B, an etched protective film 36 for filling the space pattern 34 formed on the surface of the photosensitive film 32 is formed on the entire surface. At this time, the etching-resistant protective film 36 is formed by coating and baking a silicon-containing thin film.

여기서, 내에칭 보호막(36)은 실리콘 함량이 최소 10% 이상인 절연막으로 형성하거나, 바람직하게는 실리콘 함량이 최소 20% 이상인 절연막으로 형성한다. Here, the etching resistance protective film 36 is formed of an insulating film having a silicon content of at least 10% or more, or preferably an insulating film having a silicon content of at least 20% or more.

또한, 내에칭 보호막(36)은 스페이스 패턴(22)의 갭필 ( Gap-Fill ) 이 용이하며 스페이스 패턴(34) 내부에 기포(Void)가 생기지 않도록 하고, 내에칭 보호막(36) 상부에 움푹패임(Dimple) 현상이 유발되지 않도록 평탄화시킬 수 있는 유동성이 우수한 절연물질인 코팅 가능한 물질을 이용하여 형성하여야 한다. 예를들면, 내에칭 보호막(36)은 BPSG, PSG, USG, SOG 및 이들의 조합으로 이루어지 적층구조 중에서 선택된 임의의 한가지로 형성할 수 있다. In addition, the etch-resistant protective film 36 facilitates a gap fill of the space pattern 22, prevents bubbles from forming inside the space pattern 34, and dents the upper portion of the etch-resistant protective film 36. (Dimple) It should be formed by using coatable material which is an insulating material with good fluidity which can be flattened so as not to cause phenomenon. For example, the etch-resistant protective film 36 may be formed of any one selected from a laminated structure consisting of BPSG, PSG, USG, SOG, and a combination thereof.

도2c 를 참조하면, 내에칭 보호막(36)을 에치백 ( etch back ) 또는 화학기계연마 ( CMP, Chemical Mechanical Polishing ) 공정을 실시함으로써 내에칭 보호막(356) 패턴을 형성한다. Referring to FIG. 2C, the etch-resistant protective film 36 is etched back or chemical mechanical polishing (CMP) to form a etch-resistant protective film 356 pattern.

이때, 에치백 또는 CMP 공정은 스페이스 패턴(34)이 제거되지 않도록 감광막(32)이 과도식각되도록 실시하되, CxFy 계 가스를 주식각 가스로 사용하고 산소가스를 첨가가스로 사용하여 수행하는 것이 바람직하다.At this time, the etch back or CMP process is performed so that the photoresist film 32 is excessively etched so that the space pattern 34 is not removed, but using CxFy-based gas as the stock angle gas and oxygen gas as the additive gas. Do.

도 2d 를 참조하면, 내에칭 보호막(36) 패턴을 식각 베리어로 감광막(32)을 식각하여 내에칭 보호막(36) 패턴과 감광막(32) 패턴의 적층구조를 형성한다. Referring to FIG. 2D, the photoresist layer 32 is etched using the etching resist protective layer 36 pattern as an etch barrier to form a stacked structure of the etching resist protective layer 36 pattern and the photoresist layer 32 pattern.

여기서, 감광막(32)의 식각공정은 질소 및 산소 ( N2/O2 ) 가스를 베이스로 하는 플라즈마를 이용하여 실시한다. Here, the etching process of the photosensitive film 32 is performed using the plasma based on nitrogen and oxygen (N2 / O2) gas.

도시되지 않았으나, 후속 공정으로 내에칭 보호막(36) 패턴과 감광막(32) 패턴의 적층구조를 마스크로 하여 피식각층(30)을 식각함으로써 미세패턴을 형성한다. Although not shown, a fine pattern is formed by etching the etched layer 30 using a stacked structure of the etching-resistant protective film 36 pattern and the photosensitive film 32 pattern as a mask.

아울러, 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다. In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and modifications are as follows It should be regarded as belonging to the claims.

Claims (8)

피식각층이 형성된 반도체기판 상부에 감광막을 도포하는 공정과,
상기 감광막 표면에 라인형태의 홈을 형성하여 라인/스페이스 패턴을 형성하는 공정과,
상기 스페이스 패턴을 매립하는 내에칭 보호막 패턴을 형성하는 공정과,
상기 내에칭 보호막 패턴을 마스크로 하여 상기 감광막을 식각하여 내에칭 보호막 패턴 및 감광막패턴의 적층구조를 형성하는 공정과,
상기 적층구조를 마스크로 하여 피식각층을 식각함으로써 미세패턴을 형성하는 공정을 포함하는 반도체소자의 미세패턴 형성방법.Applying a photoresist film on the semiconductor substrate on which the etched layer is formed;
Forming a line / space pattern by forming a groove in a line shape on the surface of the photosensitive film;
Forming a etching-resistant protective film pattern filling the space pattern;
Etching the photosensitive film using the etched protective film pattern as a mask to form a laminated structure of the etched protective film pattern and the photosensitive film pattern;
Forming a fine pattern by etching the layer to be etched using the stacked structure as a mask. 제 1 항에 있어서,
상기 내에칭 보호막 패턴은 실리콘이 20 퍼센트 이상 함유된 절연막인 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1,
The etching pattern protective film pattern is a fine pattern forming method of a semiconductor device, characterized in that the silicon containing more than 20 percent. 제 1 항에 있어서,
상기 내에칭 보호막 패턴은 실리콘이 10 퍼센트 이상 함유된 절연막인 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1,
The etching pattern protective film pattern is a fine pattern forming method of a semiconductor device, characterized in that the insulating film containing more than 10 percent silicon. 제 1 항에 있어서,
상기 내에칭 보호막 패턴은 BPSG, PSG, USG, SOG 및 이들의 조합으로 이루어지 적층구조 중에서 선택된 임의의 한가지로 형성하는 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1,
The method of forming a fine pattern of a semiconductor device, characterized in that the etching-resistant protective film pattern is formed by any one selected from a stacked structure consisting of BPSG, PSG, USG, SOG, and combinations thereof. 제 1 항에 있어서,
상기 내에칭 보호막 패턴은
상기 스페이스 패턴을 매립하는 내에칭 보호막을 전체표면상부에 형성하는 공정과,
상기 내에칭 보호막을 평탄화 식각하는 공정을 포함하는 공정으로 형성한 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1,
The etched protective film pattern is
Forming an etching-resistant protective film filling the space pattern on the entire surface,
And forming a step of planarizing etching of the etch-resistant protective film. 제 5 항에 있어서,
상기 평탄화 식각공정은 에치백 공정이나 CMP 공정으로 실시하는 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 5, wherein
The planarization etching process is a fine pattern forming method of a semiconductor device, characterized in that performed by an etch back process or a CMP process. 제 6 항에 있어서,
상기 에치백 공정은 CxFy 계 가스를 주식각 가스로 사용하고 산소가스를 첨가가스로 사용하여 실시하는 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method according to claim 6,
The etchback process is performed using a CxFy-based gas as a stock angle gas and an oxygen gas as an additive gas. 제 1 항에 있어서,
상기 감광막 식각공정은 질소 및 산소 ( N2/O2 ) 가스를 베이스로 하는 플라즈마를 이용하여 실시하는 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1,
The method of etching the photoresist is performed using a plasma based on nitrogen and oxygen (N 2 / O 2) gas.
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