KR20110095062A - Printed circuit board assembly - Google Patents

Printed circuit board assembly Download PDF

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Publication number
KR20110095062A
KR20110095062A KR1020100014869A KR20100014869A KR20110095062A KR 20110095062 A KR20110095062 A KR 20110095062A KR 1020100014869 A KR1020100014869 A KR 1020100014869A KR 20100014869 A KR20100014869 A KR 20100014869A KR 20110095062 A KR20110095062 A KR 20110095062A
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KR
South Korea
Prior art keywords
circuit pattern
insulating member
forming
opening
semiconductor package
Prior art date
Application number
KR1020100014869A
Other languages
Korean (ko)
Other versions
KR101130608B1 (en
Inventor
이성규
정인원
Original Assignee
이성규
정인원
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Application filed by 이성규, 정인원 filed Critical 이성규
Priority to KR1020100014869A priority Critical patent/KR101130608B1/en
Publication of KR20110095062A publication Critical patent/KR20110095062A/en
Application granted granted Critical
Publication of KR101130608B1 publication Critical patent/KR101130608B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

The present invention provides an insulating member having semiconductor elements and solder balls attached to one surface and another surface, a circuit pattern formed inside the insulating member, and a wire formed on one surface of the insulating member and connected to the semiconductor element. Disclosed are a semiconductor package including a first opening forming a space for connection, and a second opening formed on the other surface of the insulating member and forming a space for connecting a solder ball and the circuit pattern.

Description

Semiconductor package and its manufacturing method {PRINTED CIRCUIT BOARD ASSEMBLY}

The present invention relates to a semiconductor package having a semiconductor device mounted thereon and a method of manufacturing the same.

A semiconductor package is a structure for protecting a semiconductor device from external physical and electrical shocks and electrically connecting the semiconductor device to an electronic device to implement the function. Is being implemented.

Such a semiconductor package generally has a form in which a semiconductor element is mounted on a semiconductor package substrate. The substrate for a semiconductor package has various structures, such as an insulating member, the circuit pattern which comprises an electrical circuit, and the soldering resist for protecting a circuit pattern with solder.

Semiconductor packages are being applied to various electronic devices such as computers and mobile phones, and electronic devices are becoming smaller and slimmer with the development of technology. In contrast, electronic components applied to electronic devices are becoming more integrated, and various efforts are being made to reduce their size or thickness in the field of semiconductor packages. In addition, it is required to reduce the manufacturing cost of the semiconductor package while reducing the size or thickness of the semiconductor package.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and it is an object of the present invention to provide a structure of a semiconductor package that can be manufactured at low cost and a method of manufacturing the same, while reducing the thickness of the semiconductor package.

The present invention for realizing the above object is an insulating member attached to the semiconductor device and the solder ball on one surface and the other surface, a circuit pattern formed inside the insulating member, and formed on one surface of the insulating member and the semiconductor device A semiconductor package including a first opening that forms a space for connecting the wire to the circuit pattern, and a second opening that is formed on the other surface of the insulating member and forms a space for connecting the solder ball and the circuit pattern. It starts.

The circuit pattern may be formed by being embedded into the insulating member by hot pressing in a state in which the insulating member is radiused.

The insulating member may be implemented with a solder resist to protect the circuit pattern.

An antioxidant layer for preventing oxidation may be formed on the circuit patterns exposed through the first and second openings.

The semiconductor elements may be provided in plural in a stacked form.

On the other hand, the present invention comprises the steps of forming a circuit pattern on one surface of the insulating member, embedding the circuit pattern into the insulating member, and the outside of the circuit pattern and the insulating member on one surface and the other surface of the insulating member Forming first and second openings to communicate with each other, and wire bonding a semiconductor device to the circuit pattern through the first opening, and connecting a solder ball to the circuit pattern through the second opening. Disclosed is a manufacturing method of.

The embedding of the circuit pattern may include placing a guide member for guiding the embedding of the circuit pattern on one surface of the circuit pattern, wherein the insulating member in a semi-cured state is introduced through the space between the circuit patterns, and And hot pressing the guide member to cover the circuit pattern.

On the other hand, the present invention comprises the steps of forming a circuit pattern on one surface of the separation sheet, and forming a first insulating member on one surface of the circuit pattern and to form a first opening that communicates to the circuit pattern on the first insulating member Exposing the other surface of the circuit pattern by separating the separating sheet, and forming a second insulating member to be integrated with the first insulating member on the other surface of the circuit pattern. Forming a second opening in communication with the circuit pattern, and wire bonding a semiconductor device to the circuit pattern through the first and second openings, and connecting a solder ball to the circuit pattern. Disclosed is a manufacturing method of.

According to the present invention having the above configuration, it is possible to implement a connection between the semiconductor device and the solder ball using a single-layer circuit pattern, it is possible to reduce the thickness of the semiconductor package and simplify the manufacturing process.

In addition, the present invention has the advantage of reducing the manufacturing cost through a manufacturing process that can produce a plurality of semiconductor packages in a single process.

1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.
2 to 6 illustrate a method of manufacturing a semiconductor package according to an embodiment of the present invention.
7 to 15 are views illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.

EMBODIMENT OF THE INVENTION Hereinafter, the semiconductor package which concerns on this invention, and its manufacturing method are demonstrated in detail with reference to drawings.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor package includes an insulating member 110, a circuit pattern 120, a first opening 130, and a second opening 140.

The insulating member 110 supports the semiconductor element 150 and serves as a medium for transmitting an electrical signal. The insulating member 110 may be formed of a material such as epoxy resin, phenol resin, polyimide, or the like.

The semiconductor device 150 is mounted on one surface of the insulating member 110, and the solder ball 160 is attached to the other surface. The solder ball 160 functions to physically and electrically connect the semiconductor package to the main board.

The circuit pattern 120 is formed inside the insulating member 110. That is, the circuit pattern 120 is embedded in an internal space formed between one surface and the other surface of the insulating member 110. The circuit pattern 120 is formed by patterning a conductive material (for example, copper) and is formed to be electrically connected to the semiconductor device 150 and the solder ball 160.

As the present invention, when the circuit pattern 120 is embedded in the insulating member 110, it is also possible to use a solder resist (Solder Resist) for protecting the circuit pattern 120 as the insulating member 110. The solder resist is generally applied on the substrate to protect the circuit pattern 120 from solder. However, in the present invention, the support structure of the circuit pattern 120 and the semiconductor device 150 may be implemented using the solder resist itself.

The first opening 130 is formed on one surface of the insulating member 110, and is formed from one surface of the insulating member 110 to the position of the circuit pattern 120.

The second opening 140 is formed on the other surface of the insulating member 110, and is formed from the other surface of the insulating member 110 to the position of the circuit pattern 120.

The circuit pattern 120 inside the insulating member 110 may communicate with the outside of the insulating member 110 by the first and second openings 130 and 140.

The semiconductor device 150 is mounted on the insulating member 110 by wire bonding. A conductive wire 170 is connected to one side of the semiconductor device 150, and the wire 170 is connected to the circuit pattern 120 through the first opening 130. That is, the first opening 130 provides a space for the wire 170 connected to the semiconductor device 150 to be connected to the circuit pattern 120.

Although the semiconductor device 150 may have a single number, the semiconductor device 150 may be provided in a plural number in a stacked form. The present embodiment illustrates a form in which the first semiconductor element 151 and the second semiconductor element 152 are stacked as one embodiment composed of a plurality of semiconductor elements.

A part of the solder ball 160 is formed in the second opening 140, and is connected to the circuit pattern 120 through the second opening 140. The second opening 140 provides a space for connecting the solder ball 160 and the circuit pattern 120.

Antioxidation layers 181 and 182 for preventing oxidation may be additionally formed on the circuit patterns 120 exposed through the first and second openings 130 and 140. The antioxidant layers 181 and 182 may be formed by applying gold plating on the exposed circuit pattern 120.

One surface of the insulating member 110 may further include a mold 190 for protecting the semiconductor device 150 from the outside.

The structure of the semiconductor package as described above has a single-layered circuit pattern 120, and has a structure in which the semiconductor device 150 and the solder ball 160 are connected to both surfaces of the single-layered circuit pattern 120, respectively. That is, the electrical connection between the semiconductor device 150 and the solder ball 160 on both surfaces of the insulating member may be implemented using only a single circuit pattern 120. Accordingly, the thickness of the semiconductor package may be reduced compared to a semiconductor package that is conventionally implemented with a multilayer circuit pattern, and a manufacturing process such as forming a via hole is not required to conduct the circuit pattern of the multilayer. There is an advantage to that.

2 to 6 are diagrams showing a method of manufacturing a semiconductor package according to an embodiment of the present invention.

In the method of manufacturing a semiconductor package according to the present embodiment, forming a circuit pattern 120 on one surface of an insulating member 110, embedding the circuit pattern 120 into the insulating member 110, and insulating Forming first and second openings 130 and 140 communicating the circuit pattern 120 with the outside of the insulating member 110 on one surface and the other surface of the member 110, and the semiconductor device through the first opening 130. Wire bonding 150 to the circuit pattern 120 and connecting the solder ball 160 to the circuit pattern 120 through the second opening 140.

Hereinafter, the manufacturing method will be described in detail with reference to FIGS. 2 to 6.

Referring to FIG. 2, first, circuit patterns 121 and 122 are formed on one surface of the insulating members 111 and 112. According to the present embodiment, the insulating members 111 and 112 include the first insulating member 111 and the second insulating member 112, which are attached to the separating sheet 210.

The separation sheet 210 is used to maintain the fixed state of the first and second insulating members 111 and 112 in a later process and to separate them when the process is completed. The adhesion sheet and the non-adhesion region of the separation sheet 210 may be formed, and the adhesion region may be formed along the outer edge of the non-adhesion region.

The first and second insulating members 111 and 112 are bonded to the adhesive region of the separating sheet 210, and according to the present embodiment, they may be attached to the separating sheet 210 by a heat press process in a semi-cured state. . When the portion corresponding to the adhesive region is cut later, the first and second insulating members 111 and 112 are separated from the separating sheet 210.

The circuit patterns 121 and 122 may be formed by forming conductors on the insulating members 111 and 112 and then patterning the conductors. By the patterning process, spaces 123 and 124 may be formed between the circuit patterns 121 and 122. The spaces 123 and 124 between the circuit patterns 121 and 122 may refer to spaces removed by etching during the etching process.

In this embodiment, a method of manufacturing two semiconductor packages in a single process using the separating sheet 210 is applied, but the semiconductor package substrate according to the present invention may be manufactured using only a single insulating member. .

Next, as illustrated in FIG. 3, the guide members 220 are positioned on the outer surfaces of the circuit patterns 121 and 122, and then heat presses are applied thereto. Accordingly, as shown in FIG. 4, the circuit patterns 121 and 122 are embedded in the insulating members 111 and 112 of the semi-cured state.

The guide members 220 are used to guide the circuit patterns 121 and 122 to be embedded into the insulating members 111 and 112 and have a sheet or plate shape. Copper foil may be used as the guide member 220.

The materials forming the insulating members 111 and 112 pass through the spaces 123 and 124 between the circuit patterns 121 and 122 according to the heat press process, and the materials forming the insulating members 111 and 112 are guide members 220 and the circuit pattern. And enter the gaps 121 and 122 to be positioned between the guide members 220 and the circuit patterns 121 and 122. Accordingly, a thin film formed by the insulating members 111 and 112 is formed between the guide members 220 and the circuit patterns 121 and 122, and the circuit patterns 121 and 122 are covered by the thin film. After this process, the insulating members 111 and 112 in a semi-cured state are cured.

Next, as shown in FIG. 5, the adhesive region portion (the dotted line portion of FIG. 4) of the separation sheet 210 is cut to separate the insulating members 111 and 112 from the separation sheet 210. Accordingly, two insulating members 111 and 112 having circuit patterns 121 and 122 embedded therein were manufactured through a single process.

As shown in FIG. 6, the first opening 130 and the second opening 140 are formed on both surfaces of the insulating member 111 through an etching process. The first and second openings 130 and 140 may be formed through a lithography process or by etching the insulating member 110 with a chemical, a plasma, or a laser.

In FIG. 6, only one of the two insulating members 111 and 112 is illustrated, but the same process may be performed on the other.

After the anti-oxidation films 181 and 182 are formed on the first and second openings 130 and 140, respectively, the semiconductor device 150 and the solder ball 160 are attached to the insulating member 111. As described above, the semiconductor device 150 is wire-bonded through the first opening 130, and the solder ball 160 is filled in the second opening 140 to complete the manufacturing process of the semiconductor package.

7 to 15 are views illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.

In the method of manufacturing a semiconductor package according to the present exemplary embodiment, the circuit pattern 125 is formed on one surface of the separation sheet 310 (see FIG. 7), and the first insulating member 115 is formed on one surface of the circuit pattern 125. Forming a first opening 131 communicating with the circuit pattern 125 on the first insulating member 115, and separating the separation sheet 310 to form the other surface of the circuit pattern 125. Exposing the second insulating member 116 to the first insulating member 115 on the other surface of the circuit pattern 125 and communicating with the circuit pattern 125 on the second insulating member 116. Forming the second openings 141, and wire-bonding the semiconductor device 150 to the circuit patterns 125 through the first and second openings 131 and 141, and solder balls 160 to the circuit patterns 125. Connecting to the.

Hereinafter, the manufacturing method will be described in detail with reference to FIGS. 7 to 15.

First, as shown in FIG. 7, conductors 126 are formed on both sides of the separation sheet 310. The separation sheet 310 of the present embodiment is composed of a base 311 and the release films 312. The release films 312 are attached to both sides of the base 311, and serve to fix the conductor 126. The release films 312 may have an adhesive region and a non-adhesive region similarly to the separation sheet 210 of the previous embodiment.

Next, as illustrated in FIG. 8, the conductor 126 is patterned to form a circuit pattern 125. After the first insulating member 115 is formed on the outer surface of the circuit pattern 125, at least a portion of the first insulating member 115 is etched to form the first opening 131. In this embodiment, a solder resist is used as the first insulating member 115. The anti-oxidation film 183 is formed on the exposed surface of the circuit pattern 125.

Next, as shown in FIG. 9, a pair of substrates prepared in FIG. 8 is provided, and the intermediate sheet 320 is positioned therebetween. And these are made to adhere using a hot press process.

The intermediate sheet 320 may include the first release film 321, the insulating members 322, and the second release films 323, which may be separated from each other in a state where they are bonded to each other. This may be implemented by the same principle as the separation sheet 210 and the release films 312 described above.

The insulating members 322 of the intermediate sheet 320 may have the same material as the first insulating member 115 of the substrate. In this embodiment, prepreg is used as the insulating members 322.

The second release films 323 may have a size slightly smaller than those of the insulating members 322, and the first insulating member 115 of the substrate and the insulating member 322 of the intermediate sheet 320 may be formed according to a heat press process. Will be attached to each other. Accordingly, as shown in FIG. 10, two substrates are integrated with the intermediate sheet 320.

Next, a part of the substrate is separated based on the dotted line of FIG. 10. That is, only the circuit pattern 125 formed on the upper side and the lower side of the intermediate sheet 320 is left, and the remaining portion is removed. This is possible by separating the release film 312 from the circuit pattern 125 as shown in FIG. 11, and thus the other surface of the circuit pattern 125 is exposed to the outside.

Next, as shown in FIG. 12, the second insulating member 116 is formed on the outer surface (the other surface) of the circuit pattern 125. The second insulating member 116 may be formed by a hot pressing process or a solder resist, whereby the first and second insulating members 115 and 116 are integrated.

The outer surface of the second insulating member 116 is etched to form a second opening 141. The anti-oxidation film 184 is formed in the portion exposed by the second opening 141.

Next, the substrate is cut based on the dotted line of FIG. 12 to separate the substrate into two parts. The dotted line in FIG. 12 becomes an adhesive region of the first release film 321, and as the substrate is cut, the substrate is separated into two parts based on the first release film 321 as shown in FIG. 13.

Next, as shown in FIG. 14, the semiconductor device 150 is attached to the second insulating member 116, and the wire 170 is connected to the semiconductor device 150 and the circuit pattern 125. Then, the mold 190 is formed on the outer surface of the second insulating member 116.

As described above, the semiconductor element 150 is mounted in the state in which the second release film 323 is attached to the insulating member 322 and completed until the mold is formed, thereby easily handling the thin substrate in the process.

Next, when the substrate is cut based on the dotted line of FIG. 14, portions on both sides thereof are separated based on the second release film 323 as shown in FIG. 15. Accordingly, a pair of substrate structures in which a part of the circuit pattern 125 is exposed through the first and second openings 131 and 141 are formed. 15 illustrates only one of the pair of substrate structures, the same process may be performed on the other one.

Next, when the solder ball 160 is attached to the first insulating member 115, the manufacturing of the semiconductor package is completed. This is the same as the method of the previous embodiment, the description thereof will be replaced with the previous description.

The above-described semiconductor package substrate and its manufacturing method are not limited to the configuration and method of the above-described embodiments, but the above embodiments are configured by selectively combining all or some of the embodiments so that various modifications can be made. May be

Claims (8)

An insulating member to which a semiconductor device and a solder ball are attached to one surface and the other surface, respectively;
A circuit pattern formed in the insulating member;
A first opening formed on one surface of the insulating member and forming a space for connecting a wire connected to the semiconductor element to the circuit pattern; And
And a second opening formed on the other surface of the insulating member and forming a space for connecting the solder ball and the circuit pattern. The method of claim 1,
The circuit pattern is a semiconductor package, characterized in that the insulating member is buried in the interior of the insulating member by hot pressing in a semi-radiated state. The method of claim 1,
The insulating member is a semiconductor package, characterized in that the solder resist for protecting the circuit pattern. The method of claim 1,
The semiconductor package according to claim 1, wherein an anti-oxidation film is formed on the circuit pattern exposed through the first and second openings. The method of claim 1,
The semiconductor package is characterized in that a plurality of semiconductor devices are stacked on each other. Forming a circuit pattern on one surface of the insulating member;
Embedding the circuit pattern into the insulating member;
Forming first and second openings on one surface and the other surface of the insulating member to communicate the circuit pattern with the outside of the insulating member; And
Wire bonding the semiconductor device to the circuit pattern through the first opening, and connecting a solder ball to the circuit pattern through the second opening. The method of claim 6, wherein the embedding of the circuit pattern,
Positioning a guide member on one surface of the circuit pattern to guide the embedding of the circuit pattern; And
And heat-pressing the guide member so that the insulating member in a semi-cured state flows through the space between the circuit patterns to cover the circuit pattern. Forming a circuit pattern on one surface of the separation sheet;
Forming a first insulating member on one surface of the circuit pattern, and forming a first opening that communicates with the circuit pattern on the first insulating member;
Separating the separation sheet to expose the other surface of the circuit pattern;
Forming a second insulating member on the other surface of the circuit pattern to be integrated with the first insulating member, and forming a second opening on the second insulating member to communicate with the circuit pattern; And
Wire-bonding a semiconductor device to the circuit pattern through the first and second openings, and connecting a solder ball to the circuit pattern.
KR1020100014869A 2010-02-18 2010-02-18 Printed circuit board assembly KR101130608B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100014869A KR101130608B1 (en) 2010-02-18 2010-02-18 Printed circuit board assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100014869A KR101130608B1 (en) 2010-02-18 2010-02-18 Printed circuit board assembly

Publications (2)

Publication Number Publication Date
KR20110095062A true KR20110095062A (en) 2011-08-24
KR101130608B1 KR101130608B1 (en) 2012-04-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102168268B1 (en) * 2020-05-06 2020-10-21 정승규 A Method for Manufacturing Radiator Structure of 5G Repeater

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058701A (en) * 1998-08-05 2000-02-25 Sumitomo Metal Mining Co Ltd Carrier tape with reinforcing section and semiconductor device using the same
KR100671541B1 (en) * 2001-06-21 2007-01-18 (주)글로벌써키트 A manufacturing method of printed circuit embedded board
TW200820853A (en) * 2006-09-29 2008-05-01 Nippon Steel Chemical Co Manufacturing method of flexible substrate
KR100779061B1 (en) * 2006-10-24 2007-11-27 삼성전기주식회사 Printed circuit board and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102168268B1 (en) * 2020-05-06 2020-10-21 정승규 A Method for Manufacturing Radiator Structure of 5G Repeater

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