KR20110077614A - Method manufactruing of flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash memory device is provided to prevent a part without a floating gate which is located in the lower part of a dielectric film when the dielectric film is etched from being excessively etched. CONSTITUTION: Poly-silicon(140) is formed on a semiconductor substrate(100) on which a device isolation film(110). The device isolation film defines an active area and a field area. A first insulating film is formed on the poly silicon. A second insulating film is formed on the frontal surface of a semiconductor substrate after a photo-resist pattern is eliminated. A floating gate(140a) with a step is formed by eliminating the first and second insulating films. A dielectric film and a control gate are formed on the frontal surface of the semiconductor substrate with the floating gate.

Description

Manufacturing method of flash memory device {Method Manufactruing of Flash Memory Device}

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device capable of increasing the contact area between a control gate and a floating gate.

Flash memory devices are a type of programmable ROM (PROM) capable of writing, erasing, and reading information.

Flash memory devices may be divided into NOR-type structures in which cells are disposed in parallel between bit lines and ground, and NAND-type structures arranged in series, according to a cell array scheme.

NOR flash memory devices are commonly used for booting mobile phones because they allow high-speed random access when performing read operations. NAND-type flash memory devices have a slow read speed but a fast write speed, and are suitable for data storage and small size.

In addition, the flash memory device may be classified into a stack gate type and a split gate type according to the unit cell structure, and the floating gate element and the silicon-oxide-nitride-oxide-silicon (SONOS) depending on the type of the charge storage layer. It can be divided into elements. Among them, the floating gate device typically includes a floating gate formed of polycrystalline silicon surrounded by an insulator, and the floating gate is charged by channel hot carrier injection or FN tunneling by Fowler-Nordheim Tunneling. Is injected or discharged to store and erase data.

The cell structure of such a general flash memory device includes a semiconductor substrate, a tunnel oxide film, a floating gate, an oxide / nitride / oxide, and a control gate, and between the floating gate, the ONO and the control gate. Filled with

Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device capable of increasing the contact area between a control gate and a floating gate.

A method of manufacturing a flash memory device according to a first exemplary embodiment of the present invention includes forming polysilicon on a semiconductor substrate on which a device isolation layer for defining active and field regions is formed, and forming a first insulating film on the polysilicon. Etching the portion of the first insulating layer and the polysilicon through a first etching process using a photoresist pattern exposing the first insulating layer in a region corresponding to the device isolation layer as a mask; After removing the photoresist pattern, forming a second insulating film on the entire surface of the semiconductor substrate including the first insulating film, exposing the second insulating film to the device isolation layer through a second etching process; Removing the first insulating film and the second insulating film to form a floating gate having a step difference; And forming a dielectric film and a control gate on the entire surface of the semiconductor substrate.

A method of manufacturing a flash memory device according to a second embodiment of the present invention includes forming polysilicon on a semiconductor substrate on which a device isolation film for defining an active region and a field region is formed; Etching a portion of the polysilicon through a first etching process using a first photoresist pattern exposing the polysilicon as a mask, and making the first photoresist pattern larger than its original size to form a second photoresist Forming a pattern, etching the polysilicon exposed through a second etching process using the second photoresist pattern as a mask, and removing the second photoresist pattern to form a floating gate having a step Forming a dielectric film and a control gate over an entire surface of the semiconductor substrate including the floating gate; It characterized in that it comprises a step of forming.

As described above, in the method of manufacturing the flash memory device according to the present invention, the vertical length of the dielectric film formed on the sidewall of the floating gate is reduced to less than half of that of a general flash memory device due to the step of the floating gate, thereby reducing the dielectric film during etching. Etching is possible in a shorter time. In addition, the depth of the valley generated when the dielectric film is etched can be reduced by more than half. Therefore, in a general flash memory device process, over-etching may be prevented in a portion where the floating gate does not exist below the dielectric layer during vertical dielectric layer etching.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described by at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

In addition, the terminology used in the present invention is a general term that is currently widely used as much as possible, but in certain cases, the term is arbitrarily selected by the applicant. In this case, since the meaning is described in detail in the description of the present invention, It is to be understood that the present invention is to be understood as the meaning of the term rather than the name.

1A to 1E are cross-sectional views illustrating a manufacturing process of a flash memory device according to a first embodiment of the present invention.

1A to 1E show only regions related to the present invention among all flash memory devices. Since the other areas have the same configuration as a general flash memory device, illustration thereof will be omitted.

First, as shown in FIG. 1A, in the method of manufacturing a flash memory device according to the first embodiment of the present invention, a crystal defect of an upper surface of the semiconductor substrate 100 on the semiconductor substrate 100 having a cell region and a logic region is provided. A tunnel oxide film (not shown) is formed for suppression or surface treatment.

Here, the semiconductor substrate 100 is in a state in which a device isolation film 110, a well (not shown), and a channel (not shown) forming process for defining an active region and a device isolation region is completed.

On the other hand, the logic region is also formed at the time of forming the cell region and will not be described separately.

Thereafter, polysilicon 140 for a floating gate having a function of storing charge is deposited on the entire surface of the semiconductor substrate 100 including the device isolation layer 110 and the tunnel oxide layer.

Next, as shown in FIG. 1B, after forming the polysilicon 140 for the floating gate, the first insulating layer 160 is formed on the entire surface of the semiconductor substrate 100 including the polysilicon 140. Here, the first insulating layer 160 is preferably formed of TEOS using a low pressure chemical vapor deposition (LP CVD) process.

Subsequently, after the photoresist is coated on the entire surface of the first insulating layer 160, the photoresist pattern 180 exposing a portion of the first insulating layer 160 corresponding to the device isolation region through an exposure and development process. To form.

1C, a portion of the first insulating layer 160 and the polysilicon 140 exposed through the first dry etching process using the formed photoresist pattern 180 as an etching mask. Etch Here, the polysilicon 140 on the device isolation layer 110 is partially etched so that the device isolation layer 110 is not exposed.

Next, as shown in FIG. 1D, after removing the photoresist pattern 180, a second insulating layer 200 is formed on the entire surface of the resultant. Thereafter, the formed second insulating layer 200 and the remaining polysilicon 140 are etched until the device isolation layer 110 is exposed through the second dry etching process. Here, as the remaining polysilicon 140 exposed by the second insulating layer 200 is completely removed, the remaining polysilicon 140 has a step.

Subsequently, as shown in FIG. 1E, the first insulating layer 160 and the second insulating layer 200 are removed through a wet etching process to form a floating gate 140a having a step.

Then, a dielectric film 220 having an oxide-nitride-oxide (ONO) structure and a polysilicon 240 for a control gate are sequentially formed on the entire surface of the semiconductor substrate 100 including the floating gate 140a and patterned thereon. A flash memory device is completed by performing a subsequent process of a general flash memory device such as forming a gate pattern.

At this time, the vertical length A of the dielectric film 220 formed on the sidewall of the floating gate 140a decreases to less than half of that of a general flash memory device due to the step difference of the floating gate 140a, thereby etching the dielectric film 220. Etching is possible in a shorter time. In addition, the depth of the valleys generated when the dielectric layer 220 is etched may be reduced to about half or more. Therefore, in a general flash memory device process, over-etching may be prevented in a portion where the floating gate does not exist below the dielectric layer during vertical dielectric layer etching.

On the other hand, before the dielectric film 220 is formed, the first insulating film 160 and the second insulating film 200 are removed to form a floating gate 140a having a step, and then through a chemical downstream etching (CDE) process. The corner portion of the floating gate 140a may be etched to be rounded. As such, since the corner portion of the floating gate 140a is rounded, the vertical length A of the dielectric film 220 of the sidewall of the floating gate 140a formed in a subsequent process may be further reduced.

2A to 2E are cross-sectional views illustrating a manufacturing process of a flash memory device according to a second exemplary embodiment of the present invention.

However, in the manufacturing process of the flash memory device according to the second embodiment of the present invention shown in Figure 2a to 2e is given the same reference numerals as the first embodiment, and the description of the same parts will be omitted.

First, as illustrated in FIG. 2A, in the method of manufacturing a flash memory device according to the second embodiment of the present invention, a crystal defect of an upper surface of a semiconductor substrate 100 on a semiconductor substrate 100 having a cell region and a logic region is provided. A tunnel oxide film (not shown) is formed for suppression or surface treatment.

Here, the semiconductor substrate 100 is in a state in which a device isolation film 110, a well (not shown), and a channel (not shown) forming process for defining an active region and a device isolation region is completed.

Thereafter, polysilicon 140 for a floating gate having a function of storing charge is deposited on the entire surface of the semiconductor substrate 100 including the device isolation layer 110 and the tunnel oxide layer.

Subsequently, as shown in FIG. 2B, polysilicon 140 is formed for the floating gate. After the photoresist is applied to the entire surface of the semiconductor substrate 100 including the polysilicon 140, a photoresist exposing a portion of the polysilicon 140 corresponding to the device isolation region through an exposure and development process. The resist pattern 180 is formed.

Then, as illustrated in FIG. 2C, a portion of the polysilicon 140 exposed through the first dry etching process using the formed photoresist pattern 180 as an etching mask is etched. Here, the polysilicon 140 on the device isolation layer 110 is partially etched so that the device isolation layer 110 is not exposed.

Thereafter, the size of the patterned photoresist pattern 180a is made larger than the original size through a polymer generation process using a polymer generated by the dry etching process.

Subsequently, as illustrated in FIG. 2D, the first insulating layer 160 and the polysilicon 140 are etched through a second dry etching process using the photoresist pattern 180a larger than the original size as an etching mask. The device isolation layer 110 is exposed.

Next, as shown in FIG. 2E, the floating gate 140a is formed by removing the photoresist pattern 180a. At this time, the remaining floating gate 140a has a step.

Then, although not shown, a dielectric film made of an oxide-nitride-oxide (ONO) structure and a control gate polysilicon are sequentially formed on the entire surface of the semiconductor substrate 100 including the floating gate 140a, and then patterned to form a gate. A flash memory device is completed by performing a subsequent process of a general flash memory device such as forming a pattern.

At this time, the vertical length (A) of the dielectric film formed on the sidewall of the floating gate 140a is reduced to less than half compared to a general flash memory device due to the step of the floating gate 140a, so that the etching is performed in a shorter time during the dielectric film etching. It is possible. In addition, the depth of the valley generated when the dielectric film is etched can be reduced by more than half.

Accordingly, in the flash memory device according to the second embodiment of the present invention, in the general flash memory device process, over etching may be prevented in a portion where the floating gate does not exist below the dielectric film during the vertical dielectric film etching.

Meanwhile, before forming the dielectric film, as in the first embodiment of the present invention, after forming the floating gate 140a, the corner portion of the floating gate 140a may be etched by the CDE process. . As such, since the corner portion of the floating gate 140a is rounded, the vertical length A of the dielectric film 220 of the sidewall of the floating gate 140a formed in a subsequent process may be further reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1A to 1E are cross-sectional views illustrating a manufacturing process of a flash memory device according to a first embodiment of the present invention.

2A to 2E are cross-sectional views illustrating a process of manufacturing a flash memory device according to a second embodiment of the present invention.

Claims (9)

Forming polysilicon on a semiconductor substrate on which an isolation layer for defining an active region and a field region is formed; Forming a first insulating film on the polysilicon; Etching the first insulating film and a portion of the polysilicon through a first etching process using a photoresist pattern exposing the first insulating film in a region corresponding to the device isolation layer as a mask; After removing the photoresist pattern, forming a second insulating film on the entire surface of the semiconductor substrate including the first insulating film; Exposing the device isolation layer through a second etching process of the second insulating layer; Removing the first insulating film and the second insulating film to form a floating gate having a step; And forming a dielectric film and a control gate on the entire surface of the semiconductor substrate including the floating gate. The method of claim 1, The first and second etching process is a method of manufacturing a flash memory device, characterized in that the dry etching process. The method of claim 1, And the first and second insulating layers are formed of TEOS. The method of claim 1, The first etching process is And partially etching the polysilicon on the device isolation layer and remaining the polysilicon on the device isolation layer. Forming polysilicon on a semiconductor substrate on which an isolation layer for defining an active region and a field region is formed; Etching a portion of the polysilicon through a first etching process using a first photoresist pattern exposing the polysilicon in a region corresponding to the device isolation layer as a mask; Making the first photoresist pattern larger than its original size to form a second photoresist pattern; Etching the polysilicon exposed through the second etching process using the second photoresist pattern as a mask; Removing the second photoresist pattern to form a floating gate having a step; And forming a dielectric film and a control gate on the entire surface of the semiconductor substrate including the floating gate. The method of claim 5, And the second photoresist pattern is formed through a polymer generation process. The method of claim 5, Etching the polysilicon exposed to the second photoresist pattern as a mask And etching until the device isolation layer is exposed. The method of claim 5, The first and second etching process is a method of manufacturing a flash memory device, characterized in that the dry etching process. The method according to claim 1 or 2, After forming the floating gate, etching the corner portion of the floating gate through a chemical downstream stream etching (CDE) process.

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