KR20110077564A - Integrated circuit array - Google Patents

Abstract

PURPOSE: An integrated circuit array is provided to minimize layout in an integrated circuit by sharing a voltage supply line for supplying a driving voltage to a plurality of sense amplifier circuit units in one sense amplifier driving circuit. CONSTITUTION: A first sense amplifier circuit unit(100_1) amplifies a current applied from a first memory cell through a first bit line pair. A first sense amplifier driving circuit unit(210_1) drives power voltage for the amplification operation of the first sense amplifier circuit unit. A first voltage supply line connects the first sense amplifier circuit unit to the first sense amplifier driving circuit unit for supplying a power voltage. A second sense amplifier circuit unit amplifies a current applied from a second memory cell through a second bit line pair. A second sense amplifier driving circuit unit(220_1) drives the power voltage for the amplification operation of the second sense amplifier circuit unit. A second voltage supply line connects the second sense amplifier circuit unit to the second sense amplifier driving circuit unit for supplying the power voltage.

Description

Integrated Circuit Array {INTEGRATED CIRCUIT ARRAY}

The present invention relates to an integrated circuit array usable in semiconductor memory devices.

In general, semiconductor memory devices store data in a plurality of cells and read the stored data.

The semiconductor memory device senses data through bit lines connected to a plurality of cells, respectively, and the sense amplifier senses the amount of current flowing through the bit line, amplifies it, and reads the data.

In recent years, the degree of integration is increasing in semiconductor memory devices, and it is important to efficiently utilize the layout inside the semiconductor memory device. As a result, there is a problem in that the layout occupied by each component inside the semiconductor memory device must be minimized.

In addition, as the degree of integration of semiconductor memory devices increases, the possibility of interference between adjacent components may increase. As a result, there is a problem in that interference between adjacent components should be minimized while increasing the density of the semiconductor memory device.

The present invention relates to an integrated circuit array that efficiently arranges a line connecting the integrated circuit and the integrated circuits to solve the above problems.

The present invention includes a plurality of sensing units for sensing currents applied from a plurality of memory cells, each sensing unit circuit unit for amplifying a current applied through a pair of bit lines from each of the plurality of memory cells, a sense amplifier Disclosed is an integrated circuit array including a sense amplifier driving circuit unit for driving a power supply voltage required for an amplification operation of a circuit unit, and a voltage supply line connecting the sense amplifier circuit unit and the sense amplifier driving circuit unit to supply a power supply voltage.

Additionally, the present invention discloses an integrated circuit array comprising bit line equalization circuitry in which the sense amplifier circuitry equalizes the bit line pairs to the same voltage level.

Additionally, the bit line equalization circuit of the present invention is characterized by equalizing the pair of bit lines when the bit line equalization signal is enabled.

Additionally, the sense amplifier circuit portion of the present invention discloses an integrated circuit array further comprising a bit line blocking circuit for disconnecting the bit line pair when the bit line blocking signal is enabled.

Additionally, the present invention discloses an integrated circuit array, wherein the sense amplifier circuitry further includes a bitline precharge circuit for precharging the bitline pair when the bitline precharge signal is enabled.

Additionally, the bit line precharge circuit of the present invention is characterized by precharging the pair of bit lines to the same voltage level.

Additionally, the present invention may further include a first sense amplifier driving circuit configured to drive the power supply voltage supplied to the sense amplifier circuit unit to a first voltage level, and then drive the second voltage level to a second voltage level; And a second sense amplifier driving circuit for driving the power supply voltage supplied to the sense amplifier circuit unit to a third voltage level, wherein the first voltage level is higher than the second voltage level, and the second voltage level is equal to the second voltage level. An integrated circuit array is disclosed that is higher than a third voltage level.

In addition, the present invention may include a first voltage supply line connecting the first sense amplifier driving circuit and the sense amplifier circuit unit to the voltage supply line; And a second voltage supply line connecting the second sense amplifier driving circuit and the sense amplifier circuit unit.

Additionally, the present invention discloses an integrated circuit array wherein the sense amplifier drive circuitry further comprises an equalization circuit for equalizing the first voltage supply line and the second voltage supply line to the same voltage level.

Additionally, the present invention discloses an integrated circuit array, wherein the sense amplifier driving circuit unit further includes a precharge circuit configured to precharge the first voltage supply line and the second voltage supply line.

The present invention includes a plurality of sensing units for sensing a current applied through a pair of bit lines from a memory cell, wherein each of the plurality of sensing units comprises: a plurality of sense amplifier circuit units for amplifying a current applied through the pair of bit lines; A sense amplifier driving circuit unit for driving a power supply voltage required for the amplifying operation of the sense amplifier circuit unit; And a voltage supply line connecting the plurality of sense amplifier circuit units and the sense amplifier driving circuit unit to supply the power voltage.

Additionally, the present invention discloses an integrated circuit array comprising bit line equalization circuitry in which the sense amplifier circuitry equalizes the bit line pairs to the same voltage level.

Additionally, the bit line equalization circuit of the present invention is characterized by equalizing the pair of bit lines when the bit line equalization signal is enabled.

Additionally, the sense amplifier circuit portion of the present invention discloses an integrated circuit array further comprising a bit line blocking circuit for disconnecting the bit line pair when the bit line blocking signal is enabled.

Additionally, the present invention discloses an integrated circuit array, wherein the sense amplifier circuitry further includes a bitline precharge circuit for precharging the bitline pair when the bitline precharge signal is enabled.

Additionally, the bit line precharge circuit of the present invention is characterized by precharging the pair of bit lines to the same voltage level.

In addition, the present invention may further include a first sense amplifier driving circuit driving the power supply voltage supplied to the sense amplifier circuit unit to a first voltage level after the sense amplifier driving circuit unit is driven to a second voltage level; And a second sense amplifier driving circuit for driving the power supply voltage supplied to the sense amplifier circuit unit to a third voltage level, wherein the first voltage level is higher than the second voltage level, and the second voltage level is equal to the second voltage level. An integrated circuit array is disclosed that is higher than a third voltage level.

In addition, the present invention may include a first voltage supply line connecting the first sense amplifier driving circuit and the sense amplifier circuit unit to the voltage supply line; And a second voltage supply line connecting the second sense amplifier driving circuit and the sense amplifier circuit unit.

Additionally, the present invention discloses an integrated circuit array wherein the sense amplifier drive circuitry further comprises an equalization circuit for equalizing the first voltage supply line and the second voltage supply line to the same voltage level.

Additionally, the present invention discloses an integrated circuit array, wherein the sense amplifier driving circuit unit further includes a precharge circuit configured to precharge the first voltage supply line and the second voltage supply line.

The present invention has the advantage that the layout of the integrated circuit can be minimized by sharing a voltage supply line for supplying a driving voltage to the plurality of sense amplifier circuit units.

In addition, the present invention provides an advantage of preventing the sensing malfunction problem caused by leakage current flowing between different sense amplifier circuit units by separately forming lines for supplying a driving voltage from the sense amplifier driver circuit unit to the sense amplifier circuit unit. have.

Preferred embodiments of the present invention are for purposes of illustration, and those skilled in the art can make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications may be made by the following claims. Should be seen as belonging to.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a circuit diagram of an integrated circuit according to the present invention.

Referring to FIG. 1, an integrated circuit according to the present invention includes a sensing unit 10. The sensing unit 10 includes a sense amplifier circuit unit 100 and a sense amplifier driving circuit unit 200.

The sense amplifier circuit unit 100 includes a sense amplifier 110, a bit line equalization circuit 111, a bit line blocking circuit 121 and 122, and a bit line precharge circuit 130. And a first sense amplifier driving circuit 210, a second sense amplifier driving circuit 220, an equalization circuit 230, and a precharge circuit 240.

The sense amplifier 110 senses and amplifies the current flowing through the bit lines BL and / BL.

The sense amplifier 110 includes NMOS transistors N1 and N2 and PMOS transistors P1 and P2.

In the sense amplifier 110, the drain terminal of the NMOS transistor N1 is connected with the drain terminal of the PMOS transistor P1, the source terminal of the NMOS transistor N1 is connected with the pull-down voltage supply line SB, and the source terminal of the PMOS transistor P1 is pulled up The NMOS transistor N1 and the PMOS transistor P1 share a gate and the common gate terminal is connected to the bit line / BL.

On the other hand, the drain terminal of the NMOS transistor N2 is connected to the drain terminal of the PMOS transistor P2, the source terminal of the NMOS transistor N2 is connected to the pull-down voltage supply line SB, and the source terminal of the PMOS transistor P2 is connected to the pull-up voltage supply line RTO. The NMOS transistor N2 and the PMOS transistor P2 share a gate and a common gate terminal is connected to the bit line BL.

The sense amplifier 110 is supplied with a pull-up voltage from the first sense amplifier driving circuit 210 through the pull-up voltage supply line RTO, and is pulled from the second sense amplifier driving circuit 220 through the pull-down voltage supply line SB. The down voltage is supplied. The operation of the specific sense amplifier 110 will be described later.

The bit line equalization circuits 111 and 112 serve to equalize the voltage levels of the bit lines BL and / BL.

The bit line equalization circuit 111 includes an NMOS transistor N3.

In the NMOS transistor N3, the drain / source terminal is connected to the bit lines BL and / BL, respectively, and the bit line equalization signal BLEQB is input to the gate terminal. When the bit line equalization signal BLEQB is input to the gate terminal of the NMOS transistor N3 at a high level, the NMOS transistor N3 is turned on to equalize the voltage level of the bit lines BL and / BL, and the bit line equalization signal BLEQB is input to the low level. When the NMOS transistor N3 is turned off, the bit lines BL and / BL are blocked from each other.

On the other hand, the bit line equalization circuit 112 includes an NMOS transistor N4.

In the NMOS transistor N4, the drain / source terminal is connected to the bit lines BL and / BL, respectively, and the bit line equalization signal BLEQB is input to the gate terminal. When the bit line equalization signal BLEQB is input to the gate terminal of the NMOS transistor N4 at a high level, the NMOS transistor N3 is turned on to equalize the voltage level of the bit lines BL and / BL, and when the bit line equalization signal BLEQB is input to the low level, the NMOS is applied. The transistor N4 is turned off to block the bit lines BL and / BL from each other.

The bit line blocking circuits 121 and 122 block the connection between the sense amplifier 110 and the bit lines BL and / BL.

The bit line blocking circuit 121 includes NMOS transistors N5 and N6.

The NMOS transistor N5 has a drain terminal connected to the bit line BL on the cell array 300 side, a source terminal connected to the bit line BL on the sense amplifier 110 side, and a bit line blocking signal BISH is input to the gate terminal. When the bit line blocking signal BISH is input to the gate terminal of the NMOS transistor N5 at a high level, the NMOS transistor N5 is turned on so that a current flowing through the bit line BL from the cell array 300 flows into the sense amplifier 110. On the contrary, when the bit line blocking signal BISH is input to the gate terminal of the NMOS transistor N5 at a low level, the NMOS transistor N5 is turned off, and no more current flows from the cell array 300 to the sense amplifier 110 through the bit line BL. It does not enter.

The NMOS transistor N6 has a drain terminal connected to the bit line / BL on the cell array 300 side, a source terminal connected to the bit line / BL on the sense amplifier 110 side, and a bit line blocking signal BISH is input to the gate terminal. do. When the bit line blocking signal BISH is input to the gate terminal of the NMOS transistor N6 at a high level, the NMOS transistor N6 is turned on so that a current flowing through the bit line / BL from the cell array 300 flows into the sense amplifier 110. . On the contrary, when the bit line blocking signal BISH is input to the gate terminal of the NMOS transistor N6 at a low level, the NMOS transistor N6 is turned off, and no more current flows from the cell array 300 to the sense amplifier 110 through the bit line / BL. It does not enter.

On the other hand, the bit line blocking circuit 122 includes NMOS transistors N7 and N8.

The NMOS transistor N7 has a drain terminal connected to the bit line BL at the cell array 400 side, a source terminal connected to the bit line BL at the sense amplifier 110 side, and a bit line blocking signal BISL is input to the gate terminal. When the bit line blocking signal BISL is input to the gate terminal of the NMOS transistor N7 at a high level, the NMOS transistor N7 is turned on so that a current flowing through the bit line BL from the cell array 400 flows into the sense amplifier 110. On the contrary, when the bit line blocking signal BISL is input to the gate terminal of the NMOS transistor N7 at a low level, the NMOS transistor N7 is turned off, and no more current flows from the cell array 400 to the sense amplifier 110 through the bit line BL. You won't go.

The NMOS transistor N8 has a drain terminal connected to the bit line / BL on the cell array 400 side, a source terminal connected to the bit line / BL on the sense amplifier 110 side, and a bit line blocking signal BISL is input to the gate terminal. do. When the bit line blocking signal BISL is input to the gate terminal of the NMOS transistor N8 at a high level, the NMOS transistor N8 is turned on so that a current flowing through the bit line / BL from the cell array 400 flows into the sense amplifier 110. . On the contrary, when the bit line blocking signal BISL is input to the gate terminal of the NMOS transistor N8 at a low level, the NMOS transistor N8 is turned off, and no more current flows from the cell array 400 to the sense amplifier 110 through the bit line / BL. It does not enter.

The bit line precharge circuit 130 precharges the bit lines BL and / BL.

The bit line precharge circuit 130 includes NMOS transistors N9 and N10.

The NMOS transistors N9 and N10 share a drain terminal and a gate terminal, a bit line precharge voltage VBLP is applied to a common drain terminal, and a bit line precharge signal BLP is input to a common gate terminal.

When the bit line precharge signal BLP is input to the common gate terminal of the NMOS transistors N9 and N10 at a high level, the NMOS transistors N9 and N10 are turned on to supply the bit line precharge voltage VBLP to the bit lines BL and / BL. On the contrary, when the bit line precharge signal BLP is input at the low level, the NMOS transistors N9 and N10 are turned off so that the bit line precharge voltage VBLP is not supplied to the bit lines BL and / BL.

The first sense amplifier driving circuit 210 supplies the pull up voltage to the sense amplifier 110 through the pull-up voltage supply line RTO.

The first sense amplifier driving circuit 210 includes PMOS transistors P3 and P4.

The PMOS transistor P3 is supplied with a power supply voltage VDD to a source terminal, a drain terminal thereof is connected to a pull-up voltage supply line RTO, and a control signal SAP1 is input to a gate terminal. When the control signal SAP1 is input to the gate terminal of the PMOS transistor P3 at the high level, the PMOS transistor P3 is turned off to cut off the supply of the power supply voltage VDD. When the control signal SAP1 is input to the low level, the PMOS transistor P3 is turned on to supply the power supply voltage. VDD is supplied to the pullup voltage supply line RTO. As a result, the power supply voltage VDD is supplied to the sense amplifier 110 to perform an amplification operation.

The PMOS transistor P4 is supplied with the core power supply voltage VCORE to the source terminal, the drain terminal thereof is connected to the pull-up voltage supply line RTO, and the control signal SAP2 is input to the gate terminal. When the control signal SAP2 is input to the gate terminal of the PMOS transistor P4 at the high level, the PMOS transistor P4 is turned off to cut off the supply of the core power supply voltage VCORE, and when the control signal SAP2 is input to the low level, the PMOS transistor P4 is turned on to the core. Supply voltage VCORE is supplied to the pull-up voltage supply line RTO. As a result, the core power supply voltage VCORE is supplied to the sense amplifier 110 to perform an amplification operation.

The reason why the power supply voltage VDD and the core power supply voltage VCORE are supplied to the sense amplifier 110 as a pull-up voltage will be described later.

The second sense amplifier driving circuit 220 supplies the pull down voltage to the sense amplifier 110 through the pull down voltage supply line SB.

The second sense amplifier driving circuit 220 includes an NMOS transistor N11.

The NMOS transistor N11 has a drain terminal connected to a pull-down voltage supply line SB, a source terminal connected to a ground voltage VSS terminal, and a control signal SAN is input to the gate terminal. When the control signal SAN is input to the gate terminal of the NMOS transistor N11 at a high level, the NMOS transistor N11 is turned on to supply the ground voltage VSS from the ground voltage VSS terminal to the sense amplifier 110 through the pull-down voltage supply line SB. When the signal SAN is input at the low level, the NMOS transistor N11 is turned off so that the ground voltage VSS is not supplied from the ground voltage VSS terminal to the sense amplifier 110.

The equalization circuit 230 serves to equalize voltage levels of the pull-up voltage supply line RTO and the pull-down voltage supply line SB.

Equalization circuit 230 includes NMOS transistor N12.

The NMOS transistor N12 has a drain terminal connected to the pull-up voltage supply line RTO, a source terminal connected to the pull-down voltage supply line SB, and an equalization signal BLEQ is input to the gate terminal. When the control signal BLEQ is input at high level, the NMOS transistor N12 is turned on to equalize the pull-up voltage supply line RTO and pull-down voltage supply line SB, and when the control signal BLEQ is input at low level, the NMOS transistor N12 is turned off to pull up. The up voltage supply line RTO and the pull down voltage supply line SB are disconnected from each other.

The precharge circuit 240 precharges the pull-up voltage supply line RTO and the pull-down voltage supply line SB to the bit line precharge voltage VBLP.

The precharge circuit 240 includes NMOS transistors N13 and N14.

The NMOS transistors N13 and 14 share a drain terminal and a gate terminal, a bit line precharge voltage VBLP is supplied to a common drain terminal, and a control signal BLEQ is input to the common gate terminal. The NMOS transistor N13 has a source terminal connected to the pull-up voltage supply line RTO, and the NMOS transistor N14 has a source terminal connected to the pull-down voltage supply line SB.

When the control signal BLEQ is input to the common gate terminal of the NMOS transistors N13 and N14 at a high level, the NMOS transistors N13 and N14 are turned on so that the precharge voltage VBLP is supplied to the pull-up voltage supply line RTO and the pull-down voltage supply line SB. . On the contrary, when the control signal BLEQ is input at the low level, the NMOS transistors N13 and N14 are turned off so that the precharge voltage VBLP is not supplied to the pull-up voltage supply line RTO and the pull-down voltage supply line SB.

2 is a timing diagram illustrating a data sensing operation by an integrated circuit according to the present invention.

Referring to FIG. 2, in the first period T1, the bit lines BL and / BL are not pre-charged to the precharge voltage VBLP level by the bit line precharge circuit 130.

In the second period T2, when a cell included in the cell array is selected, the capacitor of the selected cell and the capacitance of the bit line BL or bit line / BL connected to the capacitor are charged sharing, so that the bit line BL and the bit line are shared. A voltage difference of ΔV occurs between / BL.

In the third period T3, when the control signal SAP1 is enabled, the PMOS transistor P3 is turned on to supply the power supply voltage VDD having a level higher than the core power supply voltage VCORE to the sense amplifier 110 through the pull-up voltage supply line RTO. As a result, the bit line BL is overdriven to the power supply voltage VDD level in the initial operation of the sense amplifier 110.

In the fourth period T4, when the control signal SAP1 is disabled, the PMOS transistor P3 is turned off to stop the supply of the power supply voltage VDD. When the control signal SAP2 is enabled, the PMOS transistor P4 is turned on to pull the pull-up voltage supply line RTO. The core power supply voltage VCORE is supplied to the sense amplifier 110 through the sensing amplifier 110.

When the control signal SAN is enabled, the NMOS transistor N1 is turned on to supply the ground voltage VSS to the sense amplifier 110 through the pull-down voltage supply line SB.

As a result, the bit line BL maintains the core power supply voltage VCORE level, and the bit line / BL falls to the ground voltage VSS level, so that the small voltage difference ΔV applied from the cell selected at the beginning of the operation of the sense amplifier 110 is reduced. It's going to be big.

In the integrated circuit according to the present invention, separately supplying the power supply voltage VDD and the core power supply voltage VCORE from the sense amplifier driving circuit unit 200 may overdrive the bitline BL to the power supply voltage VDD higher than the core power supply voltage VCORE, thereby causing the bitline BL, This is to make the voltage difference between / BL spread rapidly. As a result, the operation speed of the integrated circuit is increased.

3 is a circuit diagram illustrating an integrated circuit array according to a first embodiment of the present invention.

Referring to FIG. 3, the integrated circuit array according to the first embodiment of the present invention includes a plurality of sensing units 10_1 to 10_N.

In the integrated circuit array according to the first embodiment of the present invention, each sensing unit 10_1 includes one sense amplifier driving circuit unit 200_1 and two sense amplifier circuit units 100_1 and 100_2. One sense amplifier driving circuit unit 200_1 shares two sense amplifier circuit units 100_1 and 100_2. Sharing means that one sense amplifier driving circuit unit 200_1 shares the voltage supply lines RTO_1 and SB_1 with two sense amplifier circuit units 100_1 and 100_2, thereby supplying a driving voltage.

However, the first embodiment of the present invention is not limited to the above case, and one sense amplifier driving circuit unit may share a plurality of sense amplifier circuit units. For example, three sense amplifier circuit units may be shared in one sense amplifier driving circuit unit. In this case, one sense amplifier driving circuit unit and three sense amplifier circuit units included in one sensing unit may include voltage supply lines RTO and SB. Will be shared.

Referring to FIG. 3, a plurality of sense amplifier circuit units 100_1 and 100_2 are supplied with a power supply voltage VDD or a core power supply voltage VCORE through the pull-up voltage supply line RTO_1 at the same timing by the first sense amplifier driving circuit 210_1. . The ground voltage VSS is supplied to the plurality of sense amplifier circuit units 100_1 and 100_2 through the pull-down voltage supply line SB_1 at the same timing by the second sense amplifier driving circuit 220_1.

As described above, according to the first exemplary embodiment, the plurality of sense amplifier circuit units 100_1 to 100_2 and the sense amplifier driving circuit unit 200_1 included in the individual sensing units share the pull-up voltage supply line RTO_1 and the pull-down voltage supply line SB_1. In addition, the layout required to form a pull-up voltage supply line and a pull-down voltage supply line can be minimized.

However, in the first exemplary embodiment of the present invention, leakage current may be generated from the sense amplifier 110_1 to the sense amplifier 110_2, so that data may not be accurately sensed and amplified.

For example, it is assumed that data 0 is sensed by the bit line BL of the sense amplifier 110_1 and data 1 is sensed by the bit line BL of the sense amplifier 110_2. In this case, the node SA_1 and the node SAB_1 of the sense amplifier 110_1 are precharged to the precharge voltage VBLP level, and when data 0 is sensed through the bit line BL, the node is formed by charge sharing with the bit line BL. The voltage level of SA_1 is lowered to VBLP-ΔV, and the voltage level of node SAB_1 is raised to VBLP + ΔV. As a result, the NMOS transistor N1_1 is turned on by the voltage at the node SAB_1.

On the other hand, the pull-down voltage supply line SB_1 is precharged to the precharge voltage VBLP level similarly to the bit lines BL and / BL, and is connected to the node SA_1 as the NMOS transistor N1_1 is turned on, and as a result, the pull-down voltage supply line SB The voltage level is lowered to VBLP-ΔV '.

In the first embodiment of the present invention, since the sense amplifier 110_1 and the sense amplifier 110_2 share the pull-down voltage supply line SB_1, the voltage level of the pull-down voltage supply line SB on the sense amplifier 110_2 side is also VBLP-ΔV. Is lowered to '.

When the voltage level of the node SAB_2 is lowered to VBLP-ΔV ', the voltage difference larger than the threshold voltage of the NMOS transistors N1_2 and N2_2 is not obtained because the precharge voltage VBLP level cannot be maintained at the moment when data 1 is sensed, so that the NMOS transistor N1_2, N2_2 does not work. Therefore, the sensing operation of the sense amplifier 110_2 may not be performed correctly.

4 is a circuit diagram illustrating an integrated circuit array according to a second exemplary embodiment of the present invention.

Referring to FIG. 4, the integrated circuit array according to the second embodiment of the present invention may prevent a malfunction that may occur in accordance with the first embodiment of the present invention.

The integrated circuit array according to the second embodiment of the present invention includes a plurality of sensing units 10_1 to 10_M. Each of the sensing units includes one sense amplifier circuit unit and one sense amplifier driving circuit unit.

In FIG. 4, the integrated circuit array according to the second embodiment of the present invention illustrates a case in which one sense amplifier driving circuit unit 200_1 is connected to one sense amplifier circuit unit 100_1 in each sensing unit.

In this case, the sense amplifier driving circuit unit 200_1 supplies the power supply voltage to the sense amplifier circuit unit 100_1 only through the pull-up voltage supply line RTO_1 and the pull-down voltage supply line SB_1.

Similarly, the sense amplifier driving circuit unit 200_2 supplies the power supply voltage to the sense amplifier circuit unit 100_2 only through the pull-up voltage supply line RTO_2 and the pull-down voltage supply line SB_2.

That is, the voltage supply lines RTO and SB are not shared between the sense amplifier circuit unit 100_1 and the sense amplifier circuit unit 100_2.

Specifically, in the integrated circuit array according to the second embodiment of the present invention, the sense amplifier driving circuit unit 200_1 supplies the pull-up voltage or the pull-down voltage only to the sense amplifier circuit unit 100_1 through the pull-up voltage supply line RTO_1. The sense amplifier driving circuit unit 200_2 supplies a pull up voltage or a pull down voltage to the sense amplifier circuit unit 100_2 through a separate pull-up voltage supply line RTO_2.

In this case, even if a leakage current occurs through the pull-up voltage supply line RTO_1 or the pull-down voltage supply line SB_1 in the sense amplifier 110_1, the leakage current is blocked from being transferred to the sense amplifier 110_2.

Therefore, the possibility of influencing data sensing of the other sense amplifiers by the leakage current generated in one sense amplifier is reduced, and thus, there is an advantage that accurate data sensing is possible.

As described above, in the integrated circuit array of the present invention, the individual sensing unit i) includes a plurality of sense amplifier circuit units and one sense amplifier driving circuit unit, and one sense amplifier driving circuit unit is identical to the plurality of sense amplifier circuit units. Voltage may be supplied through the voltage supply line RTO and the pull-down voltage supply line SB, and ii) includes one sense amplifier circuit portion and one sense amplifier driving circuit portion, and one sense amplifier driving circuit portion only in one sense amplifier circuit portion. Voltage can also be supplied through independent pull-up voltage supply lines RTO and pull-down voltage supply lines SB.

In addition, the integrated circuit array according to the present invention may be applied to all kinds of semiconductor memory devices for amplifying a current sensed through a bit line. For example, the integrated circuit array according to the present invention may be applied to various semiconductor memory devices such as dynamic random access memory (DRAM), phase change RAM (PCRAM), ferroelectric RAM (FRAM), and the like. It is not limited to that.

1 is a circuit diagram of an integrated circuit according to the present invention. FIG. 2 is a block diagram illustrating a sense amplifier according to the present invention.

2 is a timing diagram illustrating a data sensing operation by an integrated circuit according to the present invention.

3 is a circuit diagram illustrating an integrated circuit array according to a first embodiment of the present invention.

4 is a circuit diagram illustrating an integrated circuit array according to a second exemplary embodiment of the present invention.

Claims (20)

A first sensing unit sensing a current applied from at least one first memory cell; And A second sensing unit configured to sense current applied from at least one second memory cell, The first sensing unit A first sense amplifier circuit unit for amplifying a current applied from the at least one first memory cell through a first pair of bit lines; A first sense amplifier driving circuit unit for driving a power supply voltage required for the amplifying operation of the first sense amplifier circuit unit, and A first voltage supply line connecting the first sense amplifier circuit unit and the first sense amplifier driving circuit unit to supply the power voltage; The second sensing unit A second sense amplifier circuit unit for amplifying a current applied from the at least one second memory cell through a second pair of bit lines; A second sense amplifier driving circuit unit for driving a power supply voltage required for the amplifying operation of the second sense amplifier circuit unit; and And a second voltage supply line connecting the second sense amplifier circuit portion and the second sense amplifier driving circuit portion to supply the power supply voltage. The method according to claim 1, The first sense amplifier circuit unit And a bit line equalization circuit that equalizes the first bit line pair to the same voltage level. The method according to claim 2, The bit line equalization circuit And equalizing the first pair of bit lines when a bit line equalization signal is enabled. The method according to claim 1, The first sense amplifier circuit unit And a bit line blocking circuit, each disconnecting the first bit line pair when the bit line blocking signal is enabled. The method according to claim 1, The first and second sense amplifier circuit unit And a bit line precharge circuit for precharging the first and second bit line pairs when a bit line precharge signal is enabled. The method according to claim 5, And the bit line precharge circuit precharges the first and second bit line pairs to the same voltage level. The method according to claim 1, The first sense amplifier driving circuit unit A first sense amplifier driving circuit driving the power supply voltage supplied to the first sense amplifier circuit unit at a first voltage level, and then driving at a second voltage level; And A second sense amplifier driving circuit for driving the power supply voltage supplied to the sense amplifier circuit to a third voltage level; And wherein the first voltage level is higher than the second voltage level and the second voltage level is higher than the third voltage level. The method of claim 7, The first voltage supply line A pull-up voltage supply line connecting the first sense amplifier driving circuit and the first sense amplifier circuit part; And And a pull-down voltage supply line connecting the second sense amplifier driving circuit and the first sense amplifier circuit. The method according to claim 8, The first sense amplifier driving circuit unit And an equalization circuit for equalizing the pull-up voltage supply line and the pull-down voltage supply line to the same voltage level. The method according to claim 8, The first sense amplifier driving circuit unit And a precharge circuit for precharging said pull-up voltage supply line and said pull-down voltage supply line. A plurality of sensing units configured to sense a current applied through the bit line pair from the memory cell, Each of the plurality of sensing units A plurality of sense amplifier circuits for amplifying a current applied through the pair of bit lines; A sense amplifier driving circuit unit for driving a power supply voltage required for the amplifying operation of the sense amplifier circuit unit; And And a voltage supply line connecting the plurality of sense amplifier circuit units and the sense amplifier driving circuit unit to supply the power voltage. The method of claim 11, The sense amplifier circuit unit And a bit line equalization circuit that equalizes the bit line pairs to the same voltage level. The method according to claim 12, The bit line equalization circuit And equalizing the pair of bit lines when a bit line equalization signal is enabled. The method of claim 11, The sense amplifier circuit unit And a bit line blocking circuit that disconnects the bit line pair when the bit line blocking signal is enabled. The method of claim 11, The sense amplifier circuit unit And a bit line precharge circuit for precharging the bit line pair when a bit line precharge signal is enabled. 16. The method of claim 15, And the bit line precharge circuit precharges the pair of bit lines to the same voltage level. The method of claim 11, The sense amplifier driving circuit unit A first sense amplifier driving circuit driving the power supply voltage supplied to the sense amplifier circuit unit at a first voltage level, and then driving at a second voltage level; And A second sense amplifier driving circuit for driving the power supply voltage supplied to the sense amplifier circuit to a third voltage level; And wherein the first voltage level is higher than the second voltage level and the second voltage level is higher than the third voltage level. The method according to claim 17, The voltage supply line A first voltage supply line connecting the first sense amplifier driving circuit and the sense amplifier circuit part; And And a second voltage supply line connecting the second sense amplifier driving circuit and the sense amplifier circuit. 19. The method of claim 18, The sense amplifier driving circuit unit And an equalization circuit for equalizing the first voltage supply line and the second voltage supply line to the same voltage level. 19. The method of claim 18, The sense amplifier driving circuit unit And a precharge circuit for precharging the first voltage supply line and the second voltage supply line.

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