KR20110077264A - Thin film transistor and fabricating method therof - Google Patents

Thin film transistor and fabricating method therof Download PDF

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Publication number
KR20110077264A
KR20110077264A KR1020090133777A KR20090133777A KR20110077264A KR 20110077264 A KR20110077264 A KR 20110077264A KR 1020090133777 A KR1020090133777 A KR 1020090133777A KR 20090133777 A KR20090133777 A KR 20090133777A KR 20110077264 A KR20110077264 A KR 20110077264A
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South Korea
Prior art keywords
layer
source
ohmic contact
thin film
forming
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KR1020090133777A
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Korean (ko)
Inventor
김성기
이홍구
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엘지디스플레이 주식회사
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Priority to KR1020090133777A priority Critical patent/KR20110077264A/en
Publication of KR20110077264A publication Critical patent/KR20110077264A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: A thin film transistor and a manufacturing method thereof are provided to reduce process costs by pattering an ohmic contact layer with a wet etching process instead of a dry etching process. CONSTITUTION: A gate electrode(102) is formed on a substrate(101). A gate insulating layer is formed on the substrate with the gate electrode. An active layer(104) is formed on a gate insulation layer(103) and is made of amorphous silicon. A source electrode(106) and a drain electrode(107) are formed on the active layer with a preset space. An ohmic contact layer(105) is formed between the active layer and the source/drain electrodes and is made of metal oxide.

Description

Thin film transistor and its manufacturing method {THIN FILM TRANSISTOR AND FABRICATING METHOD THEROF}

The present invention relates to a thin film transistor and a method for manufacturing the same, wherein when the active layer is made of amorphous silicon, by forming an ohmic contact layer made of metal oxide, a thin film transistor which can reduce the process cost and minimize the thickness of the active layer; The manufacturing method is related.

BACKGROUND ART In general, liquid crystal display devices have tended to be gradually widened due to their light weight, thinness, and low power consumption. Accordingly, the liquid crystal display device is widely used as a portable computer such as a notebook PC, office automation equipment, audio / video equipment, and the like.

In general, a liquid crystal display device displays a desired image on a screen by controlling the amount of light passing through the liquid crystal layer according to image signals applied to a plurality of control switching elements arranged in a matrix.

Amorphous silicon thin film transistors (a-Si TFTs) are mainly used as the control switching element. As described above, a liquid crystal display device employing an amorphous silicon thin film transistor as a switching element for controlling will be described. Is the same as

As shown in FIG. 1, a conventional liquid crystal display device includes a first substrate 1 as a thin film transistor substrate and a second substrate 2 as a color filter substrate.

The gate line 3 and the data line 4 intersect each other on the first substrate 1 to define a plurality of pixels, and the gate line 3 and the data line 4 of each pixel cross each other. A thin film transistor 5 is formed in the region, and a pixel electrode 6 connected to the thin film transistor 5 is formed in each pixel.

The sub color filter 7 is formed on a region corresponding to the pixel defined on the first substrate 1 on the second substrate 2, and a black matrix 8 is formed on the boundary of the sub color filter 7. The common electrode 9 for driving the liquid crystal layer 10 is formed together with the pixel electrode 6 on the first substrate 1.

In FIG. 2, a cross-sectional view of the thin film transistor 5 is illustrated in detail. Referring to FIG. 2, the thin film transistor 5 includes a gate electrode 5a and a gate formed on the gate electrode 5a. An insulating film 5b, an active layer 5c and an ohmic contact layer 5d formed on the gate insulating film 5b, and source / drain electrodes 5e and 5f formed on the ohmic contact layer 5d. It is configured by. In this case, the active layer 5c is made of amorphous silicon (a-Si: H), and the ohmic contact layer 5d is made of amorphous silicon (n + a-Si: H) doped with impurities.

The thin film transistor 5 having the above structure is a metal (eg, molybdenum) that is a material of the source / drain electrodes 5e and 5f as compared to the work function of silicon, which is the material of the active layer 5c. The ohmic contact layer made of amorphous silicon doped with impurities between the active layer 5c and the source / drain electrodes 5e and 5f in order to improve contact characteristics because ohmic contact is impossible due to the large work function of. Although 5d is formed, there is a disadvantage in that a dry etching process for removing a region corresponding to the source / drain electrodes 5e and 5f in the ohmic contact layer 5d is required during the manufacturing process. In addition, the active layer 5c must be sufficiently thick to secure a process margin during dry etching to remove a region corresponding to the source / drain electrodes 5e and 5f among the ohmic contact layers 5d. Disadvantages There has been.

In order to solve the above disadvantages, a structure in which an etch stopper (E / S) is formed has been devised, but a number of masks are required in the manufacturing process to increase manufacturing costs.

Accordingly, an object of the present invention is to provide a thin film transistor and a method of manufacturing the same, which can achieve an ohmic contact between the actives and the source / drain electrodes and minimize the thickness of the active layer. To provide.

A thin film transistor according to a preferred embodiment of the present invention for achieving the above object, the gate electrode formed on a substrate; A gate insulating film formed on the substrate on which the gate electrode is formed; An active layer formed on the gate insulating layer and made of amorphous silicon; Source / drain electrodes formed on the active layer at predetermined intervals from each other; And an ohmic contact layer formed between the active layer and the source / drain electrodes and made of a metal oxide. And a control unit.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor, including: forming a gate electrode on a substrate; Forming a gate insulating film on the substrate on which the gate electrode is formed; Forming an active layer of amorphous silicon on the gate insulating film; And forming an ohmic contact layer made of a metal oxide on the active layer, and forming a source / drain electrode overlapping the ohmic contact layer. Characterized in that comprises a.

According to the present invention having the above-described configuration and manufacturing method, by forming a ohmic contact layer between the active layer and the source / drain electrodes with a metal oxide, the process of patterning the ohmic contact layer is performed by wet etching instead of dry etching. This can be achieved through the use of relatively inexpensive wet etching equipment, thereby reducing the process cost.

In addition, the etchant used for the wet etching has a large etching selectivity between the metal oxide and silicon, so that only the metal oxide is selectively removed when the etching is performed using the etchant, and the active layer is not removed. It can form, and there exists an effect which improves mobility.

Hereinafter, a thin film transistor and a method of manufacturing the same according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a configuration of a thin film transistor according to a preferred embodiment of the present invention will be described with reference to FIG. 3.

As shown in FIG. 3, a thin film transistor according to a preferred embodiment of the present invention includes a gate electrode 102 formed on a substrate 101; A gate insulating film 103 formed on the substrate 101 on which the gate electrode 102 is formed; An active layer 104 formed on the gate insulating layer 103 and made of amorphous silicon; Source / drain electrodes 106 and 107 formed on the active layer 104 at predetermined intervals from each other; An ohmic contact layer 105 formed between the active layer 104 and the source / drain electrodes 106 and 107 and made of a metal oxide; .

The gate electrode 102 formed on the substrate 101 is made of a conductive metal such as aluminum (Al) or molybdenum (Mo), and is formed of a single layer or a double layer.

The gate insulating layer 103 formed on the substrate 101 on which the gate electrode 102 is formed is formed of an inorganic insulating material such as silicon nitride (SiN X ) and silicon oxide (SiO X ), and in some cases, benzocyclobutene ( It may be formed of an organic insulating material such as BCB).

The active layer 104 formed on the gate insulating layer 103 is made of amorphous silicon (a-Si: H), and the ohmic contact layer 105 formed on the active layer 104 is made of metal oxide.

The metal oxide forming the ohmic contact layer 105 is preferably a material having a work function smaller than that of silicon (Si). For example, zinc oxide doped with aluminum (ZnO: Al) and Cr 3 Si− SiO 2 .

The active layer 104 may be formed to a thin thickness of 200 [Å] or more and 2500 [Å] or less, which is used in a wet etching process of patterning an ohmic contact layer 105 made of a metal oxide. This is because the active layer 104 does not react with the etchant so that the active layer 104 can be formed to a minimum thickness without a process margin. Detailed description thereof will be given in the following description of the method for manufacturing the thin film transistor according to the preferred embodiment of the present invention.

The source electrode 106 and the drain electrode 107 formed on the active layer 104 at predetermined intervals from each other are made of a conductive metal such as aluminum (Al) or molybdenum (Mo), and are formed of a single layer or a double layer. do.

Hereinafter, a method of manufacturing a thin film transistor according to a preferred embodiment of the present invention will be described with reference to FIGS. 4A to 4G.

First, as shown in FIG. 4A, the gate electrode 102 is formed on the substrate 101.

That is, a first mask (not shown) in which a gate forming metal layer (not shown) and a first photoresist layer (not shown) are sequentially formed on the substrate 101, and a blocking region is formed in a region where the gate electrode 102 is to be formed. After performing photolithography on the first photoresist layer to form a first photoresist pattern (not shown), the gate forming metal layer is selectively removed using the first photoresist pattern to form the gate electrode 102. Then, the first photosensitive film pattern is removed.

In this case, the gate forming metal layer may be made of a conductive metal such as aluminum (Al) or molybdenum (Mo), but may be formed as a single layer or a double layer, and the first mask may be formed of an exposed region according to the type of the first photoresist layer. The unexposed areas could be reversed.

Next, as shown in FIG. 4B, a gate insulating film 103 is formed on the substrate 101 on which the gate electrode 102 is formed.

In this case, the gate insulating layer 103 may be formed of an inorganic insulating material such as silicon nitride (SiN X ) and silicon oxide (SiO X ), and may be formed of an organic insulating material such as benzocyclobutene (BCB) in some cases. .

Next, as shown in FIG. 4C, an active layer 104 made of amorphous silicon (a-Si: H) is formed on the gate insulating layer 103.

That is, an amorphous silicon (a-Si: H) layer (not shown) is formed on the gate insulating layer 103 using plasma chemical vapor deposition (PECVD), and a second photoresist layer (not shown) is formed on the amorphous silicon layer. After forming the photoresist layer using the second mask (not shown) in which the blocking region is formed in the region where the active layer 104 is to be formed, the second photoresist layer pattern (not shown) is formed. The amorphous silicon layer is selectively removed using the second photoresist pattern to form an active layer 104, and the second photoresist pattern is removed.

At this time, the thickness of the active layer 104 is formed to a thin thickness of 200 [Å] or more and 2500 [Å] or less.

Next, as shown in FIG. 4G, an ohmic contact layer 105 made of a metal oxide is formed on the active layer 104, and the source / drain electrodes 106 and 107 overlapping the ohmic contact layer 105. To form.

That is, as shown in FIG. 4D, the metal oxide layer 201 and the source / drain forming metal layer 202 are formed on the substrate 101 on which the active layer 104 is formed by using a sputter. The third photoresist layer 203 is sequentially formed on the source / drain forming metal layer 202 and the third mask 204 is formed by using a third mask 204 in which a blocking region is formed in a region where the source / drain electrodes 106 and 107 are to be formed. After performing photolithography on the photoresist 203 to form a third photoresist pattern 203a as shown in FIG. 4E, a wet etching using the third photoresist pattern 203a is performed to perform a source. The drain / drain metal layer 202 and the metal oxide layer 201 are selectively removed to form the source / drain electrodes 106 and 107 and the ohmic contact layer 105 as shown in FIG. 4F. As shown, the third photoresist pattern 203a is removed.

At this time, the metal oxide layer 201 is preferably made of a material having a work function smaller than the work function of silicon (Si), for example, zinc oxide doped with aluminum (ZnO: Al) and Cr 3 Si-SiO There are two .

A method for removing the source / drain formation metal layer 202 when wet etching the source / drain formation metal layer 202 and the metal oxide layer 201 using the third photoresist pattern 203a is performed. The etchant for removing the cheat and the metal oxide layer 201 may be different or the same depending on the type of material forming the source / drain forming metal layer 202 and the type of material forming the metal oxide layer 201.

As described above, the dry etching process is performed by patterning the ohmic contact layer 105 by forming the ohmic contact layer 105 positioned between the active layer and the source / drain electrodes 106 and 107 with a metal oxide. Because it can be done through wet etching, the process cost is reduced due to the use of relatively inexpensive wet etching equipment.

In addition, since the etchant used for the wet etching of the metal oxide layer 201 has a large etching selectivity between the metal oxide and silicon, when the wet etching is performed using the etchant, only the metal oxide layer 201 is removed. Since the active layer 104 is not removed, the active layer 104 can be formed to a minimum thickness, that is, 200 [Å] or more and 2500 [Å] or less without a process margin, thereby improving the mobility of the thin film transistor element.

1 is an exploded perspective view briefly showing a conventional general liquid crystal display.

FIG. 2 is a cross-sectional view illustrating the thin film transistor of FIG. 1 in detail. FIG.

3 is a cross-sectional view showing a thin film transistor according to a preferred embodiment of the present invention.

4A-4G are cross-sectional views illustrating a number of steps performed to fabricate the thin film transistor of FIG.

** Description of the symbols for the main parts of the drawings **

101 substrate 102 gate electrode

103 gate insulating film 104 active layer

105: ohmic contact layer 106: source electrode

107: drain electrode 201: metal oxide layer

202: source / drain formation layer 203: third photosensitive film

203a: third photosensitive film pattern 204: third mask

Claims (14)

A gate electrode formed on the substrate; A gate insulating film formed on the substrate on which the gate electrode is formed; An active layer formed on the gate insulating layer and made of amorphous silicon; Source / drain electrodes formed on the active layer at predetermined intervals from each other; And An ohmic contact layer formed between the active layer and the source / drain electrodes and formed of a metal oxide; A thin film transistor comprising a. The thin film transistor of claim 1, wherein the ohmic contact layer is formed of a metal oxide having a work function smaller than that of silicon. The thin film transistor of claim 2, wherein the ohmic contact layer is formed of zinc oxide (ZnO: Al) doped with aluminum. The thin film transistor of claim 2, wherein the ohmic contact layer is made of Cr 3 Si—SiO 2 . The thin film transistor according to claim 1, wherein the active layer has a thickness of 200 [kW] or more and 2500 [kW]. Forming a gate electrode over the substrate; Forming a gate insulating film on the substrate on which the gate electrode is formed; Forming an active layer of amorphous silicon on the gate insulating film; And Forming an ohmic contact layer made of a metal oxide on the active layer, and forming a source / drain electrode overlapping the ohmic contact layer; A thin film transistor manufacturing method comprising a. The method of claim 6, wherein the ohmic contact layer is formed of a metal oxide having a work function smaller than that of silicon. The method of claim 7, wherein the ohmic contact layer is formed of zinc oxide (ZnO: Al) doped with aluminum. The method of claim 7, wherein the ohmic contact layer is made of Cr 3 Si—SiO 2 . 7. The method of manufacturing a thin film transistor according to claim 6, wherein the thickness of said active layer is 200 [mW] or more and 2500 [mW]. The method of claim 6, wherein the forming of the ohmic contact layer and the source / drain electrode comprises: Sequentially forming a metal oxide layer, a source / drain forming metal layer, and a photoresist layer on the substrate on which the active layer is formed; Forming a photoresist pattern by performing photolithography using a mask having a blocking region in a region corresponding to a source / drain electrode to be formed later; Selectively removing the source / drain forming metal layer and the metal oxide layer by using the photoresist pattern to form a source / drain electrode and an ohmic contact layer; And Removing the photoresist pattern; A thin film transistor manufacturing method comprising a. The method of claim 11, wherein the forming of the source / drain electrode and the ohmic contact layer by selectively removing the source / drain forming metal layer and the metal oxide layer using the photoresist pattern is performed by wet etching. The thin film transistor manufacturing method characterized by the above-mentioned. 13. The method of claim 12, wherein the etchant for removing the metal layer for source / drain formation and the etchant for removing the metal oxide layer in the wet etching are different. The method of claim 12, wherein the etchant for removing the source / drain forming metal layer and the etchant for removing the metal oxide layer are the same in the wet etching using the photosensitive film pattern.
KR1020090133777A 2009-12-30 2009-12-30 Thin film transistor and fabricating method therof KR20110077264A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104966697A (en) * 2015-07-14 2015-10-07 深圳市华星光电技术有限公司 TFT substrate structure and manufacturing method thereof
CN105070722A (en) * 2015-07-14 2015-11-18 深圳市华星光电技术有限公司 TFT substrate structure and manufacturing method thereof
WO2022120746A1 (en) * 2020-12-10 2022-06-16 昆山龙腾光电股份有限公司 Array substrate and manufacturing method therefor, and display panel
WO2024085528A1 (en) * 2022-10-20 2024-04-25 주성엔지니어링(주) Thin-film transistor and manufacturing method therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104966697A (en) * 2015-07-14 2015-10-07 深圳市华星光电技术有限公司 TFT substrate structure and manufacturing method thereof
CN105070722A (en) * 2015-07-14 2015-11-18 深圳市华星光电技术有限公司 TFT substrate structure and manufacturing method thereof
WO2017008334A1 (en) * 2015-07-14 2017-01-19 深圳市华星光电技术有限公司 Tft substrate structure and manufacturing method therefor
WO2022120746A1 (en) * 2020-12-10 2022-06-16 昆山龙腾光电股份有限公司 Array substrate and manufacturing method therefor, and display panel
WO2024085528A1 (en) * 2022-10-20 2024-04-25 주성엔지니어링(주) Thin-film transistor and manufacturing method therefor

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