KR20110076618A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A test pattern of a semiconductor device and an analyzing method thereof are provided to accurately measure the property of a semiconductor device capacitor. CONSTITUTION: An analyzing method of a test pattern of a semiconductor device comprises the following steps: forming a semiconductor device capacitor(100) on a substrate; forming plural GND pads(10,20,30,40) on the substrate for measuring the test values of the capacitor; connecting the GND pads using plural GND lines; locating signal pads(50,60) around the capacitor; connecting the capacitor and the signal pads using bridges(55,65,75,85); and installing dummy resistant bodies(70,80) on the bridges.

Description

Test pattern of semiconductor device and analysis method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

The embodiment relates to a test pattern of a semiconductor device and a method of analyzing the same.

With the development of high semiconductor integration technology, a technology for forming a capacitor element on a substrate has been developed. As the semiconductor device type capacitor, PIP (Polysilicon / Insulator / Polysili con) and MIM (Metal / Insulator / Metal) types are mainly used.

In order to measure the high frequency region of the capacitor formed on the semiconductor substrate, after performing the accurate calibration (RF Calibration and PAD De-embedding) of the measuring equipment of the high frequency region, the quality factor (Q-factor) can be extracted from the measurement result. Can be. The quality factor is expressed as the ratio of resistive components in which the pure capacitance of the capacitor is parasitic.

However, since the parasitic components (parasitic resistance, parasitic inductance, parasitic capacitor, etc.) other than the capacitor component of the capacitor are not accurately measured or have a very small value, there is a problem that the quality factor of the capacitor is incorrectly measured.

The embodiment provides a test pattern of a semiconductor device and an analysis method thereof for enabling accurate measurement of characteristics of a semiconductor device capacitor.

The test pattern of the semiconductor device according to the embodiment, the semiconductor device capacitor formed on the substrate; A plurality of GND pads formed on the substrate for measuring test values of the capacitors; A plurality of GND lines connecting between the GND pads; A signal pad disposed in the vicinity of the capacitor; A bridge connecting the capacitor and the signal pad; And a dummy resistor interposed in the bridge and having a relatively higher resistance value than the capacitor.

An analysis method of a test pattern of a semiconductor device according to an embodiment may include: measuring resistance of the capacitor and the dummy resistor using the test pattern of the semiconductor device of claim 1; Calculating the resistance of the capacitor by subtracting the resistance value of the dummy resistor from the measured resistance.

According to the embodiment, it is possible to provide a test pattern of a semiconductor device and an analysis method thereof for enabling accurate measurement of characteristics of a semiconductor device capacitor.

A test pattern and a method of analyzing the semiconductor device according to the embodiments will be described in detail with reference to the accompanying drawings. Hereinafter, when referred to as "first", "second", etc., this is not intended to limit the members but to show that the members are divided and have at least two. Thus, when referred to as "first", "second", etc., it is apparent that a plurality of members are provided, and each member may be used selectively or interchangeably. In addition, the size (dimensions) of each component of the accompanying drawings are shown in an enlarged manner to help understanding of the invention, the ratio of the dimensions of each of the illustrated components may be different from the ratio of the actual dimensions. In addition, not all components shown in the drawings are necessarily included or limited to the present invention, and components other than the essential features of the present invention may be added or deleted. In the description of an embodiment, each layer (film), region, pattern, or structure is formed “on” or “under” a substrate, each layer (film), region, pad, or pattern. In the case where it is described as "to", "on" and "under" include both "directly" or "indirectly" formed. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings. In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

1 is a plan view of a test pattern of a semiconductor device according to an embodiment.

The test pattern of the semiconductor device according to the embodiment is for accurately measuring a quality factor, which is one of the high frequency characteristics of the semiconductor capacitor device. The semiconductor capacitor device may include a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, a polysilicon-insulator-polysilicon (PIP) capacitor, or the like.

In the present embodiment, the capacitor 100 to be measured is formed of a lower electrode using a metal, an insulator layer is formed thereon, and an upper electrode is formed again using a metal on the insulator layer. A case of the MIM capacitor of the type will be described.

The test pattern according to the embodiment for measuring the capacitor 100 includes a first upper GND pad 10 and a second upper GND pad 20, an upper GND line 15 connecting them, and a second lower GND pad. 30 and the first lower GND pad 40, the lower GND line 35 connecting them, the first signal pad 50 and the second signal pad 60 formed on both sides of the capacitor 100, Bridges 55, 65, 75, and 85 connecting the signal pads 50 and 60 and the capacitor 100, and a first dummy resistor 70 connected between the bridges 55, 65, 75 and 85, respectively. And a second dummy resistor 80.

The upper and lower GND pads 10, 20, 30, and 40 are GND pads for measurement, and the signal pads 50 and 60 are pads for high frequency signal input and output.

The first upper GND pad 10 and the second upper GND pad 20 and the upper GND line 15 connecting them may be connected to a metal layer by a semiconductor process.

The first lower GND pad 40 and the second lower GND pad 30 and the lower GND line 35 connecting them may be connected to a metal layer by a semiconductor process.

Here, the upper pads 10 and 20 and the line 15 and the lower pads 30 and 40 and line 35 are electrically separated from each other.

In addition, the upper pads 10 and 20 and the line 15 and the lower pads 30 and 40 and the line 35 may include the signal pads 50 and 60 and the bridge formed on both sides of the capacitor 100. (55, 65, 75, 85) and dummy resistors 70, 80), but are electrically isolated.

The first signal pad 50 and the second signal pad 60 are respectively connected to the left and right sides of the capacitor 100. The first signal pad 50 operates as an RF input port through which an RF signal is input. The second signal pad 60 acts as an RF output port as an RF signal port.

The first dummy resistor 70 is connected to the first bridge 55 and the second bridge 75 connecting the first signal pad 50 and the capacitor 100. A second dummy resistor 80 is connected to the third bridge 65 and the fourth bridge 85 connecting the second signal pad 60 and the capacitor 100.

The first dummy resistor 70 is an resistor having an electrical resistance component and is electrically connected to the first bridge 55 and the second bridge 75. The first dummy resistor 70 has a high resistance that is approximately 25 to 100% or more greater than the resistance of the capacitor 100. The first dummy resistor 70 may be formed of a thin film of NiCr or TaN alloy deposited through evaporation and sputtering. In addition, the first dummy resistor 70 may be formed of a p + poly silicon thin film and a Phosphorus n + poly silicon thin film (Thin film) on which Boron is deposited through a semiconductor process impurity implantation (Ion implant).

The second dummy resistor 80 is an resistor having an electrical resistance component and is electrically connected to the third bridge 65 and the fourth bridge 85. The second dummy resistor 80 has a high resistance that is approximately 25 to 100% or more greater than that of the capacitor 100. The second dummy resistor 80 is also formed of a thin film of NiCr or TaN alloy resistor deposited through semiconductor evaporation, sputtering, or boron deposited through a semiconductor process impurity implantation. It may be formed of a p + poly silicon thin film and a Phosphorus n + poly silicon thin film (Thin film).

In this configuration, when a high frequency signal is input and output to the first signal pad 50 and the second signal pad 60 to measure the quality of the capacitor 100, the first dummy having a relatively larger resistance than the capacitor 100. The resistance value to which the resistor 70 and the second dummy resistor 80 are added can be obtained. This is because the parasitic resistance of the capacitor 100 is measured to be small because the equivalent resistance of the conventional capacitor 100 has an extremely small value (0.1 ohm or less) than the characteristic impedance of 50 ohm for RF measurement. This is to prevent the occurrence. The parasitic resistance inherent in the capacitor 100 can be determined by adding the high resistances 70 and 80 which already know the resistance value and measuring the resistance value, and then electrically removing the resistance value by the high resistances 70 and 80. have. Here, the resistance value of the high resistors 70 and 80 may be set to a value of 25 to 100% or more than the resistance value of the capacitor 100 to improve the accuracy of the measurement when measuring the resistance value. By measuring the accurate parasitic resistance measured according to this configuration, the Q-factor of the capacitor can also be accurately determined.

FIG. 2 is an equivalent circuit diagram of the semiconductor device test pattern of FIG. 1.

The RF signal is input to the first signal pad 50 and the resistance and reactance generated when the RF signal is output to the second signal pad 60 through the capacitor 100 are displayed.

Cmim is a capacitor component of the capacitor 100, and R1 and R2 are parasitic resistance components. L1 and L2 are parasitic inductance components. C1 and C2 are grounds of the capacitor 100 and parasitic capacitor components generated in the capacitor 100, and PAD1 and PAD2 are components of the signal pads 50 and 60.

3 and 4 are plan views for analyzing a test pattern according to an embodiment. FIG. 3 is a view of an open circuit except for the capacitor 100. FIG. 4 is a view showing a second bridge 75 and a fourth bridge. This is a diagram of a Thru circuit without the space between (85).

3 is a pattern for a de-embedding process for electrically removing the first dummy resistor 70, the resistor and the second dummy resistor 80, and the dummy resistor 70 from which the capacitor 100 is removed. , Fig. 80 shows a pattern of an open circuit for PAD de-embedding.

By opening the configuration of the signal pads 50 and 60 connected to both sides of the capacitor 100 mutually, the parasitic capacitance of the first signal pad 50 and the bridges 55 and 75 to which the first dummy resistor 70 is connected The parasitic capacitances of the second signal pad 60 and the bridges 65 and 85 to which the second dummy resistor 80 is connected may be extracted and removed.

The first signal pad 50, the first bridge 55, the first dummy resistor 70, the second signal pad 60, and the third bridge 65, which are parts of the capacitor 100 except for the parasitic capacitor that the capacitor 100 has, are included. The second dummy resistor 80 is to remove the additional parasitic capacitor generated from the fourth bridge (85).

4 is a pattern for a de-embedding process for electrically removing the first dummy resistor 70, the resistor, and the second dummy resistor 80. The capacitor 100 is removed and the second bridge ( 75 shows a pattern of a through circuit electrically connected to the first dummy resistor 70.

Through the configuration of the signal pads 50 and 60 connected to both sides of the capacitor 100, the first signal pads 50 and the bridges 55 and 75 of the first dummy resistor 70 are connected to each other. The parasitic capacitance and the parasitic capacitance of the second signal pad 60 and the bridges 65 and 85 to which the second dummy resistor 80 is connected may be extracted and removed.

The first signal pad 50, the first bridge 55, the first dummy resistor 70, the second bridge 75, and the second signal, which are parts of the capacitor 100 except for the parasitic resistance component and the parasitic inductance, which are owned by the capacitor 100. To remove additional parasitic resistance components and parasitic inductance components generated in the pad 60, the third bridge 65, the second dummy resistor 80, and the fourth bridge 85.

5 and 6 are graphs of test results of semiconductor devices. In the graphs of FIGS. 5 and 6, the solid line represents the resistance value and the Q value of the capacitor measured without the dummy resistors 70 and 80 connected, and the dotted line connects the dummy resistors 70 and 80 according to the embodiment. It is measured after.

The present embodiment has a main purpose when the capacitor 100 is implemented on a semiconductor substrate and then evaluated in a high frequency region to identify more accurate device characteristics. In evaluating the capacitor 100 according to the embodiment, the equivalent resistance of the capacitor 100 is extremely small (˜0.1 ohm or less), and thus the parasitic resistance of the original capacitor 100 is smaller than 50 ohm characteristic impedance for RF measurement. This is measured small. Therefore, the parasitic resistance value of the capacitor 100 itself is removed by removing the measurement error by attaching the dummy resistors 70 and 80, which are approximately 25 to 100% or more higher than the original resistance, to the MIM capacitor 100. I can figure it out. In addition, it is possible to accurately determine the Q-factor of the capacitor 100 through the accurate measurement of the parasitic resistance value.

As shown in FIG. 5 and FIG. 6, it can be confirmed that the resistance value and the Q value measured after connecting the dummy resistors 70 and 80 are more reliable.

As described above, according to the embodiment, a pattern for accurately measuring a capacitor regardless of a natural uncertainty of a high frequency measuring device is used to remove a unique measurement pattern including a capacitor and unnecessary components of the measurement pattern. It is composed of a de-embedding pattern to obtain an accurate quality factor.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

In addition, the above description has been made with reference to the embodiment, which is merely an example, and is not intended to limit the present invention. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a plan view of a test pattern of a semiconductor device according to the embodiment.

FIG. 2 is an equivalent circuit diagram of the semiconductor device test pattern of FIG. 1. FIG.

3 and 4 are plan top views for test pattern analysis according to an embodiment.

5 and 6 are graphs of test results of semiconductor devices.

Claims (13)

A semiconductor device capacitor formed on the substrate; A plurality of GND pads formed on the substrate for measuring test values of the capacitors; A plurality of GND lines connecting between the GND pads; A signal pad disposed in the vicinity of the capacitor; A bridge connecting the capacitor and the signal pad; And A test pattern of a semiconductor device interposed in the bridge and including a dummy resistor having a relatively higher resistance value than the capacitor. The method of claim 1, The capacitor, A test pattern of a semiconductor device including at least one of a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, and a polysilicon-insulator-polysilicon (PIP) capacitor. The method of claim 1, The signal pad, A test pattern of a semiconductor device comprising an RF signal input pad and an RF signal output pad. The method of claim 3, The bridge, A test pattern of a semiconductor device comprising an input bridge and an output bridge connecting the capacitor and the signal pad. The method of claim 1, The dummy resistor is a test pattern of a semiconductor device interposed between the input bridge and the output bridge, respectively. The method of claim 1, The dummy resistor is a test pattern of a semiconductor device is set to a value of 25 ~ 100% or more than the resistance value of the capacitor. The method of claim 1, The dummy resistor includes at least one of a NiCr and a TaN alloy resistor thin film deposited through semiconductor evaporation and sputtering. The method of claim 1, The dummy resistor includes at least one of a p + poly silicon thin film and a Phosphorus n + poly silicon thin film in which boron is deposited through a semiconductor process impurity implantation (Ion implant). The method of claim 1, A test pattern of a semiconductor device from which the capacitor is removed for de-embedding to electrically remove the dummy resistor. The method of claim 1, A test pattern of a semiconductor device interconnecting a bridge for removing the capacitor and connecting the signal pad for de-embedding for electrically removing the dummy resistor. Measuring the resistance of the capacitor and the dummy resistor using the test pattern of the semiconductor device of claim 1; And calculating the resistance of the capacitor by subtracting the resistance value of the dummy resistor from the measured resistance. The method of claim 11, Calculating the resistance of the capacitor, The test pattern analysis method of claim 1, further comprising extracting and removing capacitance of an open circuit from which the capacitor is removed from the test pattern of the semiconductor device of claim 1. The method of claim 11, Calculating the resistance of the capacitor, The method of claim 1, further comprising extracting and removing the capacitor from the test pattern of the semiconductor device and extracting the resistance and inductance of a through circuit interconnecting the bridges connecting the signal pads. .

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