CN105653805A - Method for correcting back-end parasitic interconnection line model - Google Patents
Method for correcting back-end parasitic interconnection line model Download PDFInfo
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The invention relates to a method for correcting a back-end parasitic interconnection line model. The method comprises the steps that an annular oscillator circuit is designed, an MOS device test structure is designed, a mapping test is conducted on the MOS device, an MOS device Spice model is corrected, and chipset for an annular oscillator mapping test is selected based on the statistical property of test data of the MOS device; non-loaded and capacitor-loaded annular oscillators are tested to obtain oscillation frequency, and the oscillation frequency is converted into time delay of a single-stage inverter; linear fitting is conducted on time delay test data and the number of loads of the annular oscillators; non-loaded and different capacitor-loaded annular oscillators are simulated, the single-stage inverter time delay is obtained, linear fitting is conducted on simulation data and the number of loads of the annular oscillators, and relevant middle-way parasitic capacitance parameters are corrected based on a fitting result; back-end interconnection line parasitic capacitance type parameters are corrected based on the slope of the fitting result, and an ITF file is updated; capacitor-resistor-loaded annular oscillators are simulated, the back-end interconnection line parasitic resistor type parameters are corrected, and the ITF file is updated.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to a kind of method of road parasitism Interconnect model after correction.
Background technology
Integrated circuit diagram parasitic parameter extraction is the committed step of design and verification of IC, and the object of its extraction is broadly divided into two classes: one is for front-end process, identifies and extract parasitic active device that may be present in domain, such as parasitic MOSFET etc.; Another kind of, it is for backend process, identifies and extract the dead resistance of interconnection line equivalence, parasitic capacitance etc. in domain. Along with technology generations is constantly updated, in nanometer-grade IC, Interconnect Delay is gradually increased, and having exceeded semiconductor device time delay becomes and affect integrated circuit timing principal element. Therefore precisely matching multilayer interconnection wire delay is most important to the performance of the high-end chip of correct assessment, and the extraction accuracy of interconnection line parasitic parameter is then day by day crucial.
Can that accurately extract interconnection line parasitic parameter it is critical only that the technique profile information whether rationally determining interconnection line, and whether the ITF file namely used in parasitic parameter extraction process is enough accurate. In ITF file, comprise material and the geometry information of each metal level and each dielectric layer. Can comprise the material informations such as resistivity and a series of structural information for metal level, such as the thickness of metal level, the corner cut of trapezoid cross section, upper bottom is relative to the skew of layout drawing size, and the information such as the Changing Pattern that changes with metal level size of these information. The information such as each level of dielectric constant and thickness generally can include to(for) dielectric layer. Circuit designer can utilize the loading ITF files such as extraction tool such as Star-RC that circuit layout is carried out parasitic parameter extraction. So the determination of the foundation of Interconnect model i.e. ITF file. The namely correction to the technique profile information comprised in ITF file to the correction of Interconnect model.
Determine that the common practices of ITF file has non-electrical method and electrical method at present. As by diced chip, chip is done tem observation and directly obtains the geometry information of each metal level and dielectric layer, but sample selected by the undulatory property of technique is likely to be not located in goldendie (optimal chip), may not necessarily the general information of reacting metal line, cause model error. ITF file is determined, mainly according to the relational design parasitic capacitance resistance test structure between each technological parameter and parasitic capacitance resistance by electrical method. Such as, between interconnection line, parasitic capacitance is main with metal level dielectric constant metal layer thickness T, metal connecting line length L with distance between centers of tracks S-phase pass; Interconnection interlayer parasitic capacitance main with metal level dielectric constant and metal connecting line width W, metal connecting line length L, metal interlevel dielectric layer thickness H relevant, it is possible to design large area and with layer coupling capacitive calibration process above parameter. The unified thickness with metal wire of resistance, resistivity etc. is correlated with, it is possible to design serpentine resistive survey sets the technological parameters such as the resistivity of correct-by-construction metal level.
The electric capacity that rear road metal wire is constituted is less, and test is easily caused by error, and extraction model is likely to cause model error on this basis. For calibration model error, industry generally adopts the ring oscillator adding Interconnect Load to be verified, because the time delay that its frequency of oscillation will directly reflect that parasitic capacitance resistance brings. The accuracy of ITF file is determined by the frequency of oscillation of contrast test circuit and the result utilizing the emulation of ITF file to obtain.
Said method has been merely given as comparatively general test circuit, cannot the error of effective location model when reality performs. The frequency of oscillation of ring oscillator is a comprehensive result, the DC characteristic of MOS device, the capacitance characteristic of MOS device itself, MOS device and through hole, middle road parasitism parasitic capacitance between post-channel interconnection line, the parasitic capacitance resistance of post-channel interconnection metal wire all can affect frequency of oscillation, and ring oscillator survey sets itself and also brings along error, above-mentioned factor all can to the problem of road model after we effectively location, and calibration model brings difficulty.
Summary of the invention
In order to overcome problem above, the invention provides the bearing calibration of a kind of rear road parasitism Interconnect model.
To achieve these goals, the invention provides a kind of method of road parasitism Interconnect model after correction, the ITF file of rear road parasitism Interconnect model is corrected by the method, comprising:
Step 01: design the ring oscillator of a series of different loads type, in order to parasitism interconnected model in road after correcting; The MOS device design test structure used in above-mentioned ring oscillator is carried out mapping test, based on test data, the spice model of MOS device is corrected, the statistical distribution characteristic of data is tested, it is determined that for the wafer set of ring oscillator mapping test based on MOS;
Step 02: design non-loaded and capacitive load ring oscillator, wherein capacitive load ring oscillator is that the parallel connection adding one or more electric capacity on non-loaded ring oscillator basis is constituted as load; Based on described wafer set, above-mentioned non-loaded and capacitive load ring oscillator is carried out mapping test, obtain corresponding frequency of oscillation, and frequency of oscillation is converted into the time delay of single-stage phase inverter; The test data of single-stage phase inverter time delay are carried out linear fit with load number for independent variable;
Step 03: above-mentioned non-loaded and capacitive load ring oscillator is emulated, obtains the time delay of single-stage phase inverter;The emulation data of single-stage phase inverter time delay are carried out linear fit with capacitive load number for independent variable;
Step 04: contrast above-mentioned test data and the emulation linear fitting result of data, intercept based on described linear fit result corrects the middle road parasitic capacitance relevant parameter between MOS device and post-channel interconnection line, ITF file Zhong Hou road parasitic capacitance relevant parameter is corrected based on the slope in described linear fit result, make emulation data coincide with test data, update ITF file;
Step 05: the ring oscillator of design capacitance ohmic load, the ring oscillator carrying out testing and emulating this capacitance resistance load respectively obtains single-stage phase inverter time delay, after correction, road dead resistance relevant parameter makes test data coincide with emulation data, updates ITF file;
Step 06: repeat the above steps 03-05, until the single-stage reverser delay test data of all ring oscillators and emulation data are coincide.
Preferably, described method specifically includes:
Step 101: design a non-loaded ring oscillator test circuit, it is determined that the size of the MOS device used in the phase inverter in this non-loaded ring oscillator test circuit and the progression of phase inverter; And draw ring oscillator domain;
Step 102: couple electric capacity and layer capacitance for load with same layer respectively, one group of ring oscillator test circuit of each design, wherein, the MOS device size that the phase inverter in described ring oscillator test circuit uses is equivalently-sized with the MOS device that above-mentioned non-loaded ring oscillator test circuit uses; And choose basic capacitive load, use the parallel connection of single or multiple basic capacitive load as load; The electric capacity quantity that the load of the described each ring oscillator circuit in one group of ring oscillator test circuit is in parallel is different;
Step 103: test the MOS device used in circuit for described ring oscillator, the test structure of design correspondingly-sized, measure the I-V curve of this MOS device, Cgg, Cgc capacitance curve, and this MOS device is carried out mapping test, it is judged that whether the electrology characteristic average of this MOS device and Spice model coincide; As misfitted, then adjust the Spice model of this MOS device so that MOS device DC characteristic and capacitance characteristic are all in the error allowed band of electrology characteristic average;
Step 104: choose the wafer at MOS device place in the error allowed band of described electrology characteristic average as the ring oscillator mapping wafer set tested;
Step 105: in described wafer set, to described non-loaded electric capacity and there is the ring oscillator of load capacitance to carry out mapping test, thus testing out frequency of oscillation, and ask for the average of frequency of oscillation, then, the time delay that the average of this frequency is converted to single-stage phase inverter is 1/ (progression of the average * phase inverter of frequency);
Step 106: with the number of load for transverse axis, the time delay of single-stage phase inverter is the longitudinal axis, draws out test data; Adopt ITF file and Spice model emulation ring oscillator circuit, obtain oscillator frequency simulation value, and described oscillator frequency simulation value is converted into the emulation time delay of single-stage phase inverter, then draw out emulation data;
Step 107: according to the described emulation data linearity for number of loads, will deviate from the ring oscillator circuit of the linearity and retest or delete described test data;
Step 108: respectively described emulation data and described test data are carried out linear fit and obtain fitted figure, compares slope and the intercept of the fitted figure of described emulation data and the fitted figure of described test data;When described intercept difference, then adjust road parasitic capacitance relevant parameter in the MOS device in ITF file, update ITF file; When described slope difference, then adjust ITF file Zhong Hou road parasitic capacitance relevant parameter, the then difference according to basic load, determine parameter type, and adjust described rear road parasitic capacitance relevant parameter, update ITF file;
Step 109: choose a capacitive load ring oscillator in above-mentioned capacitive load, load capacitance parallel resistance is constituted capacitance resistance unloaded ring oscillator circuit, the frequency of oscillation of testing capacitor ohmic load ring oscillator, obtain single-stage inverter delay, and capacitance resistance unloaded ring oscillator circuit is carried out emulation by ITF file basis in the updated and obtains the first simulation value, contrast described test data whether identical with described first simulation value; If differing, then adjust the dead resistance relevant parameter of ITF file, update ITF file;
Step 110: the ITF file of the renewal obtained according to described step 109 emulates in described step 101 non-loaded ring oscillator circuit again to obtain the second simulation value, judge that described second simulation value and described test data are whether in range of error, if not existing, then readjust middle road parasitic capacitance relevant parameter, and update ITF file;
Step 111: the capacitive load ring oscillator circuit that the ITF file of the renewal obtained according to described step 110 comes in simulation process 102 is to obtain the 3rd simulation value, judge that described 3rd simulation value and described test data are whether in range of error, if not existing, then readjust rear road parasitic capacitance relevant parameter, and update ITF file;
Step 112: the capacitance resistance unloaded ring oscillator circuit that the ITF file of the renewal obtained according to described step 111 emulates in described step 109 is to obtain the 4th simulation value, judge that described 4th simulation value and described test data are whether in range of error, if not existing, then readjust resistance relevant parameter, and update ITF file;
Step 113: repeating said steps 110-112, until the simulation value of all of ring oscillator circuit and described test data are within range of error, thus obtaining the ITF file based on circuit calibration.
Preferably, in described step 101, described ring oscillator circuit includes multistage phase inverter, and the output stage of each of which level phase inverter uses the shortest metal interconnecting wires that design rule allows to be connected with the input pole of one-level phase inverter behind.
Preferably, in described step 102, capacitive load structural design should comprise each metal level of different technical parameters, each metal layer optional that technological parameter is identical is taken one layer and is designed; Capacitive load unit includes same layer coupling electric capacity and interlayer large area electric capacity, respectively in order to correct in ITF file with layer metallic parasitic electric capacity relevant parameter and interlayer sneak electric capacity relevant parameter.
Preferably, in described step 109, ohmic load can be made up of the metal level of different technical parameters, respectively in order to correct the dead resistance relevant parameter of corresponding metal level.
The through hole sectional area that preferably, in described step 108, described middle road parasitic capacitance relevant parameter includes the following thickness of dielectric layers of the first metal layer, dielectric constant, MOS active area are connected with M1; Described rear road parasitic capacitance relevant parameter includes: post-channel interconnection metal layer thickness, metal level cross section physical dimension parameter, with layer intermetallic dielectric layer dielectric constant, different metal inter-level dielectric thickness and dielectric constant;In described step 109, the dead resistance relevant parameter of described ITF file includes metal level resistivity and metal layer thickness.
Preferably, in described step 109, described resistance on the ring oscillator of capacitive load in parallel resistance is serpentine resistive structure.
Preferably, in described step 01, non-loaded MOS device is carried out mapping test and includes the test of direct current IV curve, capacitance curve test
Preferably, the error allowed band of described electrology characteristic average be described electrology characteristic average �� 5% in.
The present invention proposes one group of combined test structure, it is first determined the DC characteristic of MOS device, capacitance characteristic model accuracy.
Provide one group of metal wire on this basis to connect the ring oscillator bringing load minimum and survey and set structure, the accuracy of road simulation model in assessment, and provide bearing calibration. Provide one group of varying number, the ring oscillator test structure of the capacitive interconnection metallization lines load of different capacitance structures, the accuracy of road parasitic capacitance relevant parameter after assessment on this basis.
Above-mentioned test data are carried out linear process, namely linear regression analysis is done in single-stage phase inverter time delay and load number, respectively according to parasitic capacitance relevant parameter in road in the intercept of fitting a straight line and slope correction MOS and post-channel interconnection line parasitic capacitance relevant parameter. Provide the capacitance resistance ring oscillator test structure as load in parallel on this basis, assess dead resistance relevant parameter accuracy.
And above-mentioned ring oscillator is surveyed and set in circuit, its circuit construction variations is all that changing a certain principal element positions modeling, and this can help our location model problem place to a great extent on the existing ring oscillator test circuit of contrast. but non-loaded ring oscillator can not avoid the parasitic factor that post-channel interconnection metal wire brings completely, the ring oscillator frequency of oscillation changing value caused after adding load is simultaneously relevant with MOS parasitism factor and affiliated load, actual used load, do not have the load of pure capacitive or purely resistive, capacitive load has dead resistance equally, ohmic load has parasitic capacitance equally, non-principal factor cannot be completely eliminated by circulating above-mentioned steps for these, the each model parameter of iteration correction, the accuracy of model can be stepped up, until the convergence of this process, namely all test structured testing values and simulation value are in range of error.
The bearing calibration of the rear road parasitism Interconnect model of the present invention, can being likely to bring the model parameter of error by expliciting the position, each step can highlight principal element, so that it is guaranteed that the effectiveness of parameter correction, make model reach degree of precision, and improved the accuracy of model by iteration correction further.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the bearing calibration of the rear road parasitism Interconnect model of a preferred embodiment of the present invention
Fig. 2 is the circuit diagram of the non-loaded ring oscillator of a preferred embodiment of the present invention
Fig. 3 is the circuit diagram of the ring oscillator of the capacitive load of a preferred embodiment of the present invention
Fig. 4 is the circuit diagram of the ring oscillator of multiple capacitive loads of a preferred embodiment of the present invention
Fig. 5 is the circuit diagram of the ring oscillator of the capacitance resistance load of a preferred embodiment of the present invention
Fig. 6 is the schematic diagram of the same layer coupling capacitance structure of a preferred embodiment of the present invention
Fig. 7 is the schematic diagram of the layer coupling capacitance structure of a preferred embodiment of the present invention
Fig. 8 is the schematic diagram of the serpentine resistive structure of a preferred embodiment of the present invention
Detailed description of the invention
For making present disclosure clearly understandable, below in conjunction with Figure of description, present disclosure is described further.Certainly the invention is not limited in this specific embodiment, the general replacement known by those skilled in the art is also covered by protection scope of the present invention.
The method of road parasitism Interconnect model after the correction of the present invention, the ITF file of rear road parasitism Interconnect model is corrected by the method, in one embodiment of the present of invention, refers to Fig. 1, including:
Step 01: design the ring oscillator of a series of different loads type, in order to parasitism interconnected model in road after correcting; The MOS device design test structure used in above-mentioned ring oscillator is carried out mapping test, based on test data, the spice model of MOS device is corrected, the statistical distribution characteristic of data is tested, it is determined that for the wafer set of ring oscillator mapping test based on MOS; In one preferred embodiment, MOS device is carried out mapping test and includes the test of direct current IV curve, capacitance curve test;
Step 02: design non-loaded and capacitive load ring oscillator, wherein capacitive load ring oscillator is that the parallel connection adding one or more electric capacity on non-loaded ring oscillator basis is constituted as load; Based on described wafer set, above-mentioned non-loaded and capacitive load ring oscillator is carried out mapping test, obtain corresponding frequency of oscillation, and frequency of oscillation is converted into the time delay of single-stage phase inverter; The test data of single-stage phase inverter time delay are carried out linear fit with load number for independent variable;
Step 03: above-mentioned non-loaded and capacitive load ring oscillator is emulated, obtains the time delay of single-stage phase inverter; The emulation data of single-stage phase inverter time delay are carried out linear fit with capacitive load number for independent variable;
Step 04: contrast above-mentioned test data and the emulation linear fitting result of data, intercept based on described linear fit result corrects the middle road parasitic capacitance relevant parameter between MOS device and post-channel interconnection line, ITF file Zhong Hou road parasitic capacitance relevant parameter is corrected based on the slope in described linear fit result, make emulation data coincide with test data, update ITF file;
Step 05: the ring oscillator of design capacitance ohmic load, the ring oscillator carrying out testing and emulating this capacitance resistance load respectively obtains single-stage phase inverter time delay, after correction, road dead resistance relevant parameter makes test data coincide with emulation data, updates ITF file;
Step 06: repeat the above steps 03-05, until the single-stage reverser delay test data of all ring oscillators and emulation data are coincide.
Below in conjunction with accompanying drawing 2-8 and specific embodiment, the present invention is described in further detail. It should be noted that, accompanying drawing all adopts the form simplified very much, uses non-ratio accurately, and only in order to conveniently, clearly to reach to aid in illustrating the purpose of the present embodiment.
Step 101: design a non-loaded ring oscillator test circuit, it is determined that the size of the MOS device used in the phase inverter in this non-loaded ring oscillator test circuit and the progression of phase inverter; And draw ring oscillator domain;
Concrete, the circuit structure of non-loaded ring oscillator is as in figure 2 it is shown, circuit includes multistage phase inverter, and wherein the output stage of every grade of phase inverter uses the shortest metal interconnecting wires that design rule allows to be connected with the input pole of one-level phase inverter behind; The impact on ring oscillator frequency of oscillation is postponed with what reduce that post-channel interconnection line causes.
Step 102: couple electric capacity and layer capacitance for load with same layer respectively, one group of ring oscillator test circuit of each design, wherein, the MOS device size that the phase inverter in described ring oscillator test circuit uses is equivalently-sized with the MOS device that above-mentioned non-loaded ring oscillator test circuit uses;And choose basic capacitive load, use the parallel connection of single or multiple basic capacitive load as load;
Concrete, the electric capacity quantity that the load of the described each ring oscillator circuit in one group of ring oscillator test circuit is in parallel is different, for instance load electric capacity in parallel respectively 1,2,3,44 ring oscillators constitute one group. Capacitive load structural design should comprise each metal level of different technical parameters as far as possible, each metal layer optional that technological parameter is identical is taken one layer and is designed; Capacitive load unit includes same layer coupling electric capacity and interlayer large area electric capacity, respectively in order to correct in ITF file with layer metallic parasitic electric capacity relevant parameter and interlayer sneak electric capacity relevant parameter
The structure of the ring oscillator of formed capacitive load as it is shown on figure 3, the multiple capacitive loads formed ring oscillator structure as shown in Figure 4; For 1P6M technique, this technique has the first metal layer (M1), the second metal level (M2), the 3rd metal level (M3), the 4th metal level (M4), fifth metal layer (M5) and the 6th metal level (M6), the technique of the first metal layer (M1) is different to the technique of the 6th metal level (M2��M6) from the second metal level, and the second metal level is identical to the technique of the 6th metal level (M2��M6); Choose the coupling electric capacity C of the first metal layer (M1) respectivelyM1Coupling electric capacity C with the second metal level (M2)M2Electric capacity is coupled, as shown in Figure 6 as same layer; Choose the first metal layer (M1) and the layer capacitance C of the second metal level (M2)M1M2, and the layer capacitance of the second metal level (M2) and the 3rd metal level (M3) as layer coupling electric capacity CM2M3, as shown in Figure 7; In Fig. 2, C can respectively CM1, CM2, CM1M2, CM2M3, choose the physical dimensions such as the most live width of short processes size electric capacity, gap that design rule allows.
Step 103: test the MOS device used in circuit for described ring oscillator, the test structure of design correspondingly-sized, measure the I-V curve of this MOS device, Cgg, Cgc capacitance curve, and this MOS device is carried out mapping test, it is judged that whether the electrology characteristic average of this MOS device and Spice model coincide; As misfitted, then adjust the Spice model of this MOS device so that MOS device DC characteristic and capacitance characteristic are all in the error allowed band of electrology characteristic average;
Concrete, the error allowed band of electrology characteristic average be electrology characteristic average �� 5% in; It is industry current techique for the MOS device test structure used in ring oscillator circuit, repeats no more here.
Step 104: choose the wafer at MOS device place in the error allowed band of described electrology characteristic average as the ring oscillator mapping wafer set tested;
Step 105: in described wafer set, to described non-loaded electric capacity and there is the ring oscillator of load capacitance to carry out mapping test, thus testing out frequency of oscillation, and ask for the average of frequency of oscillation, then, the time delay that the average of this frequency is converted to single-stage phase inverter is 1/ (progression of the average * phase inverter of frequency);
Concrete, testing out frequency of oscillation is f, and asks for the average f ' of frequency of oscillation f, then, the average f ' of this frequency f is converted to the time delay T=1/ (the progression N of average f ' the * phase inverter of frequency) of single-stage phase inverter;
Step 106: with the number of load for transverse axis, the time delay of single-stage phase inverter is the longitudinal axis, draws out test data; Adopt ITF file and Spice model emulation ring oscillator circuit, obtain oscillator frequency simulation value, and described oscillator frequency simulation value is converted into the emulation time delay of single-stage phase inverter, then draw out emulation data;
Concrete, with load number, namely the number in parallel of basic load is transverse axis, and single-stage phase inverter time delay is the longitudinal axis, draws Survey data. Use ITF file and Spice model emulation ring oscillator circuit, obtain frequency of oscillation simulation value, be converted into the time delay of single-stage phase inverter drawing data equally.
Step 107: according to the described emulation data linearity for number of loads, will deviate from the ring oscillator circuit of the linearity and retest or delete described test data;
Concrete, owing to basic load is identical, emulation data can show the good linearity. Observing the test data linearity for number of loads, the ring oscillator for deviating considerably from the linearity should retest or reject this data.
Step 108: respectively described emulation data and described test data are carried out linear fit and obtain fitted figure, compares slope and the intercept of the fitted figure of described emulation data and the fitted figure of described test data; When described intercept difference, then adjust road parasitic capacitance relevant parameter in the MOS device in ITF file, update ITF file; When described slope difference, then adjust ITF file Zhong Hou road parasitic capacitance relevant parameter, the then difference according to basic load, determine parameter type, and adjust described rear road parasitic capacitance relevant parameter, update ITF file;
Concrete, middle road post electric capacity relevant parameter can be the first metal layer (M1) following thickness of dielectric layers, the physical dimension etc. of the through hole sectional area that the dielectric constant of medium, MOS active area are connected with M1 between active area and the first metal layer (M1). Rear road parasitic capacitance relevant parameter includes: post-channel interconnection metal layer thickness, metal level cross section physical dimension parameter, with layer intermetallic dielectric layer dielectric constant, different metal inter-level dielectric thickness and dielectric constant; Difference according to basic load, determine parameter type, such as, electric capacity is coupled bigger with the dielectric constant dependency with layer metal layer thickness, with layer inter-metal medium with layer, interlayer large area electric capacity and inter-level dielectric layer thickness, dielectric constant dependency are bigger, adjust these parameters, update ITF file.
Step 109: choose a capacitive load ring oscillator in above-mentioned capacitive load, load capacitance parallel resistance is constituted capacitance resistance unloaded ring oscillator circuit, the frequency of oscillation of testing capacitor ohmic load ring oscillator, obtain single-stage inverter delay, and capacitance resistance unloaded ring oscillator circuit is carried out emulation by ITF file basis in the updated and obtains the first simulation value, contrast described test data whether identical with described first simulation value; If differing, then adjust the dead resistance relevant parameter of ITF file, update ITF file;
Concrete, the dead resistance relevant parameter of ITF file includes metal level resistivity and metal layer thickness, choose certain capacitive load ring oscillator above-mentioned, parallel resistance on selected capacitive load ring oscillator basis, design capacitance ohmic load ring oscillator, the circuit of the ring oscillator of capacitance resistance load is as shown in Figure 5, test its frequency of oscillation, obtain single-stage inverter delay, and the circuit emulating this capacitance resistance unloaded ring oscillator in ITF file basis in the updated obtains simulation value, whether contrast test data and simulation value coincide, as misfitted the parameter (resistance relevant parameter) adjusting ITF file resistance type, such as metal level resistivity, metal layer thickness etc., update ITF file.Here resistance in parallel on the ring oscillator of capacitive load adopts serpentine resistive structure as shown in Figure 7. Ohmic load can be made up of the metal level of different technical parameters, can respectively in order to correct the dead resistance relevant parameter of corresponding metal level. The present invention adopts the resistance of the first metal layer to correct the parameter of resistance type of the first metal layer for 1P6M technique, adopts the resistance of the second metal level to correct second metal level parameter to the resistance type of the 6th metal level.
Step 110: the ITF file of the renewal obtained according to described step 109 emulates in described step 101 non-loaded ring oscillator circuit again to obtain the second simulation value, judge that described second simulation value and described test data are whether in range of error, if not existing, then readjust middle road parasitic capacitance relevant parameter, and update ITF file;
It should be noted that the range of error in the present embodiment be electrology characteristic average �� 5% in.
Step 111: the capacitive load ring oscillator circuit that the ITF file of the renewal obtained according to described step 110 comes in simulation process 102 is to obtain the 3rd simulation value, judge that described 3rd simulation value and described test data are whether in range of error, if not existing, then readjust rear road parasitic capacitance relevant parameter, and update ITF file;
Step 112: the capacitance resistance unloaded ring oscillator circuit that the ITF file of the renewal obtained according to described step 111 emulates in described step 109 is to obtain the 4th simulation value, judge that described 4th simulation value and described test data are whether in range of error, if not existing, then readjust resistance relevant parameter, and update ITF file;
Step 113: repeating said steps 110-112, until the simulation value of all of ring oscillator circuit and described test data are within range of error, thus obtaining the ITF file based on circuit calibration.
Although the present invention discloses as above with preferred embodiment; right described embodiment is illustrated only for the purposes of explanation; it is not limited to the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection domain that the present invention advocates should be as the criterion with described in claims.
Claims (9)
1. a method for road parasitism Interconnect model after correction, the ITF file of rear road parasitism Interconnect model is corrected by the method, it is characterised in that including:
Step 01: design the ring oscillator of a series of different loads type, in order to parasitism interconnected model in road after correcting; The MOS device design test structure used in above-mentioned ring oscillator is carried out mapping test, based on test data, the spice model of MOS device is corrected, the statistical distribution characteristic of data is tested, it is determined that for the wafer set of ring oscillator mapping test based on MOS;
Step 02: design non-loaded and capacitive load ring oscillator, wherein capacitive load ring oscillator is that the parallel connection adding one or more electric capacity on non-loaded ring oscillator basis is constituted as load; Based on described wafer set, above-mentioned non-loaded and capacitive load ring oscillator is carried out mapping test, obtain corresponding frequency of oscillation, and frequency of oscillation is converted into the time delay of single-stage phase inverter; The test data of single-stage phase inverter time delay are carried out linear fit with load number for independent variable;
Step 03: above-mentioned non-loaded and capacitive load ring oscillator is emulated, obtains the time delay of single-stage phase inverter;The emulation data of single-stage phase inverter time delay are carried out linear fit with capacitive load number for independent variable;
Step 04: contrast above-mentioned test data and the emulation linear fitting result of data, intercept based on described linear fit result corrects the middle road parasitic capacitance relevant parameter between MOS device and post-channel interconnection line, ITF file Zhong Hou road parasitic capacitance relevant parameter is corrected based on the slope in described linear fit result, make emulation data coincide with test data, update ITF file;
Step 05: the ring oscillator of design capacitance ohmic load, the ring oscillator carrying out testing and emulating this capacitance resistance load respectively obtains single-stage phase inverter time delay, after correction, road dead resistance relevant parameter makes test data coincide with emulation data, updates ITF file;
Step 06: repeat the above steps 03-05, until the single-stage reverser delay test data of all ring oscillators and emulation data are coincide.
2. method according to claim 1, it is characterised in that described method specifically includes:
Step 101: design a non-loaded ring oscillator test circuit, it is determined that the size of the MOS device used in the phase inverter in this non-loaded ring oscillator test circuit and the progression of phase inverter; And draw ring oscillator domain;
Step 102: couple electric capacity and layer capacitance for load with same layer respectively, one group of ring oscillator test circuit of each design, wherein, the MOS device size that the phase inverter in described ring oscillator test circuit uses is equivalently-sized with the MOS device that above-mentioned non-loaded ring oscillator test circuit uses; And choose basic capacitive load, use the parallel connection of single or multiple basic capacitive load as load; The electric capacity quantity that the load of the described each ring oscillator circuit in one group of ring oscillator test circuit is in parallel is different;
Step 103: test the MOS device used in circuit for described ring oscillator, the test structure of design correspondingly-sized, measure the I-V curve of this MOS device, Cgg, Cgc capacitance curve, and this MOS device is carried out mapping test, it is judged that whether the electrology characteristic average of this MOS device and Spice model coincide; As misfitted, then adjust the Spice model of this MOS device so that MOS device DC characteristic and capacitance characteristic are all in the error allowed band of electrology characteristic average;
Step 104: choose the wafer at MOS device place in the error allowed band of described electrology characteristic average as the ring oscillator mapping wafer set tested;
Step 105: in described wafer set, to described non-loaded electric capacity and there is the ring oscillator of load capacitance to carry out mapping test, thus testing out frequency of oscillation, and ask for the average of frequency of oscillation, then, the time delay that the average of this frequency is converted to single-stage phase inverter is 1/ (progression of the average * phase inverter of frequency);
Step 106: with the number of load for transverse axis, the time delay of single-stage phase inverter is the longitudinal axis, draws out test data; Adopt ITF file and Spice model emulation ring oscillator circuit, obtain oscillator frequency simulation value, and described oscillator frequency simulation value is converted into the emulation time delay of single-stage phase inverter, then draw out emulation data;
Step 107: according to the described emulation data linearity for number of loads, will deviate from the ring oscillator circuit of the linearity and retest or delete described test data;
Step 108: respectively described emulation data and described test data are carried out linear fit and obtain fitted figure, compares slope and the intercept of the fitted figure of described emulation data and the fitted figure of described test data;When described intercept difference, then adjust road parasitic capacitance relevant parameter in the MOS device in ITF file, update ITF file; When described slope difference, then adjust ITF file Zhong Hou road parasitic capacitance relevant parameter, the then difference according to basic load, determine parameter type, and adjust described rear road parasitic capacitance relevant parameter, update ITF file;
Step 109: choose a capacitive load ring oscillator in above-mentioned capacitive load, load capacitance parallel resistance is constituted capacitance resistance unloaded ring oscillator circuit, the frequency of oscillation of testing capacitor ohmic load ring oscillator, obtain single-stage inverter delay, and capacitance resistance unloaded ring oscillator circuit is carried out emulation by ITF file basis in the updated and obtains the first simulation value, contrast described test data whether identical with described first simulation value; If differing, then adjust the dead resistance relevant parameter of ITF file, update ITF file;
Step 110: the ITF file of the renewal obtained according to described step 109 emulates in described step 101 non-loaded ring oscillator circuit again to obtain the second simulation value, judge that described second simulation value and described test data are whether in range of error, if not existing, then readjust middle road parasitic capacitance relevant parameter, and update ITF file;
Step 111: the capacitive load ring oscillator circuit that the ITF file of the renewal obtained according to described step 110 comes in simulation process 102 is to obtain the 3rd simulation value, judge that described 3rd simulation value and described test data are whether in range of error, if not existing, then readjust rear road parasitic capacitance relevant parameter, and update ITF file;
Step 112: the capacitance resistance unloaded ring oscillator circuit that the ITF file of the renewal obtained according to described step 111 emulates in described step 109 is to obtain the 4th simulation value, judge that described 4th simulation value and described test data are whether in range of error, if not existing, then readjust resistance relevant parameter, and update ITF file;
Step 113: repeating said steps 110-112, until the simulation value of all of ring oscillator circuit and described test data are within range of error, thus obtaining the ITF file based on circuit calibration.
3. method according to claim 2, it is characterized in that, in described step 101, described ring oscillator circuit includes multistage phase inverter, and the output stage of each of which level phase inverter uses the shortest metal interconnecting wires that design rule allows to be connected with the input pole of one-level phase inverter behind.
4. method according to claim 2, it is characterised in that in described step 102, capacitive load structural design should comprise each metal level of different technical parameters, each metal layer optional that technological parameter is identical is taken one layer and is designed; Capacitive load unit includes same layer coupling electric capacity and interlayer large area electric capacity, respectively in order to correct in ITF file with layer metallic parasitic electric capacity relevant parameter and interlayer sneak electric capacity relevant parameter.
5. method according to claim 4, it is characterised in that in described step 109, ohmic load can be made up of the metal level of different technical parameters, respectively in order to correct the dead resistance relevant parameter of corresponding metal level.
6. method according to claim 2, it is characterised in that in described step 108, the through hole sectional area that described middle road parasitic capacitance relevant parameter includes the following thickness of dielectric layers of the first metal layer, dielectric constant, MOS active area are connected with M1;Described rear road parasitic capacitance relevant parameter includes: post-channel interconnection metal layer thickness, metal level cross section physical dimension parameter, with layer intermetallic dielectric layer dielectric constant, different metal inter-level dielectric thickness and dielectric constant; In described step 109, the dead resistance relevant parameter of described ITF file includes metal level resistivity and metal layer thickness.
7. method according to claim 2, it is characterised in that in described step 109, described resistance on the ring oscillator of capacitive load in parallel resistance is serpentine resistive structure.
8. method according to claim 1, it is characterised in that in described step 01, carries out mapping test and includes the test of direct current IV curve, capacitance curve test non-loaded MOS device.
9. method according to claim 1, it is characterised in that the error allowed band of described electrology characteristic average be described electrology characteristic average �� 5% in.
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| CN110674612A (en) * | 2019-09-25 | 2020-01-10 | 华东师范大学 | Modeling method for back-end interconnection parasitic capacitance resistance of super-large-scale integrated circuit process |
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