CN115831936B - Substrate with buried capacitor and buried capacitor testing method thereof - Google Patents
Substrate with buried capacitor and buried capacitor testing method thereof Download PDFInfo
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- CN115831936B CN115831936B CN202111086106.4A CN202111086106A CN115831936B CN 115831936 B CN115831936 B CN 115831936B CN 202111086106 A CN202111086106 A CN 202111086106A CN 115831936 B CN115831936 B CN 115831936B
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Abstract
The application discloses a substrate with buried capacitor, comprising: a top layer having a first top pad, a third via, a second resistor, and a fourth via; a formation; a second insulating layer is arranged between the signal layer and the stratum, and the stratum and the signal layer are used as electrode plates of the third capacitor and the fourth capacitor; a bottom layer having a first bottom pad, and the top layer, the ground layer, and the bottom layer are all grounded; wherein the input current flows through the first bottom pad, the fourth via, the second resistor, the third via and the first top pad to form a first current branch; the interference current is grounded after passing through the first bottom bonding pad, the fourth via hole and the third capacitor to form a second current branch, and is grounded after passing through the first bottom bonding pad, the fourth via hole, the second resistor, the third via hole and the fourth capacitor to form a third current branch. The substrate enables a person skilled in the art to detect the capacitance of each substrate, and improves detection accuracy. The application also correspondingly discloses a buried capacitance testing method of the substrate.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a substrate with a buried capacitor and a buried capacitor testing method thereof.
Background
There are various ways of integrating in the package, wherein 2D (2D) integration, 2d+ integration, 4D integration, cavity integration, and planar integration are all realized by a substrate, or by electrically connecting the wafer to MEMS (Micro-Electro-Mechanical System, i.e. microelectromechanical system). Substrates continue to be an important component of the integrated circuit packaging art. In order to further improve the integration level, the passive element capacitor, resistor and inductor are partially or fully embedded into the substrate in the plane integration mode in the in-package integration, which is called as a buried capacitor or resistor or buried inductance substrate. The filter circuit formed by the buried resistor can protect the inside from the interference of ESD (electrostatic discharge) and RF (Radio Frequency) signals.
The actual imposition is spliced by the base plates so as to improve the utilization rate of the plates. In the detection of the resistance and capacitance of the buried resistor, there is a detection of the resistance. As in patent CN201510082453.8, a buried resistor detection method is provided: and constructing a resistance detection graph at the imposition edge, and replacing the detection result of each substrate with the resistance detection result of the imposition edge graph.
The capacitor can also adopt a similar mode by replacing the detection result of each substrate with the detection result of the buried resistance value of the spliced edge pattern, but the mode ignores the difference of each substrate, and the detection risk exists. For this purpose, it is necessary to detect the capacitance value of each substrate.
Disclosure of Invention
Aiming at the problems in the related art, the application provides the substrate with the buried capacitor, which can detect the capacitance of each substrate and improve the detection accuracy.
The technical scheme of the application is realized as follows:
according to one aspect of the present application, there is provided a substrate having a buried capacitor, comprising:
a top layer having a first top pad, a third via, a second resistor, and a fourth via;
a formation;
a second insulating layer is arranged between the signal layer and the stratum, and the stratum and the signal layer are used as electrode plates of a third capacitor and a fourth capacitor;
a bottom layer having a first bottom pad, and the top layer, the ground layer, and the bottom layer are all grounded;
wherein an input current flows through the first bottom pad, the fourth via, the second resistor, the third via, and the first top pad to form a first current branch; the interference current is grounded after passing through the first bottom bonding pad, the fourth via hole and the third capacitor to form a second current branch, and is grounded after passing through the first bottom bonding pad, the fourth via hole, the second resistor, the third via hole and the fourth capacitor to form a third current branch.
The third via hole is electrically connected with the top layer and the signal layer, and is electrically insulated from the stratum and the bottom layer to form an electrical connection between the third via hole and the fourth capacitor;
the fourth via is electrically connected with the top layer and the signal layer, and is electrically insulated from the ground layer and the bottom layer to form an electrical connection between the fourth via and the third capacitor.
And the fifth via hole is electrically connected with the top layer, the stratum layer and the bottom layer and grounded, and is electrically insulated from the signal layer.
The top layer is further provided with a second top bonding pad, a second via hole, a first resistor and a first via hole;
the signal layer and the stratum also serve as electrode plates of a first capacitor and a second capacitor;
the bottom layer is also provided with a second bottom bonding pad;
the output current forms a fourth current branch through the second top bonding pad, the second via hole, the first resistor, the first via hole and the second bottom bonding pad; the interference current is grounded after passing through the second bottom bonding pad, the first via hole and the first capacitor to form a fifth current branch, and is grounded after passing through the second bottom bonding pad, the first via hole, the first resistor, the second via hole and the second capacitor to form a sixth current branch.
The second via is electrically connected with the top layer and the signal layer, and is electrically insulated from the stratum and the bottom layer to form an electrical connection between the second via and the second capacitor;
the first via is electrically connected with the top layer and the signal layer, and is electrically insulated from the ground layer and the bottom layer to form an electrical connection between the first via and the first capacitor.
The first insulating layer is arranged between the top layer and the stratum, the second insulating layer is arranged between the stratum and the signal layer, and the third insulating layer is arranged between the signal layer and the bottom layer, wherein the dielectric coefficient of the second insulating layer is larger than that of the first insulating layer and the third insulating layer.
The bottom layer is also provided with a seventh bonding pad, and the seventh bonding pad is grounded.
Correspondingly, the application also provides a buried capacitor testing method of the substrate, which is used for testing the substrate with the buried capacitor and comprises the following steps:
the probe measures the capacitance value between the second bottom bonding pad and the seventh bonding pad, and the test result is the sum of the first capacitance and the second capacitance;
the probe measures the capacitance value between the first bottom bonding pad and the seventh bonding pad, and the test result is the sum of the third capacitance and the fourth capacitance;
and judging whether the error between the measured capacitance value and the preset capacitance value is within a preset range.
In summary, the substrate with the buried capacitor and the corresponding buried capacitor testing method provided by the application enable a person skilled in the art to test the capacitor in each substrate, thereby eliminating the possibility of missing detection and improving the detection accuracy.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 illustrates a top schematic view of a front side of a top layer of a substrate provided in accordance with some embodiments;
FIG. 2 illustrates a top view schematic of a front side of a formation of a substrate provided in accordance with some embodiments;
FIG. 3 illustrates a top schematic view of a front side of a signal layer of a substrate provided in accordance with some embodiments;
FIG. 4 illustrates a schematic top view of the back side of the bottom layer of a substrate provided in accordance with some embodiments;
FIG. 5 shows a schematic circuit diagram of the input current and the disturbance current of the top layer;
fig. 6 shows a schematic circuit diagram of the output current and the disturbance current of the top layer.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the application, fall within the scope of protection of the application.
Referring to fig. 1, 2, 3 and 4, according to an embodiment of the present application, there is provided a substrate having a buried capacitor, including a top layer 100, a ground layer 200, a signal layer 300 and a bottom layer 400, which are sequentially stacked. The structure of the substrate will be described in detail below. The substrate in the present application is used in a MEMS (Micro-Electro-Mechanical System, short for microelectromechanical systems) microphone.
A first insulating layer (not shown) is disposed between the top layer 100 and the ground layer 200, a second insulating layer (not shown) is disposed between the ground layer 200 and the signal layer 300, and a third insulating layer (not shown) is disposed between the signal layer 300 and the bottom layer 400, wherein the dielectric constant of the second insulating layer is greater than the dielectric constants of the first insulating layer and the third insulating layer. The plates of the first capacitor (shown as capacitor 1 in the figure), the second capacitor (shown as capacitor 2 in the figure), the third capacitor (shown as capacitor 3 in the figure) and the fourth capacitor (shown as capacitor 4 in the figure) referred to below are the formation 200 and the signal layer 300, respectively. And the first capacitance, the second capacitance, the third capacitance, and the fourth capacitance are separated. The buried capacitor of the present application is actually a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor.
A fifth via (shown as via 5) is electrically connected to the top layer 100, the ground layer 200, the bottom layer 400 and is electrically isolated from the signal layer 300.
A third via (shown as via 3) is electrically connected to the top layer 100, the signal layer 300, and is electrically insulated from the ground layer 200, the bottom layer 400 to form an electrical connection between the third via and the fourth capacitor;
a fourth via (shown as via 4) is electrically connected to the top layer 100, the signal layer 300, and is electrically isolated from the ground layer 200, the bottom layer 400 to form an electrical connection for the fourth via to the third capacitor.
A second via (shown as via 2) is electrically connected to the top layer 100, the signal layer 300, and is electrically insulated from the ground layer 200, the bottom layer 400 to form an electrical connection between the second via and the second capacitor;
a first via (shown as via 1) is electrically connected to the top layer 100, the signal layer 300, and is electrically insulated from the ground layer 200, the bottom layer 400 to form an electrical connection between the first via and the first capacitor.
It should be noted that the first via, the second via, the third via, the fourth via, and the fifth via are all metal vias, and penetrate through the top layer 100, the ground layer 200, the signal layer 300, and the bottom layer 400, so as to realize electrical connection between different levels. Moreover, the first via, the second via, the third via, the fourth via, and the fifth via correspond to the positions shown in fig. 1 to 4.
Referring to fig. 5, the VDD network of the top layer 100 will be described below.
Referring to fig. 1-4 in combination, the top layer 100 has a first top pad (shown as pad 1), a third via, a second resistor (shown as resistor 2), and a fourth via. A second insulating layer is provided between the signal layer 300 and the ground layer 200, and the ground layer 200 and the signal layer 300 serve as electrode plates for the third capacitor and the fourth capacitor. The bottom layer 400 has a first bottom pad (shown as pad 8).
Wherein the input current flows through the first bottom pad, the fourth via, the second resistor, the third via and the first top pad to form a first current branch; the interference current is grounded after passing through the first bottom bonding pad, the fourth via hole and the third capacitor to form a second current branch, and is grounded after passing through the first bottom bonding pad, the fourth via hole, the second resistor, the third via hole and the fourth capacitor to form a third current branch. The interference current is filtered out through the second current branch and the third current branch.
Referring to fig. 6, the VOUT network of the top tier 100 will be described.
Referring to fig. 1-4 in combination, the top layer 100 also has a second top pad (shown as pad 2), a second via, a first resistor (shown as resistor 1), and a first via. The signal layer 300 and the formation 200 also serve as electrode plates for the first capacitance and the second capacitance. The bottom layer 400 also has a second bottom pad (shown as pad 6).
The output current forms a fourth current branch through the second top bonding pad, the second via hole, the first resistor, the first via hole and the second bottom bonding pad; the interference current is grounded after passing through the second bottom bonding pad, the first via hole and the first capacitor to form a fifth current branch, and is grounded after passing through the second bottom bonding pad, the first via hole, the first resistor, the second via hole and the second capacitor to form a sixth current branch.
The above VDD network and VOUT network constitute two sets of pi-type filter circuits.
The top layer 100 and the bottom layer 400 have insulating varnish on the surfaces thereof, and the pads 3, 4, 5, 7 (shown as pad 7) and 9 all belong to the GND network, and the pads are formed by removing the insulating varnish from the pad areas. The top layer 100, the formation 200, and the formation 200 are electrically connected via a fifth via to form a GND network. The seventh bonding pad is used for the following buried capacitance test method of the substrate.
Correspondingly, the application also provides a buried capacitor testing method of the substrate, which is used for the substrate with the buried capacitor, and comprises the following steps:
step 1: the probe measures the capacitance value between the second bottom pad and the seventh pad, and the test result is the sum of the first capacitance and the second capacitance.
Step 2: the probe measures the capacitance value between the first bottom pad and the seventh pad, and the test result is the sum of the third capacitance and the fourth capacitance.
Step 3: and judging whether the error between the measured capacitance value and the preset capacitance value is within a preset range.
In summary, in the existing buried resistor test method, the layout of resistors and capacitors and the layout mode of pads are limited, and those skilled in the art cannot test the capacitors in each substrate. The substrate with the buried capacitor and the corresponding buried capacitor testing method provided by the application enable a person skilled in the art to test the capacitor in each substrate, thereby eliminating the possibility of missing detection and improving the detection accuracy.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the application.
Claims (8)
1. A substrate having a buried capacitor, comprising:
a top layer having a first top pad, a third via, a second resistor, and a fourth via;
a formation;
a second insulating layer is arranged between the signal layer and the stratum, and the stratum and the signal layer are used as electrode plates of a third capacitor and a fourth capacitor;
a bottom layer having a first bottom pad, and the top layer, the ground layer, and the bottom layer are all grounded;
wherein an input current flows through the first bottom pad, the fourth via, the second resistor, the third via, and the first top pad to form a first current branch; the interference current is grounded after passing through the first bottom bonding pad, the fourth via hole and the third capacitor to form a second current branch, and is grounded after passing through the first bottom bonding pad, the fourth via hole, the second resistor, the third via hole and the fourth capacitor to form a third current branch.
2. The substrate with buried capacitor of claim 1, wherein,
the third via is electrically connected with the top layer and the signal layer, and is electrically insulated from the ground layer and the bottom layer to form an electrical connection between the third via and the fourth capacitor;
the fourth via is electrically connected with the top layer and the signal layer, and is electrically insulated from the ground layer and the bottom layer to form an electrical connection between the fourth via and the third capacitor.
3. The substrate with buried capacitor of claim 1, wherein a fifth via is electrically connected to the top layer, the ground layer, the bottom layer and to ground, the fifth via being electrically isolated from the signal layer.
4. The substrate with buried capacitor of claim 1, wherein,
the top layer is also provided with a second top bonding pad, a second via hole, a first resistor and a first via hole;
the signal layer and the stratum also serve as electrode plates of a first capacitor and a second capacitor;
the bottom layer is also provided with a second bottom bonding pad;
the output current forms a fourth current branch through the second top bonding pad, the second via hole, the first resistor, the first via hole and the second bottom bonding pad; the interference current is grounded after passing through the second bottom bonding pad, the first via hole and the first capacitor to form a fifth current branch, and is grounded after passing through the second bottom bonding pad, the first via hole, the first resistor, the second via hole and the second capacitor to form a sixth current branch.
5. The substrate with buried capacitor of claim 4, wherein said second via is electrically connected to said top layer, said signal layer, said second via is electrically insulated from said ground layer, said bottom layer to form an electrical connection of a second via to said second capacitor;
the first via is electrically connected with the top layer and the signal layer, and is electrically insulated from the ground layer and the bottom layer to form an electrical connection between the first via and the first capacitor.
6. The substrate with buried capacitor of claim 1, wherein a first insulating layer is provided between the top layer and the ground layer, the second insulating layer is provided between the ground layer and the signal layer, and a third insulating layer is provided between the signal layer and the bottom layer, wherein a dielectric coefficient of the second insulating layer is greater than dielectric coefficients of the first insulating layer and the third insulating layer.
7. The substrate with buried capacitor of claim 1, wherein the bottom layer further has a seventh pad, the seventh pad being grounded.
8. A burial capacity test method for testing the substrate with burial capacity according to any one of claims 1 to 7, comprising:
the probe measures the capacitance value between the second bottom bonding pad and the seventh bonding pad, and the test result is the sum of the first capacitance and the second capacitance;
the probe measures the capacitance value between the first bottom bonding pad and the seventh bonding pad, and the test result is the sum of the third capacitance and the fourth capacitance;
and judging whether the error between the measured capacitance value and the preset capacitance value is within a preset range.
Priority Applications (1)
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| CN202111086106.4A CN115831936B (en) | 2021-09-16 | 2021-09-16 | Substrate with buried capacitor and buried capacitor testing method thereof |
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| CN202111086106.4A CN115831936B (en) | 2021-09-16 | 2021-09-16 | Substrate with buried capacitor and buried capacitor testing method thereof |
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| CN115831936A CN115831936A (en) | 2023-03-21 |
| CN115831936B true CN115831936B (en) | 2023-09-05 |
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| CN101750529A (en) * | 2008-12-18 | 2010-06-23 | 施耐德电器工业公司 | Capacitive divider device, voltage sensor, trip device module and electrical protection apparatus provided with such a device |
| CN101794929A (en) * | 2009-12-26 | 2010-08-04 | 华为技术有限公司 | Device for improving transmission bandwidth |
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| CN108226237A (en) * | 2018-03-02 | 2018-06-29 | 鄂尔多斯市源盛光电有限责任公司 | A kind of detection method and device |
| CN110137154A (en) * | 2019-04-04 | 2019-08-16 | 惠科股份有限公司 | A kind of test structure, substrate and its manufacturing method |
| CN112738999A (en) * | 2020-10-28 | 2021-04-30 | 苏州浪潮智能科技有限公司 | Differential signal via hole and coupling capacitor impedance continuity design method and PCB |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7026646B2 (en) * | 2002-06-20 | 2006-04-11 | Micron Technology, Inc. | Isolation circuit |
| FR2928030B1 (en) * | 2008-02-22 | 2010-03-26 | Commissariat Energie Atomique | METHOD FOR ALIGNING TWO SUBSTRATES WITH MICROBOBINS |
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- 2021-09-16 CN CN202111086106.4A patent/CN115831936B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6181004B1 (en) * | 1999-01-22 | 2001-01-30 | Jerry D. Koontz | Digital signal processing assembly and test method |
| CN101750529A (en) * | 2008-12-18 | 2010-06-23 | 施耐德电器工业公司 | Capacitive divider device, voltage sensor, trip device module and electrical protection apparatus provided with such a device |
| CN101794929A (en) * | 2009-12-26 | 2010-08-04 | 华为技术有限公司 | Device for improving transmission bandwidth |
| CN103489841A (en) * | 2013-08-08 | 2014-01-01 | 华进半导体封装先导技术研发中心有限公司 | PCB with capacitor, inductor and resistor buried in simultaneously and manufacturing method thereof |
| CN108226237A (en) * | 2018-03-02 | 2018-06-29 | 鄂尔多斯市源盛光电有限责任公司 | A kind of detection method and device |
| CN110137154A (en) * | 2019-04-04 | 2019-08-16 | 惠科股份有限公司 | A kind of test structure, substrate and its manufacturing method |
| CN112738999A (en) * | 2020-10-28 | 2021-04-30 | 苏州浪潮智能科技有限公司 | Differential signal via hole and coupling capacitor impedance continuity design method and PCB |
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