KR20110070317A - Method for forming pattern in semiconductor device - Google Patents

Method for forming pattern in semiconductor device Download PDF

Info

Publication number
KR20110070317A
KR20110070317A KR1020090127105A KR20090127105A KR20110070317A KR 20110070317 A KR20110070317 A KR 20110070317A KR 1020090127105 A KR1020090127105 A KR 1020090127105A KR 20090127105 A KR20090127105 A KR 20090127105A KR 20110070317 A KR20110070317 A KR 20110070317A
Authority
KR
South Korea
Prior art keywords
layer
pattern
forming
mask
relacs
Prior art date
Application number
KR1020090127105A
Other languages
Korean (ko)
Inventor
손민석
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090127105A priority Critical patent/KR20110070317A/en
Publication of KR20110070317A publication Critical patent/KR20110070317A/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G03F7/3021—Imagewise removal using liquid means from a wafer supported on a rotating chuck
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/422—Stripping or agents therefor using liquids only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The pattern forming method of the semiconductor device of the present invention comprises the steps of forming a line / space type first pattern on a semiconductor substrate, and filling a line / space type first pattern on a semiconductor substrate and comprising a RELACS material. Forming a mask layer, forming a photoresist pattern on the resultant product on which the mask layer is formed, and removing a portion of the first pattern using the photoresist pattern and the mask layer as a mask.

Fine pattern, SPT, RELACS material, void

Description

Method for forming pattern in semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a fine pattern of a semiconductor device.

Lithography process of semiconductor manufacturing technology has been recognized as the technology that directly affects the miniaturization of semiconductor devices. The miniaturization of semiconductor devices is because the number of devices that can be processed simultaneously on one wafer is directly related to productivity, that is, the cost competitiveness of each device due to the characteristics of the semiconductor process being processed on a wafer basis.

Since the resolution obtained using the KrF and ArF exposure equipment currently commercially available is limited to about 0.1 μm, attempts to manufacture highly integrated semiconductor devices by forming patterns having smaller sizes are continuing. As one of methods for forming a fine pattern, there is a method of reducing the spacing between patterns by using a resolution enhancement lithography assisted by chemical shrink (RELACS) material. Specifically, when a photoresist pattern is formed by performing an exposure and development process on a semiconductor substrate, and then a RELACS material is coated on the entire surface of the photoresist pattern and a heating process is performed, a crosslinking reaction between the RELACS material and the photoresist pattern occurs and finally The spacing between the patterns is reduced by the obtained pattern, thereby reducing the size of the contact hole.

Meanwhile, various techniques for forming an ultrafine pattern by overcoming the limitation of photolithography equipment have been proposed, one of which is a patterning technique using a spacer. In the patterning technique using a spacer, a thickness of a spacer is formed by forming a material film pattern having a predetermined size on the etching target film, forming a spacer around the material film pattern, and then etching the lower etching target film using the spacer as an etching mask. It is a method to form a fine pattern to such an extent. When the pattern is formed using the spacer patterning technique, the line / space pattern is first formed, and then the end of the line is cut using a contact hole mask. However, when using a contact hole mask, voids occur because the photoresist does not fill well between the lines, and the voids make it difficult to realize a desired pattern because the photoresist film does not function properly as a barrier during the etching process. Occurs.

An object of the present invention is to provide a method of forming a pattern of a semiconductor device capable of effectively forming a fine pattern by filling voids between line / space patterns without voids.

Another technical problem to be achieved by the present invention is to provide a pattern forming method of a semiconductor device that can effectively form a fine pattern by filling voids between line / space type patterns when forming a fine pattern using a spacer. have.

According to an aspect of the present invention, there is provided a method of forming a pattern of a semiconductor device, the method including: forming a first pattern of a line / space type on a semiconductor substrate; Forming a mask layer formed of a RELACS material by filling the first pattern, forming a photoresist pattern on the resultant product on which the mask layer is formed, and using the photoresist pattern and the mask layer as a mask, the first pattern It characterized in that it comprises the step of removing a portion of the.

The forming of the mask layer may include applying a RELACS material layer on the semiconductor substrate on which the first pattern is formed, performing a heat treatment on the RELACS material layer, and a predetermined thickness of the heat treated RELACS material layer. It may include the step of removing.

The removing of the thickness of the RELACS material layer may include removing the thickness of the RELACS material layer using a developer or removing the RELACS material layer by a chemical mechanical polishing (CMP) process.

According to another aspect of the present invention, there is provided a method of forming a pattern of a semiconductor device, including forming an etching target layer on a semiconductor substrate, forming a hard mask layer and a sacrificial layer on the etching target layer, Patterning the film into a line / space type, forming a spacer on a sidewall of the sacrificial layer, removing the sacrificial layer, etching the hard mask layer using the spacer as a mask, and etching the etching target layer Removing the spacers after forming the line / space type etch target pattern, and filling a gap between the etch target pattern and forming a mask layer formed of a RELACS material on the semiconductor substrate on which the etch target pattern is formed; And forming a photoresist pattern on the resultant product on which the mask layer is formed. And removing a portion of the etching target layer pattern by using the photoresist pattern and the mask layer as a mask.

The hard mask layer may be formed of a material having an etching selectivity with respect to the etching target layer.

The sacrificial layer may be formed of a material having an etch selectivity with respect to the hard mask layer.

The spacer may be formed of a material having an etching selectivity with respect to the sacrificial layer, the hard mask layer, and the etching target layer.

The forming of the mask layer may include applying a RELACS material layer on the semiconductor substrate on which the first pattern is formed, performing a heat treatment on the RELACS material layer, and a predetermined thickness of the heat treated RELACS material layer. It may include the step of removing.

In the step of removing the thickness of the RELACS material layer, the thickness of the RELACS material layer may be removed using a developer, or the chemical mechanical polishing (CMP) process may be removed from the RELACS material layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

1 to 8 are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, etching target layers 102 and 104 are formed on the semiconductor substrate 100. The etching target layers 102 and 104 may be a single layer or a multilayer layer in which two or more layers are stacked as shown. In the case of forming the gate of the memory device, the etching target layer 102 may be a gate conductive layer of a transistor made of, for example, a polysilicon layer, and the etching target layer 104 may be formed of, for example, metal silicide to reduce the resistance of the gate. It can be made of a low resistance layer. In the case of a flash memory device, the etching target layer 102 may be a control gate conductive layer of a memory cell transistor and a gate conductive layer of a selection transistor. In addition, in the case of a flash memory device, an interlayer insulating film is formed under the etching target layer 102, and a tunnel oxide film of the cell transistor and a gate insulating film of the selection transistor are formed under the etching target layer 102. Alternatively, the present invention may be applied to a process of forming a trench in a semiconductor substrate to form an isolation layer of a memory device. In this case, the etching target film becomes a semiconductor substrate.

Next, the hard mask 106 is formed on the etching target layer 104, and then the sacrificial layer 108 and the anti-reflection layer 110 are sequentially formed on the hard mask 106.

The hard mask 106 is to protect the etching target layers 102 and 104 in an etching process for patterning the etching target layers 102 and 104. Therefore, the hard mask 106 may be formed of a material having an etching selectivity with respect to the etching target layer in the process of etching the etching target layer. For example, when the etching target film is formed of a polysilicon film, the hard mask 106 may be formed of a nitride film or an oxide film, and the hard mask 106 may be formed of a multilayer film.

In addition, the sacrificial layer 108 may be formed of a material having a high etching selectivity with respect to the hard mask 106. When the hard mask 106 is formed of a nitride film, the sacrificial film 108 may be formed of an oxide film. In addition, the sacrificial film 108 may be formed of a polysilicon film or an amorphous carbon film which is relatively easy to remove through a dry etching process.

The anti-reflection film 110 may be formed of a silicon oxynitride layer (SiON) to prevent reflection of light in a photolithography process for patterning an etch target layer.

Referring to FIG. 2, after the photoresist is applied on the hard mask 106, the photoresist pattern 112 is formed by performing an exposure and development process using a first mask. The photoresist pattern 112 serves as a mask for patterning the sacrificial layer 108 in a subsequent step. In a subsequent step, a spacer is formed on the sidewall of the sacrificial film patterned by the photoresist pattern 112, and finally, a line-shaped pattern is formed using the spacer as a mask. Therefore, the width of the photoresist pattern 112 is a gap between adjacent patterns, and one photoresist pattern 112 is formed between two adjacent patterns. The photoresist pattern 112 is formed to have a space between two adjacent patterns and a space between two adjacent patterns, that is, a double pitch.

Referring to FIG. 3, the anti-reflection film and the sacrificial film are etched using the photoresist pattern as an etch mask, and then the photoresist pattern and the anti-reflection film are removed. Next, a spacer material is deposited on the entire surface of the semiconductor substrate on which the sacrificial film pattern 108a is formed and then etched back to form the spacer 114 on the sidewall of the sacrificial film pattern 108a. The spacer 114 may be formed of a material having an etch selectivity with respect to the sacrificial layer pattern 108a and the hard mask 106. For example, when the sacrificial film pattern 108a is formed of an oxide film and the hard mask 106 is formed of a nitride film, the spacer 114 may be formed of a polysilicon film. In addition, since the width of the pattern is determined according to the thickness of the spacer 114, in order to obtain a desired width of the pattern, the thickness of the spacer 114 must be appropriately adjusted.

Referring to FIG. 4, only the spacers 114 remain by removing the sacrificial layer pattern existing between the spacers 114. The hard mask 106 is etched using the spacer 114 as an etch mask, and then the etching target layers 104 and 102 are etched using the spacer 114 and the hard mask 106 as an etch mask. do.

Referring to FIG. 5, when the spacer is removed, an etch target layer pattern 120 having a line / space type is formed. When the line / space type pattern is formed, a photolithography process using the second mask is performed to form a contact hole pattern while removing unnecessary portions at the end of the line.

To this end, first, a RELACS material is coated on the entire surface of the semiconductor substrate on which the line / space type etching target layer pattern 120 is formed, and then a baking process is performed at a predetermined temperature to form a gap between the line / space type etching target layer patterns. A buried RELACS mask layer 130 is formed. As mentioned, RELACS materials have the property of applying well along narrow line / space patterns and when applied and then heated, the properties change between lines and lines to fill the space between lines without voids. have. Therefore, the void-free RELACS mask layer 130 is formed between the minute etching target layer patterns 120.

Referring to FIG. 6, the thickness of the RELACS mask layer 130 is lowered to a degree such that the thickness of the RELACS mask layer 130 is removed using a developer to protect the substrate between the etching target layer patterns 120. Alternatively, as shown in FIG. 8, a chemical mechanical polishing (CMP) process may be performed on the RELACS mask layer 130 until the etch target layer pattern 120 is exposed.

The photoresist layer 140 is coated on the resultant of which the thickness of the RELACS mask layer 130 is reduced. Since the narrow line patterns are well filled without voids by the RELACS mask layer 130 and the photoresist is applied thereon, the void problem that occurs when the line patterns are filled only with the photoresist does not occur.

Referring to FIG. 7, a photoresist pattern is formed by performing exposure and development processes on the photoresist film. The photoresist pattern 140 is formed to expose the region where the contact hole is to be formed and the distal end of the line / space pattern. Subsequently, the photoresist pattern is etched to form a contact hole, and at the same time, the end of the line / space type etch target layer pattern 120 is etched and removed.

According to the method of forming a pattern of a semiconductor device according to the present invention, a line / space type pattern is formed using a first mask, and then a RELACS material is applied to the entire surface and heat-treated to fill a gap between the patterns, and then a second mask is used. By performing the photolithography process, the void problem that occurs when the line patterns are filled only with the photoresist does not occur.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 to 8 are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with an embodiment of the present invention.

Claims (9)

Forming a first pattern of a line / space type on the semiconductor substrate; Forming a mask layer formed of a RELACS material on the semiconductor substrate, filling the first pattern of the line / space type; Forming a photoresist pattern on the resultant product on which the mask layer is formed; And And removing a part of the first pattern using the photoresist pattern and the mask layer as a mask. The method of claim 1, Forming the mask layer, Applying a layer of RELACS material on the semiconductor substrate having a first pattern formed thereon; Performing heat treatment on the RELACS material layer; And Removing the heat-treated layer of the RELACS material by a predetermined thickness. The method of claim 2, Removing the thickness of the RELACS material layer, Removing the thickness of the RELACS material layer using a developer, or removing the RELACS material layer by a chemical mechanical polishing (CMP) process on the RELACS material layer. Forming an etching target layer on the semiconductor substrate; Forming a hard mask layer and a sacrificial layer on the etching target layer; Patterning the sacrificial layer to a line / space type; Removing the sacrificial layer after forming a spacer on a sidewall of the sacrificial layer; Etching the hard mask layer using the spacer as a mask; Etching the etching target layer to form an etch target layer pattern of a line / space type, and then removing the spacers; Forming a mask layer formed of a RELACS material on the semiconductor substrate on which the etch target layer pattern is formed, filling the etch target layer pattern; Forming a photoresist pattern on the resultant product on which the mask layer is formed; And And removing a portion of the etching target layer pattern using the photoresist pattern and the mask layer as masks. 5. The method of claim 4, The hard mask layer may be formed of a material having an etch selectivity with respect to the etch target layer. 5. The method of claim 4, The sacrificial layer may be formed of a material having an etch selectivity with respect to the hard mask layer. 5. The method of claim 4, The spacer may be formed of a material having an etch selectivity with respect to the sacrificial layer, the hard mask layer, and the etching target layer. 5. The method of claim 4, Forming the mask layer, Applying a layer of RELACS material on the semiconductor substrate having a first pattern formed thereon; Performing heat treatment on the RELACS material layer; And Removing the heat-treated layer of the RELACS material by a predetermined thickness. The method of claim 8, In the step of removing the thickness of the RELACS material layer, Remove the thickness of the RELACS material layer using a developer, or And removing the RELACS material layer by a chemical mechanical polishing (CMP) process.
KR1020090127105A 2009-12-18 2009-12-18 Method for forming pattern in semiconductor device KR20110070317A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090127105A KR20110070317A (en) 2009-12-18 2009-12-18 Method for forming pattern in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090127105A KR20110070317A (en) 2009-12-18 2009-12-18 Method for forming pattern in semiconductor device

Publications (1)

Publication Number Publication Date
KR20110070317A true KR20110070317A (en) 2011-06-24

Family

ID=44401855

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090127105A KR20110070317A (en) 2009-12-18 2009-12-18 Method for forming pattern in semiconductor device

Country Status (1)

Country Link
KR (1) KR20110070317A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140083559A (en) * 2012-12-26 2014-07-04 에스케이하이닉스 주식회사 Method for manufacturing semiconductor devie

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140083559A (en) * 2012-12-26 2014-07-04 에스케이하이닉스 주식회사 Method for manufacturing semiconductor devie

Similar Documents

Publication Publication Date Title
US7968467B2 (en) Method for forming patterns in semiconductor memory device
KR101004691B1 (en) Method for forming micropattern in semiconductor device
CN109545684B (en) Semiconductor structure and forming method thereof
KR101576335B1 (en) Method for integrated circuit patterning
US7563712B2 (en) Method of forming micro pattern in semiconductor device
US7919414B2 (en) Method for forming fine patterns in semiconductor device
US7384874B2 (en) Method of forming hardmask pattern of semiconductor device
JP2009071306A (en) Method for forming micropattern in semiconductor device
US7687403B2 (en) Method of manufacturing flash memory device
JP2006303403A (en) Flash memory element manufacturing method
US9324577B2 (en) Modified self-aligned contact process and semiconductor device
TWI567785B (en) Method for fabricating patterned structure of semiconductor device
US10032664B2 (en) Methods for patterning a target layer through fosse trenches using reverse sacrificial spacer lithography
KR20070113604A (en) Method for forming micro pattern of semiconductor device
KR20110070317A (en) Method for forming pattern in semiconductor device
KR100875653B1 (en) Method of forming fine pattern of semiconductor device
US8940641B1 (en) Methods for fabricating integrated circuits with improved patterning schemes
US8524608B1 (en) Method for fabricating a patterned structure of a semiconductor device
KR20110077484A (en) Method of forming fine pattern for semicondutor device
TWI621210B (en) Method for fabricating semiconductor device
KR100912958B1 (en) Method for fabricating fine pattern in semiconductor device
KR101113768B1 (en) Method for manufacturing semiconductor device using dual damascene process
KR100466026B1 (en) Method for manufacturing conducting layer pattern on the semiconductor device
TWI449085B (en) Process for semiconductor device
TWI697032B (en) Method of fabricating semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination