KR20110070165A - Organic light emitting diode - Google Patents

Abstract

The present invention relates to an organic light emitting display device, and more particularly, to an organic light emitting display device for preventing degradation in a specific region of the organic light emitting display device.

A feature of the present invention is to form a power connection wiring crossing the data link wiring in the direction parallel to the gate wiring between the power pad electrode and the power wiring in the data and power link portion of the OLED.

As a result, the current transferred from the power pad unit to the plurality of power wires is dispersed in the specific area through the power connection wires, and is dispersed, thereby preventing temperature rise and deterioration thereof in the specific area.

This prevents a local temperature rise on the panel, which in turn prevents the problem that the characteristics of the device change or decrease due to deterioration through the temperature rise of the OLED.

OLED, deterioration, power wiring, power pad part

Description

Organic electroluminescent device

The present invention relates to an organic light emitting display device, and more particularly, to an organic light emitting display device for preventing degradation in a specific region of the organic light emitting display device.

Until recently, cathode ray tubes (CRT) have been mainly used as display devices. However, in recent years, flat panel such as plasma display panel (PDP), liquid crystal display device (LCD), organic electro-luminescence device (OLED), which can replace CRT Display devices are widely researched and used.

Among the flat panel display devices as described above, the organic light emitting display device (hereinafter referred to as OLED) is a self-light emitting device, and since the backlight used in the liquid crystal display device which is a non-light emitting device is not necessary, a light weight can be achieved.

In addition, the viewing angle and contrast ratio are superior to the liquid crystal display device, and it is advantageous in terms of power consumption, it is possible to drive the DC low voltage, the response speed is fast, and the internal components are solid, so it is strong against external shock, and the operating temperature range is also high. It has a wide range of advantages.

In particular, since the manufacturing process is simple, there is an advantage that can reduce the production cost more than the conventional liquid crystal display device.

OLEDs having these characteristics are largely divided into a passive matrix type and an active matrix type. The passive matrix type constitutes a device in a matrix form while crossing a signal line, whereas an active matrix type is a pixel. A thin film transistor, which is a switching element that turns on / off, is positioned for each pixel area.

In recent years, the passive matrix type has many limited elements such as resolution, power consumption, and lifespan. Accordingly, active matrix type OLEDs capable of realizing high resolution and large screens have been actively studied.

1 is a circuit diagram of one pixel area of a general active matrix OLED.

Each pixel area P includes a switching thin film transistor STr, a driving thin film transistor DTr, and a storage capacitor StgC.

In more detail, the gate wiring GL is formed in a first direction, and extends in a second direction crossing the first direction to define the pixel region P together with the gate wiring GL. The wiring DL is formed, and the power supply wiring PL is spaced apart from the data wiring DL to apply a power supply voltage.

In each pixel area P, a switching thin film transistor STr connected to the two wires is formed at a portion where the gate wiring GL and the data wiring DL intersect, and the switching thin film transistor STr is a driving thin film transistor ST. DTr) and the storage capacitor StgC, and the driving thin film transistor DTr is connected between the power supply line PL and the organic light emitting diode E.

That is, the first electrode, which is one terminal of the organic light emitting diode E, is connected to the drain electrode of the driving thin film transistor DTr, and the second electrode, which is the other terminal, is grounded. At this time, the power supply line PL transfers the power supply voltage to the organic light emitting diode E.

Therefore, when a signal is applied to each pixel area P through the gate line GL, the switching thin film transistor STr is turned on for each pixel area P, and the signal of the data line DL is driven. Since the driving thin film transistor DTr is turned on by being transferred to the gate electrode of the thin film transistor DTr, light is output through the organic light emitting diode E.

In the above-described configuration, a gate pad portion (not shown) for applying a signal to the gate wiring GL, a data pad portion (not shown) for applying a signal to the data wiring DL, and a power supply wiring PL are disposed outside the substrate. A power pad unit (not shown) for applying a signal is provided.

At this time, the power pad unit (not shown) is formed on one side or both sides of the data pad unit (not shown), and supplies the power voltage to each pixel region P. This operation is a problem when the OLED has a small area. If the signal flows in one direction as the driving method without a large area increases, a non-uniformity of image quality due to a resistance deviation occurs.

That is, in a process in which currents received from the outside are transferred to a plurality of power wirings for each pixel region through a power pad unit (not shown), the power pad unit and the plurality of power supply units are instantaneously transmitted from the power pad unit to the plurality of power wirings. Current is concentrated in the area where the power wiring is connected.

This causes a local temperature rise on the panel. This results in an increase in the temperature of the OLED, thereby causing a problem of changing or lowering the characteristics of the device due to deterioration.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a first object of the present invention is to disperse the amount of current concentrated in a power pad of an organic light emitting display device.

Through this, the second object is to improve the reliability of the OLED and the characteristics of the device.

In order to achieve the above object, the present invention provides a plurality of pixel regions defined through gate and data wirings crossing each other, a power supply wiring, a switching thin film transistor connected to the gate and data wiring, and a switching thin film transistor. A display area including a connected driving thin film transistor and a first organic light emitting diode; A data pad unit having a data pad electrode for applying a signal to the data line outside the display area, and a data link line for connecting the data pad electrode to the data line; A power pad unit having a power pad electrode for applying a signal to the power wires outside the display area, and a power link unit having a power connection wire connected to the power pad electrode through a power link wire; An organic light emitting display device includes an insulating layer formed between the data link wiring and the power connection wiring.

The power connection wiring is formed to cross the data link wiring in a direction parallel to the gate wiring, and the power wiring is branched from the power connection wiring.

And a gate pad portion formed outside the display area that is not parallel to the data pad portion and having a gate pad electrode for applying a signal to the gate line, and a gate link connecting the gate pad electrode and the gate line. The wiring line includes a gate link unit, wherein the data line and the power line are spaced apart from each other in parallel with each other, and an insulating film is formed between the data line and the power line.

In the organic light emitting display device according to the present invention, a plurality of power pad portions are formed from the power pad portion by forming a power connection wiring crossing the data link wiring in a direction parallel to the gate wiring between the power pad electrode and the power wiring. The electric current transmitted to the power wiring is dispersed in the specific region through the power connection wiring, and thus, the temperature rise and the deterioration due to the specific region can be prevented.

This prevents the local temperature rise on the panel, which has the effect of preventing the problem that the characteristics of the device is changed or degraded due to degradation through the temperature rise of the OLED.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a schematic diagram of an OLED according to an embodiment of the present invention.

As shown in the figure, on the substrate 101 of the OLED 100, in the display area AA for displaying an image, a plurality of gate wirings GL are formed extending in the first direction and intersect with the first direction. The data line DL is formed along with the gate line GL to define the pixel region P. The power line PL is spaced apart from the data line DL to apply a power voltage. ) Is formed.

In each pixel area P, a switching thin film transistor STr connected to the two wirings is formed at a portion where the gate wiring GL and the data wiring DL intersect each other, and the switching thin film transistor STr is a driving thin film. The transistor DTr and the storage capacitor StgC are connected to each other, and the driving thin film transistor DTr is connected between the power supply line PL and the organic light emitting diode E.

That is, the first electrode, which is one terminal of the organic light emitting diode E, is connected to the drain electrode of the driving thin film transistor DTr, and the second electrode, which is the other terminal, is grounded. At this time, the power supply line PL transfers the power supply voltage to the organic light emitting diode E.

On the other hand, in the non-display area NA outside the display area AA, a gate pad part GPA, which is a group of gate pads formed at one end of the plurality of gate wirings GL, is formed, and the gate pad part GPA is provided. The other side of the substrate 101 that is not parallel to the ()) is a data pad unit (DPA) that is a group of a plurality of data pads connected to the ends of the plurality of data lines (DL).

Here, the gate pad part GPA applies a gate signal to the gate wiring GL, and the data pad part DPA applies a data path for one horizontal line in synchronization with the gate signal through the data wiring DL. .

The gate and data pad units GPA and DPA are electrically connected to the gate line GL and the data line DL through the gate and the data link lines 221 and 121, respectively.

Therefore, when a signal is applied to each pixel area P through the gate line GL, the switching thin film transistor STr is turned on for each pixel area P, and the signal of the data line DL is driven. Since the driving thin film transistor DTr is turned on by being transferred to the gate electrode of the thin film transistor DTr, light is output through the organic light emitting diode E.

At this time, when the driving thin film transistor DTr is turned on, the level of the current flowing from the power supply line PL to the organic light emitting diode E is determined. As a result, the organic light emitting diode E is gray. Gray scale can be implemented.

The storage capacitor StgC plays a role of maintaining a constant gate voltage of the driving thin film transistor DTr when the switching thin film transistor STr is turned off, so that the switching thin film transistor STr is turned off. Even in the off state, the level of the current flowing through the organic light emitting diode E can be kept constant until the next frame.

At this time, as the most characteristic part of the present invention, in the non-display area NA of the substrate 101 parallel to the data pad part DPA, a power pad part VPA for applying a power voltage to the power supply wiring PL is provided. The power pad unit VPA is electrically connected to the plurality of power lines PL through a power connection line 140 formed to cross the data link line 121 in a direction parallel to the gate line GL.

Here, the power pad unit VPA is connected to the power connection wiring 140 through the power link wiring 131, and the plurality of power wiring PL has a structure branched from the power connection wiring 140.

Through this, in the process of transferring current from the power pad unit VPA to the plurality of power lines PL, it is possible to prevent the local temperature rise on the panel as the current is concentrated.

This consequently prevents the problem of temperature rise of the OLED 100 and changes or decreases in the characteristics of the device.

Looking at this in more detail, the conventional OLED 100 is a plurality of power wiring from the power pad unit (VPA) in the process of the current coming from the outside is transferred to the plurality of power wiring (PL) through the power pad unit (VPA). At the moment when power is delivered to PL, a problem occurs in which current is concentrated in a region where the power pad unit VPA and the plurality of power lines PL are connected.

This causes a local temperature rise on the panel. As a result, the temperature of the OLED 100 is increased, thereby causing a problem of changing or decreasing the characteristics of the device due to deterioration.

However, the OLED 100 of the present invention further includes a power connection wiring 140 between the power pad unit VPA and the plurality of power wirings PL, and the plurality of power wirings PL is connected to the power supply wiring 140. By applying a current through), it is to prevent such a problem caused by the current is applied to a plurality of power wiring (PL) directly from the power pad unit (VPA).

That is, in the OLED 100 of the present invention, the current transferred from the power pad unit VPA to the plurality of power wirings PL is not concentrated in a specific region through the power connection wiring 140, and the power connection wiring 140 is performed. By being dispersed through, it is possible to prevent the temperature rise and deterioration due to the specific region.

3 is an enlarged plan view illustrating a structure in which the data pad electrode and the power pad electrode of FIG. 2 are connected to each of the data wires and the power wires.

As shown, the OLED (100 in FIG. 2) according to the embodiment of the present invention has a display area AA for displaying an image in the center and a non-display area NA outside thereof.

In the display area AA, a plurality of gate lines GL and a plurality of data lines DL intersect to define a pixel area P, and are spaced apart from the plurality of data lines DL in parallel with each other. The wiring PL is formed.

In this case, each pixel region P is connected to the gate line GL and the power line PL, and includes a source layer and a drain electrode (not shown) spaced apart from each other. A driving thin film transistor DTr is formed as an element.

In this case, the gate wiring GL is connected to the gate electrode (not shown), and the power supply wiring PL is connected to the source electrode (not shown).

The drain electrode of the driving thin film transistor DTr is connected to the first electrode of the organic light emitting diode (E of FIG. 2) through a contact hole (not shown).

The non-display area NA on the outside of the display area AA includes a gate pad part (not shown) having a gate pad electrode (not shown) connected to an external driving circuit on one side thereof and an external driving circuit on the other side thereof. And a data pad part DPA having a data pad electrode 120 connected thereto.

At this time, in the gate and data link unit (not shown, DLA) positioned between the display area AA and the gate and data pad unit (not shown, DPA), each gate pad electrode (not shown) and data pad electrode are shown. Gate and data link wirings (not shown) connected to the 120 and connected to the gate wiring GL in the first direction and the data wiring DL in the second direction perpendicular to the first direction, respectively, formed in the display area AA. , 121).

In addition, a power pad unit VPA having a power pad electrode 130 connected to an external driving circuit is located at one side of the data pad unit DPA, and a power source is disposed between the display area AA and the power pad unit VPA. The link unit VLA is positioned, and the power link unit VLA has a power link wiring 131 connected to the power pad electrode 130 and the power line PL formed in the display area AA.

In particular, in the OLED (100 of FIG. 2) of the present invention, a power connection wiring 140 is formed between the power link wiring 131 and the power wiring PL.

That is, the power connection wiring 140 is formed in the data link unit DLA and the power link unit VLA to cross the data link wiring 121 in a direction parallel to the gate wiring GL, and each pixel area P The power supply wiring PL formed by stars is formed in a structure branched from the power connection wiring 140.

Therefore, the current transferred from the power pad unit VPA to the plurality of power wirings PL is not concentrated in a specific area through the power connection wiring 140, but is distributed through the power connection wiring 140. Temperature rise and thereby deterioration can be prevented.

This prevents a local temperature rise on the panel, which in turn prevents the problem of changing or deteriorating the characteristics of the device due to degradation through the temperature rise of the OLED (100 in FIG. 2).

Next, the interlayer structure of the OLED according to the present invention will be described in more detail with reference to FIG. 4.

4 is a cross-sectional view taken along the cutting lines IV-IV and V-V of FIG. 3 and is a cross-sectional view of a portion of one pixel area including a driving thin film transistor in the display area, and includes a power connection wiring. Sectional drawing which cut | disconnected a part of data link part and power link part.

As shown, a semiconductor layer 103 is formed in the pixel region P on the substrate 101. The semiconductor layer 103 is made of silicon, and the center portion of the semiconductor region 103 is formed of an active region 103a and a active region (channel). 103a) Source and drain regions 103b and 103c doped with a high concentration of impurities on both sides.

The gate insulating layer 107 is formed on the semiconductor layer 103 and the data and power link units DLA and VLA.

A gate electrode 105 and a gate wiring extending in one direction are formed on the gate insulating film 107 in the pixel region P to correspond to the active region 103a of the semiconductor layer 103, although not shown in the drawing. .

In addition, an upper portion of the gate insulating layer 107 of the data link unit and the power link units DLA and VLA is connected to the power line wiring (PL in FIG. 3), and the power connection wiring line is made of the same material as the gate wiring line (GL in FIG. 3). 140 is formed.

At this time, although not shown in the drawing, the power wiring (PL in FIG. 3) of the pixel region P has a structure branched from the power connecting wiring 140, and the same material in the same process as the power connecting wiring 140. Is formed.

In addition, a first interlayer insulating film 109a is formed on the entire surface of the substrate 101 including the gate electrode 105, the gate wiring (GL in FIG. 3), and the power connection wiring 140. 109a and the lower gate insulating layer 107 include first and second semiconductor layer contact holes 111a and 111b exposing source and drain regions 103b and 103c located on both sides of the active region 103a, respectively. .

Next, upper portions of the first interlayer insulating layer 109a including the first and second semiconductor layer contact holes 111a and 111b are spaced apart from each other and exposed through the first and second semiconductor layer contact holes 111a and 111b. Source and drain electrodes 113 and 115 are formed in contact with the source and drain regions 103b and 103c, respectively.

In addition, a data wiring DL intersecting with a lower gate wiring (GL in FIG. 3) is formed on the first interlayer insulating film 109a, and the first interlayer of the data link unit and the power link unit DLA and VLA is formed. The data link wiring 121 is formed on the insulating film 109a.

Thus, even though the data link wiring 121 and the power connection wiring 140 are formed to cross each other, the data link wiring 121 and the power connection wiring 140 are insulated from each other through the first interlayer insulating film 109a. The liver can prevent the short from occurring.

This, it can be seen that the power wiring (PL of FIG. 3) formed by branching from the power connection wiring 140 is also formed of a different material in a different layer from the data wiring DL, so that the power wiring (PL of FIG. 3) and Even if the data wirings DL are located adjacent to each other, shorts are prevented from occurring.

A second interlayer insulating film 109b having a drain contact hole 117 exposing the source and drain electrodes 113 and 115 and the data link wiring 121 to expose the drain electrode 115 is formed.

In this case, the semiconductor layer 103 including the source and drain electrodes 113 and 115 and the source and drain regions 103b and 103c in contact with the electrodes 113 and 115 and the gate insulating layer formed on the semiconductor layer 103 are formed. 107 and the gate electrode 105 form a driving thin film transistor DTr.

Although not shown in the drawing, the switching thin film transistor (not shown) has the same structure as the driving thin film transistor DTr and is connected to the driving thin film transistor DTr.

In addition, the switching and driving thin film transistor (DTr) shows, as an example, a top gate type in which the semiconductor layer 103 is formed of a polysilicon semiconductor layer. As a variation thereof, amorphous and pure impurities are used. It may be formed of a bottom gate type made of silicon.

In addition, the first electrode 211, the organic light emitting layer 213, and the second electrode constituting the organic light emitting diode E are located in an area of the pixel region P, which is substantially over the second interlayer insulating film 109b. The electrodes 215 are formed sequentially.

The first and second electrodes 211 and 215 and the organic light emitting layer 213 formed therebetween form an organic light emitting diode (E).

The first electrode 211 is connected to the drain electrode 115 of the driving thin film transistor DTr.

In this case, the first electrode 211 is preferably formed of indium tin oxide (ITO), which is a material having a relatively high work function value to serve as an anode electrode.

In addition, the second electrode 215 is made of aluminum (Al) or aluminum alloy (AlNd), which is a metal material having a relatively low work function in order to serve as a cathode.

Therefore, the light emitted from the organic light emitting layer 213 is driven by the bottom emission method emitted toward the first electrode 211.

In addition, the organic light emitting layer 213 may be composed of a single layer made of a light emitting material, and in order to increase the light emitting efficiency, a hole injection layer, a hole transporting layer, a light emitting layer, an emitting material layer, It may be composed of multiple layers of an electron transporting layer and an electron injection layer.

When a predetermined voltage is applied to the first electrode 211 and the second electrode 215 according to the selected color signal, the OLED 100 may be formed from holes and second electrodes 215 injected from the first electrode 211. The applied electrons are transported to the organic light emitting layer 213 to form excitons, and when such excitons transition from the excited state to the ground state, light is generated and emitted in the form of visible light.

At this time, since the emitted light passes through the transparent first electrode 211 to the outside, the OLED 100 implements an arbitrary image.

The first electrode 211 is formed for each pixel region P, and a bank 118 is positioned between the first electrodes 211 formed for each pixel region P. FIG.

That is, the bank 118 is formed in a matrix type with a lattice structure as a whole, and the first electrode 211 is separated by pixel area P with the bank 118 as a boundary for each pixel area P. FIG. It is formed into a structure.

Thereafter, the OLED 100 completed as described above is finally completed through an encapsulation process.

The OLED 100 having the structure as described above has a gate wiring (FIG. 3) between the power pad electrode (130 in FIG. 3) and the power wiring (PL in FIG. 3) in the data and power link units DLA and VLA. Current to be transferred from the power pad unit (VPA in FIG. 3) to the plurality of power wirings (PL in FIG. 3) by forming the power connection wiring 140 crossing the data link wiring 121 in a direction parallel to GL). It can be seen that the structure is able to prevent the temperature rise and deterioration due to the temperature in the specific region by being distributed through the power connection wiring 140, rather than being concentrated in a specific region through the power connection wiring 140.

This prevents a local temperature rise on the panel, which in turn prevents the problem that the characteristics of the device change or decrease due to deterioration through the temperature rise of the OLED 100.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

1 is a circuit diagram of one pixel of a typical active matrix OLED.

2 is a schematic diagram of an OLED according to an embodiment of the invention.

3 is an enlarged plan view illustrating a structure in which the data pad electrode and the power pad electrode of FIG. 2 are connected to each data line and the power line;

4 is a cross-sectional view taken along lines IV-IV and V-V of FIG. 3.

Claims (5)

A plurality of pixel areas defined through gates and data lines crossing each other, a power line, a switching thin film transistor connected to the gate and data wiring, a driving thin film transistor connected to the switching thin film transistor, and a first organic light emitting diode A display area comprising; A data pad portion having a data pad electrode for applying a signal to the data wiring outside the display area, and a data link portion having a data link wiring connecting the data pad electrode and the data wiring; A power pad unit having a power pad electrode for applying a signal to the power wires outside the display area, and a power link unit having a power connection wire connected to the power pad electrode through a power link wire; An insulating film formed between the data link wiring and the power connection wiring Organic electroluminescent device comprising a. The method of claim 1, And the power connection line is formed to intersect the data link line in a direction parallel to the gate line. The method of claim 1, The power wiring is an organic light emitting device branched from the power connection wiring. The method of claim 1, A gate pad portion formed outside the display area that is not parallel to the data pad portion and having a gate pad electrode for applying a signal to the gate line, and a gate link wiring connecting the gate pad electrode and the gate line to each other; An organic light emitting display device comprising a gate link portion formed. The method of claim 1, And the data line and the power line are spaced apart from each other in parallel with each other, and an insulating film is formed between the data line and the power line.

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