KR20110067759A - Imd fabrication method for semiconductor device - Google Patents

Imd fabrication method for semiconductor device Download PDF

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KR20110067759A
KR20110067759A KR1020090124485A KR20090124485A KR20110067759A KR 20110067759 A KR20110067759 A KR 20110067759A KR 1020090124485 A KR1020090124485 A KR 1020090124485A KR 20090124485 A KR20090124485 A KR 20090124485A KR 20110067759 A KR20110067759 A KR 20110067759A
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metal
interlayer insulating
insulating film
forming
semiconductor device
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KR1020090124485A
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Korean (ko)
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권성수
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: An IMD fabrication method for a semiconductor device is provided to implement mechanically reinforced structure while having low dielectric constant by forming an air cap in an interlayer insulating film. CONSTITUTION: In an IMD(Inter Metal Dielectric) fabrication method for a semiconductor device, a metal wirings and via are formed on the semiconductor substrate and a metal guard(170) is formed at the same time. The IMD(200) has a deep silicon via and penetration silicon via therein. An air cap is formed by removing IMD between metal wires through the deep silicon via. A silicon thin film is laminated on the inter-layer insulating film including the air gap. The via plug(260) is formed on the penetration silicon via and metal wiring through a metal gapfill process.

Description

에어갭을 이용한 반도체 소자의 층간절연막 형성방법{IMD fabrication method for semiconductor device}Interlayer insulating film formation method of semiconductor device using air gap {IMD fabrication method for semiconductor device}

본 발명은 반도체 소자의 층간 절연막 형성방법에 관한 것으로, 보다 자세하게는 에어갭을 이용하여 반도체 소자의 층간 절연막을 형성하는 방법에 관한 것이다. The present invention relates to a method of forming an interlayer insulating film of a semiconductor device, and more particularly, to a method of forming an interlayer insulating film of a semiconductor device using an air gap.

최근 들어, 반도체 소자의 집적도를 높이기 위한 기술로서, 다층으로 된 구조의 각 층에 금속 배선을 형성하거나, 동일 층상에서 금속 배선과 금속 배선 사이의 간격을 좁게 하는 방식을 채택하고 있다. In recent years, as a technique for increasing the degree of integration of semiconductor devices, a method of forming metal wirings in each layer of a multilayer structure or narrowing the gap between metal wirings and metal wirings on the same layer has been adopted.

이렇게 금속 배선 사이의 간격이 좁아지면서 동일 층상에서 서로 인접한 금속 배선 사이 또는 상하로 인접한 각 금속 배선층 사이에 존재하는 기생 저항 및 기생 캐패시턴스를 다루는 문제가 가장 중요하게 대두되고 있다. As the gap between the metal wires is narrowed, the problem of dealing with the parasitic resistance and parasitic capacitance existing between the adjacent metal wires on the same layer or between the metal wire layers adjacent to each other up and down is most important.

즉, 초 고집적 반도체 소자의 경우, 다층 금속 배선 구조에 존재하는 이러한 기생 저항 및 기생 캐패시턴스 성분들이 RC(Resistance Capacitance)에 의해 유도되는 지연(delay)에 의하여 소자의 전기적 특성을 열화시키고, 더 나아가 반도체 소자의 전력 소모량과 신호 누설량을 증가시킬 수 있다. That is, in the case of ultra-highly integrated semiconductor devices, the parasitic resistance and parasitic capacitance components present in the multi-layered metal interconnection structure deteriorate the electrical characteristics of the device due to the delay induced by RC (Resistance Capacitance). The device's power consumption and signal leakage can be increased.

따라서, 초 고집적 반도체 소자에 있어서 RC값이 작은 다층 금속 배선 기술을 개발하는 것이 매우 중요한 문제로 대두되고 있는데, RC값이 작은 고성능의 다층 금속 배선 구조를 형성하기 위해서는 비저항이 낮은 금속을 사용하여 배선층을 형성하거나, 유전율이 낮은 절연막을 사용할 필요가 있다. Therefore, it is very important to develop a multi-layered metal wiring technology having a small RC value in an ultra-high density semiconductor device. In order to form a high-performance multi-layered metal wiring structure having a small RC value, a wiring layer using a low resistivity metal is used. It is necessary to form a film or to use an insulating film having a low dielectric constant.

이러한 필요성에 의해, 캐패시턴스를 줄이기 위한 낮은 유전상수를 갖는 물질(low K material), 예를 들면, 기존의 TEOS 계열의 산화에서 SiO 계열의 낮은 유전 상수 물질에 대한 연구가 진행되고는 있으나, 현재 확실한 저유전 물질이 선택되지 않아 실제 공정에 적용하기에는 많은 어려움이 있다. Due to this necessity, research is being conducted on low K materials for reducing capacitance, for example, low dielectric constant materials of SiO series in the oxidation of existing TEOS series. Since low dielectric materials are not selected, there are many difficulties in applying them in the actual process.

본 발명이 이루고자 하는 기술적 과제는, 층간 절연막에 에어갭을 형성하여 종래의 층간절연막에 비하여 낮은 유전율을 가지면서 기계적으로 강화된 구조를 갖는 반도체 소자의 층간절연막 형성방법을 제공하는데 있다. An object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device having a mechanically strengthened structure with a low dielectric constant compared to the conventional interlayer insulating film by forming an air gap in the interlayer insulating film.

본 발명의 에어갭을 이용한 반도체 소자의 층간절연막 형성방법은 반도체 기판 상에 금속 배선들 및 비아들을 형성함과 동시에 메탈 가드를 형성하는 단계와, 금속배선들, 비아들 및 메탈 가드를 포함하여 형성된 층간 절연막 내에 딥 실리콘 비아 및 관통 실리콘 비아를 형성하는 단계와, 딥 실리콘 비아를 통해 금속 배선들 사이의 층간 절연막을 제거하여 에어 갭을 형성하는 단계와, 에어갭을 포함하는 층간 절연막 상에 실리콘 박막을 적층하는 단계 및 관통 실리콘 비아 및 상위 금속 배선 상에 메탈 갭필 공정을 통해 비아 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다. In the method of forming an interlayer dielectric layer of a semiconductor device using an air gap, the method may include forming metal guards and simultaneously forming metal guards and vias on a semiconductor substrate, and including metal interconnects, vias, and metal guards. Forming a deep silicon via and a through silicon via in the interlayer insulating film; forming an air gap by removing the interlayer insulating film between the metal lines through the deep silicon via; and forming a silicon thin film on the interlayer insulating film including the air gap. And forming a via plug through a metal gapfill process on the through silicon via and the upper metal wiring.

이상에서 설명한 바와 같이, 본 발명에 의한 에어갭을 이용한 반도체 소자의 층간절연막 형성방법은 반도체 소자의 크기가 작아지면서 메탈과 메탈을 격리시켜주는 층간절연막의 두께가 얇아짐에 따라 나타나는 상부 메탈과 하부 메탈간의 간섭을 최대한 억제하기 위해, 층간 절연막 내에 딥 실리콘 비아(deep silicon via)를 형성하여 상기 딥 실리콘 비아를 통해 상기 층간절연막을 제거하여 유전율이 1 인 공기를 에어 갭으로 사용함으로써, 초고집적 반도체 소자에 있어서 다층 콘택 구조에서 발생하는 기생 캐패시턴스를 확실히 줄일 수 있는 효과가 있다. As described above, in the method of forming the interlayer insulating film of the semiconductor device using the air gap according to the present invention, the upper metal and the lower metal which appear as the size of the semiconductor device becomes smaller and the thickness of the interlayer insulating film separating the metal from the metal becomes thinner. In order to suppress interference between metals as much as possible, a deep silicon via is formed in the interlayer insulating film, and the interlayer insulating film is removed through the deep silicon via, thereby using air having a dielectric constant of 1 as an air gap, thereby providing a highly integrated semiconductor. In the device, there is an effect that the parasitic capacitance generated in the multilayer contact structure can be reliably reduced.

또한, 본 발명은 상기 상부 메탈 상에 실리콘 박막을 적층하여 상기 딥 실리콘 비아에 금속을 매립함으로써, 기계적으로 강화된 에어갭 층간 절연막을 제공할 수 있다. In addition, the present invention may provide a mechanically strengthened air gap interlayer insulating film by depositing a silicon thin film on the upper metal to fill a metal in the deep silicon via.

또한, 본 발명은 상기 하부 및 상부 메탈 형성시 동시에 메탈 가드(metal guard)를 동시에 형성하여 상기 층간 절연막 제거시 소자의 셀 지역만의 층간 절연막만을 제거함으로써, 추가적인 공정을 요하지 않고, 공정의 안정성을 기할 수 있는 효과를 갖는다. In addition, the present invention by forming a metal guard (metal guard) at the same time when forming the lower and upper metal at the same time to remove only the interlayer insulating film of the cell region of the device when removing the interlayer insulating film, does not require an additional process, the stability of the process It has a measurable effect.

이하, 본 발명에 의한 반도체 소자의 층간절연막 형성방법의 실시예를 첨부한 도면들을 참조하여 다음과 같이 설명한다.Hereinafter, an embodiment of a method for forming an interlayer insulating film of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

도 1a 내지 도 1e들은 본 발명에 의한 반도체 소자의 층간절연막 형성방법을 설명하기 위한 공정 단면도들이다.1A to 1E are cross-sectional views illustrating a method of forming an interlayer insulating film of a semiconductor device according to the present invention.

도 1a를 참조하면, 소정의 구조물이 형성된 기판(100) 상에 금속층을 형성하고 패터닝하여 제1 금속배선인 하부 금속 배선(110)을 형성한다. 하부 금속 배선(110)은 상기 소정의 구조물과 컨택(105)을 통해 전기적으로 연결된다. Referring to FIG. 1A, a metal layer is formed and patterned on a substrate 100 on which a predetermined structure is formed to form a lower metal wire 110 that is a first metal wire. The lower metal wire 110 is electrically connected to the predetermined structure through the contact 105.

하부 금속 배선(110)과 비아(130)를 통해 전기적으로 연결되는 제2 금속배선(140) 및 제2 금속배선(140)과 비아(150)를 통해 전기적으로 연결되는 제3 금속배선인 상위 금속 배선(160)을 형성한다.The upper metal that is the second metal wire 140 electrically connected through the lower metal wire 110 and the via 130 and the third metal wire electrically connected through the second metal wire 140 and the via 150. The wiring 160 is formed.

이때, 제1 금속배선(110), 제2 금속배선(140) 및 비아들(130, 150)을 형성함과 동시에 메탈 가드(170)를 형성한다. 메탈 가드(170)는 각 레이어 상의 상기 금속 배선들(110, 140) 또는 비아들(130, 150)을 형성하는 구성 성분과 동일한 성분으로 형성함이 바람직하다. In this case, the first metal wiring 110, the second metal wiring 140, and the vias 130 and 150 are formed and the metal guard 170 is formed. The metal guard 170 is preferably formed of the same component as the component forming the metal wires 110 and 140 or the vias 130 and 150 on each layer.

제1 금속배선(110), 제2 금속배선(140) 및 제3 금속배선(160)은 알루미늄(Al), 구리(Cu) 또는 알루미늄 구리 합금(AlCu) 중 어느 하나로 형성할 수 있다.The first metal wire 110, the second metal wire 140, and the third metal wire 160 may be formed of any one of aluminum (Al), copper (Cu), or aluminum copper alloy (AlCu).

메탈 가드(170)는 후속 공정에서 층간 절연막을 식각할 때 식각하고자 하는 소자의 셀(cell) 지역 내의 층간 절연막만을 제거하기 위한 방어벽 기능을 한다.The metal guard 170 functions as a protective barrier to remove only the interlayer insulating layer in the cell region of the device to be etched when etching the interlayer insulating layer in a subsequent process.

본 발명은 금속배선들(110, 140) 및 비아들(130, 150)을 형성함과 동시에 메탈 가드(metal guard)를 형성함으로써, 추가적인 공정없이 차후 층간 절연막(200)을 제거하여 에어갭을 형성할 때 소자의 셀 지역만의 층간 절연막(200)만을 제거하도록 한다. The present invention forms the metal wires 110 and 140 and the vias 130 and 150, and simultaneously forms a metal guard, thereby removing the interlayer insulating film 200 to form an air gap without further processing. In this case, only the interlayer insulating layer 200 in the cell region of the device is removed.

제1 금속 배선(110) 내지 제3 금속배선(160)이 형성되어 있는 각 레이어 상에 상기 금속 배선들 간을 절연시키기 위한 층간 절연막(IMD막:Inter metal dielectric, 200)을 형성한다. An interlayer dielectric (IMD film: Inter metal dielectric, 200) is formed on each layer where the first metal wiring 110 to the third metal wiring 160 is formed to insulate the metal wirings from each other.

도 1b를 참조하면, 층간 절연막(200) 상에 감광막을 도포하고 상기 감광막을 패턴화하여 상기 감광막 패턴(미도시)을 마스크로 층간 절연막(200)의 일부분을 식각함으로써 딥 실리콘 비아(deep silicon via)를 형성한다.Referring to FIG. 1B, a deep silicon via is formed by applying a photoresist film on the interlayer insulating film 200 and patterning the photoresist to etch a portion of the interlayer insulating film 200 using the photoresist pattern (not shown) as a mask. ).

본원 발명에서는 딥 실리콘 비아를 추후 전원전압 또는 접지전압 신호와의 연결을 위한 관통 실리콘 비아(210) 및 층간 절연막(200) 제거용 딥 실리콘 비 아(220)로 형성함을 예로 든다. In the present invention, for example, the deep silicon via is formed of a through silicon via 210 and a deep silicon via 220 for removing the interlayer insulating layer 200 for connection with a power supply voltage or a ground voltage signal.

도 1c를 참조하면, 딥 실리콘 비아(220)를 통하여 화학적 식각(Chemical etch)을 이용하여 층간 절연막(200)의 소정 영역을 제거한다. 즉, 제1 금속배선(110), 제2 금속배선(140) 및 제3 금속배선(160) 사이의 층간 절연막을 제거하여유전율이 1인 공기를 에어 갭(300)을 형성한다. Referring to FIG. 1C, a predetermined region of the interlayer insulating layer 200 is removed by using chemical etching through the deep silicon vias 220. That is, the interlayer insulating film between the first metal wire 110, the second metal wire 140, and the third metal wire 160 is removed to form an air gap 300 for air having a dielectric constant of 1.

본 발명은 이와 같이 금속배선들 간의 층간 절연막을 제거하여 유전율이 1인 공기를 에어 갭(300)을 형성함으로써, 초고집적 반도체 소자에 있어서 다층 콘택 구조에서 발생하는 기생 캐패시턴스를 줄일 수 있다.The present invention can reduce the parasitic capacitance generated in the multilayer contact structure in the ultra-high density semiconductor device by removing the interlayer insulating film between the metal wirings to form an air gap 300 of air having a dielectric constant of 1.

도 1d를 참조하면, 상위 금속배선(160)을 포함하는 층간 절연막(200) 상에 실리콘 박막(240)을 적층한다. 실리콘 박막(240) 내에 비아(250, 260)를 형성하여 상위 금속 배선(160)을 노출시킬 수 있다. Referring to FIG. 1D, the silicon thin film 240 is stacked on the interlayer insulating layer 200 including the upper metal wiring 160. Vias 250 and 260 may be formed in the silicon thin film 240 to expose the upper metal wiring 160.

실리콘 박막(240)은 thin-silicon, pyrex 및 glass 중 어느 하나를 이용할 수 있다. The silicon thin film 240 may use any one of thin-silicon, pyrex, and glass.

본 발명은 에어갭(300)을 포함하는 층간 절연막(200)으로 인해 약해질 수 있는 구조물을 층간 절연막(200)상에 실리콘 박막(240)을 형성함으로써, 기계적으로 강화시킬 수 있다. According to the present invention, a structure that may be weakened by the interlayer insulating layer 200 including the air gap 300 may be mechanically strengthened by forming the silicon thin film 240 on the interlayer insulating layer 200.

도 1e를 참조하면, 관통 실리콘 비아(210) 및 비아(250)를 포함하는 반도체 기판(100) 상에 메탈 갭필(metal gap fill) 공정을 통해 외부 접속 단자와 전기적으로 연결되는 비아 플러그(260)를 형성한다. Referring to FIG. 1E, a via plug 260 electrically connected to an external connection terminal through a metal gap fill process on a semiconductor substrate 100 including a through silicon via 210 and a via 250. To form.

이로써, 금속 배선층 사이에 에어갭을 갖는 층간 절연막이 형성된다. As a result, an interlayer insulating film having an air gap is formed between the metal wiring layers.

이상에서 설명한 본 발명은 상술한 실시예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

도 1a 내지 도 1e는 본 발명에 의한 에어갭을 이용한 반도체 소자의 층간절연막 형성방법을 설명하기 위한 공정 단면도들이다. 1A to 1E are cross-sectional views illustrating a method of forming an interlayer insulating film of a semiconductor device using an air gap according to the present invention.

Claims (5)

반도체 기판 상에 금속 배선들 및 비아들을 형성함과 동시에 메탈 가드를 형성하는 단계;Forming a metal guard simultaneously with forming metal lines and vias on the semiconductor substrate; 상기 금속배선들, 비아들 및 메탈 가드를 포함하여 형성된 층간 절연막 내에 딥 실리콘 비아 및 관통 실리콘 비아를 형성하는 단계;Forming deep silicon vias and through silicon vias in the interlayer insulating film including the metal wires, vias, and metal guards; 상기 딥 실리콘 비아를 통해 상기 금속 배선들 사이의 상기 층간 절연막을 제거하여 에어 갭을 형성하는 단계;Forming an air gap by removing the interlayer insulating film between the metal wires through the deep silicon vias; 상기 에어 갭을 포함하는 상기 층간 절연막 상에 실리콘 박막을 적층하는 단계; 및Depositing a silicon thin film on the interlayer insulating film including the air gap; And 상기 관통 실리콘 비아 및 상위 상기 금속 배선 상에 메탈 갭필 공정을 통해 비아 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 에어갭을 이용한 반도체 소자의 층간절연막 형성방법.Forming a via plug on the through-silicon via and the upper metal wiring through a metal gap fill process. 제 1 항에 있어서,The method of claim 1, 상기 메탈 가드는 상기 금속 배선들 및 비아들을 형성하는 성분과 동일한 성분으로 형성함을 특징으로 하는 에어갭을 이용한 반도체 소자의 층간절연막 형성방법.And the metal guard is formed of the same component as the component forming the metal lines and the vias. 제1 항에 있어서, The method according to claim 1, 상기 메탈 가드는 상기 층간 절연막 제거시 식각하고자 하는 상기 층간 절연막만을 제거하기 위한 방어벽 기능을 하도록 형성하는 것을 특징으로 하는 에어갭을 이용한 반도체 소자의 층간절연막 형성방법.And the metal guard is formed to function as a barrier for removing only the interlayer insulating layer to be etched when the interlayer insulating layer is removed. 제1 항에 있어서,The method according to claim 1, 상기 층간 절연막은 화학적 식각(Chemical etch)으로 제거함을 특징으로 하는 에어갭을 이용한 반도체 소자의 층간절연막 형성방법. The interlayer insulating film is a method of forming an interlayer insulating film of a semiconductor device using an air gap, characterized in that for removing by chemical etching (Chemical etch). 제1 항에 있어서,The method according to claim 1, 상기 실리콘 박막은 thin-silicon, Pyrex 및 Glass 중 어느 하나를 이용하는 것을 특징으로 하는 에어갭을 이용한 반도체 소자의 층간절연막 형성방법. The silicon thin film is a method of forming an interlayer insulating film of a semiconductor device using an air gap, characterized in that using any one of thin-silicon, Pyrex and Glass.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9799606B2 (en) 2014-04-07 2017-10-24 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9847276B2 (en) 2013-11-20 2017-12-19 Samsung Electronics Co., Ltd. Semiconductor devices having through-electrodes and methods for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9847276B2 (en) 2013-11-20 2017-12-19 Samsung Electronics Co., Ltd. Semiconductor devices having through-electrodes and methods for fabricating the same
US9799606B2 (en) 2014-04-07 2017-10-24 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

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