KR20110066809A - Method of fabricating the array substrate for liquid crystal display device using a oxidized semiconductor - Google Patents

Abstract

PURPOSE: A method for manufacturing an array substrate for a liquid crystal display device is provided to reduce the manufacturing costs by reducing the number of parts. CONSTITUTION: A method for manufacturing an array substrate for a liquid crystal display device comprises steps of: forming a gate electrode, a storage capacitor lower patter, a common electrode patter, a pixel electrode patter, and a first pattern for a gate pad using a first mask process; forming a gate insulation pattern and a second oxidized semiconductor pattern on the substrate through a second mask process; forming a source electrode, a drain electrode, a storage capacitor upper electrode, a data line, a data pad, and a second pattern for a gate pad through a third mask process; forming a protective layer on the substrate; and forming a first and a second contacnnt hole which exposes the gate pad, and a data pad.

Description

Method of fabricating the array substrate for liquid crystal display device using a oxidized semiconductor}

The present invention relates to a method for manufacturing an array substrate for a liquid crystal display device, and more particularly, to a method for manufacturing an array substrate for a liquid crystal display device using an oxide semiconductor layer.

Recently, the importance of flat panel displays (FPDs) has increased with the development of multimedia. In response, various liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), light emitting devices (Light Emitting Devices), etc. Flat panel displays have been put into practical use.

Among them, the liquid crystal display device has better visibility than the cathode ray tube, the average power consumption and the heat generation amount are small, and the electroluminescent display device has a high response time with a response speed of 1 ms or less, low power consumption, Since it is self-luminous, there is no problem in viewing angle, and thus, it is attracting attention as a next-generation flat panel display.

There are two methods of driving a flat panel display device: a passive matrix method and an active matrix method using a thin film transistor. The passive matrix method forms the anode and the cathode to be orthogonal and selects and drives the lines, whereas the active matrix method connects the thin film transistors to each pixel electrode and drives them according to the voltage maintained by the capacitor capacitance connected to the gate electrode of the thin film transistor. That's the way it is.

In the thin film transistor for driving the flat panel display device, not only the characteristics of the basic thin film transistor such as mobility and leakage current, but also durability and electrical reliability for maintaining a long life is very important. Here, the semiconductor layer of the thin film transistor is mainly formed of amorphous silicon or polycrystalline silicon, the amorphous silicon has the advantage that the film forming process is simple and the production cost is low, but the electrical reliability is not secured. In addition, polycrystalline silicon is very difficult to apply a large area due to the high process temperature, there is a problem that the uniformity according to the crystallization method is not secured.

On the other hand, when the semiconductor layer is formed of oxide, high mobility can be obtained even when the film is formed at a low temperature, and since the resistance change is large according to the oxygen content, it is very easy to obtain the desired physical properties. It's attracting great attention. In particular, zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO4), or the like is exemplified.

The thin film transistor substrate using the oxide semiconductor layer is formed through a plurality of mask processes. One mask process includes a plurality of processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a strip process, and an inspection process.

However, as a large number of mask processes are required, the manufacturing process is complicated, which is a major cause of an increase in manufacturing cost of a flat panel display.

Accordingly, in the manufacturing process of the thin film transistor substrate using the oxide semiconductor layer, the first mask for forming source / drain electrodes, the second mask for forming a semiconductor layer, the third mask for forming a gate, the fourth mask for forming a contact hole, and the pixel A total of five mask processes are used as in the fifth mask process for forming electrodes, and a direction for further reducing the number of mask processes is required in the five mask processes.

An object of the present invention for solving the above problems is to provide a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer that can reduce the manufacturing cost by reducing the number of masks.

In order to achieve the above object, a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to the present invention includes a gate electrode, a storage capacitor lower pattern, a common electrode pattern, a pixel electrode pattern, Forming a first pattern for a gate pad, forming a gate insulating pattern and a second oxide semiconductor pattern on the substrate on which the first mask process is completed using a second mask process, and using a third mask process Forming a source electrode, a drain electrode, a storage capacitor upper electrode, a data line, a data pad, a gate pad, a common electrode, and a pixel electrode on the substrate on which the second mask process is completed, and the substrate on which the third mask process is completed. Forming a passivation layer on the passivation layer; And by performing a dry etching process and forming a first and second contact holes respectively exposing the gate pad and a data pad.

The gate electrode, the storage capacitor lower pattern, the common electrode pattern, the pixel electrode pattern, the first pattern for the gate pad, the source electrode, the drain electrode, the storage capacitor upper electrode, the data line, the data pad, the second pattern for the gate pad, and the common electrode. The pattern and the pixel electrode pattern are formed in a structure in which the first metal layer and the second metal layer are stacked.

Forming a gate insulating pattern and a second oxide semiconductor pattern on the substrate using the second mask process may include sequentially forming a gate insulating layer and an oxide semiconductor layer on the substrate, and forming a gate insulating pattern and an oxide semiconductor layer on the oxide semiconductor layer. Forming a first oxide semiconductor pattern and the gate insulating pattern by etching the oxide semiconductor layer and the gate insulating layer using the first photoresist pattern as an etch mask; Forming a second photoresist pattern by performing an ashing process on the resist pattern, and etching the first oxide semiconductor pattern using the second photoresist pattern as an etch mask to form the second oxide semiconductor pattern. .

The oxide semiconductor layer is formed of any one of ZnO, CdO, GaO, InO, InO, and SnO. The second mask uses a mask having three different transmittances.

Performing wet etching during the etching process of the oxide semiconductor layer using the first photoresist pattern and the second photoresist pattern as an etching mask, and performing dry etching during the etching process of the gate insulating layer using the first photoresist pattern as an etching mask. Perform.

In the common electrode pattern and the pixel electrode pattern stacked on the second metal layer and the first metal layer, the second metal layer is removed through the third mask process to form the common electrode and the pixel electrode.

The method of manufacturing the thin film transistor array substrate using the oxide semiconductor layer according to the present invention is performed through a three mask process, thereby reducing the manufacturing cost by reducing the number of masks than the five mask process.

Hereinafter, an embodiment of a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer will be described in detail with reference to the accompanying drawings.

1A and 1B are plan views and cross-sectional views illustrating a first mask process in a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to an embodiment of the present invention.

1A and 1B, a gate electrode 20a, a storage capacitor lower pattern 20b, a common electrode pattern 20c, and a pixel electrode pattern 20d are formed on a substrate 10 through a first mask process. The first pattern 20e for the gate pad is formed.

The substrate 10 may include a region G-Pad in which a gate pad is formed, a region D-Pad in which a data pad is formed, a region D-line in which a data line is formed, a pixel region PXL, The gate line is formed into a region G-line, a capacitor is formed Cst, and a thin film transistor region TFT is defined. Here, since the structure of the region G-line in which the gate line is formed and the region Cst in which the capacitor is formed is the same, it will be described by integrating into the regions G-line and Cst in which the gate line is formed.

The gate electrode 20a, the storage capacitor lower pattern 20b, the pixel electrode pattern 20c, the common electrode pattern 20d, and the first pattern 20e for the gate pad may include a first metal layer 21a and a second metal layer ( 21b) is laminated, the first metal layer 21a uses MoTi, and the second metal layer 21b uses Cu.

The gate electrode 20a, the storage capacitor lower pattern 20b, the pixel electrode pattern 20c, the common electrode pattern 20d, and the gate pad first pattern 20e may be formed of a first metal layer and a first layer on the substrate 10. 2 a metal layer and a photoresist are sequentially formed, and a photo process using a first mask is performed on the photoresist to form a first photoresist pattern (not shown), and the first metal layer and the second metal layer are formed using an etching mask. It is formed by etching.

The strip is formed on the substrate 10 on which the gate electrode 20a, the storage capacitor lower pattern 20b, the common electrode pattern 20d, the pixel electrode pattern 20c and the gate pad first pattern 20e are formed. The process is performed to remove the first photoresist pattern (not shown).

2A and 2B are plan and cross-sectional views illustrating a second mask process in a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to an embodiment of the present invention, and FIGS. 3A to 3D illustrate the second mask process. Sectional drawing for demonstrating concretely.

As shown in FIGS. 2A and 2B, the gate electrode 20a, the storage capacitor lower pattern 20b, the common electrode pattern 20c, the pixel electrode pattern 20d, and the gate pad first pattern 20e are formed. The gate insulating pattern 22b and the second oxide semiconductor pattern 24c are formed on the substrate 10 through a second mask process.

Specifically, as shown in FIG. 3A, a gate electrode 20a, a storage capacitor lower pattern 20b, a common electrode pattern 20c, a pixel electrode pattern 20d, and a gate pad first pattern 20e are formed. After the gate insulating layer 22a and the oxide semiconductor layer 24a are formed on the substrate 10, the second photoresist pattern 100a is formed on the oxide semiconductor layer 24a.

The oxide semiconductor layer 24a is formed of any one of ZnO, CdO, GaO, InO, InO, and SnO.

The second photoresist pattern 100a is formed by forming a photoresist on the oxide semiconductor layer 24a and performing a photolithography process using the second mask on the photoresist.

In this case, the mask uses a mask having three different transmittances, including a transmissive region for transmitting light, a transflective region for transmitting and blocking a portion of the light, and a blocking region for blocking the light. In this case, the semi-transmissive region is a region having a higher transmittance than the blocking region, and the thickness of the photoresist pattern in the semi-transmissive region formed through the photolithography process is lower than the thickness of the photoresist pattern in the blocking region.

Therefore, the blocking region is disposed in the region corresponding to the gate electrode of the region TFT in which the thin film transistor is formed, and the transmission region is disposed in the region G-Pad and pixel region PXL in which the gate pad is formed, and The transmission region is disposed in all of the remaining regions except the region in which the blocking region and the transmission region are disposed.

3B, the oxide semiconductor layer 24a and the gate insulating layer 22a are etched using the second photoresist pattern 100a formed on the substrate 10 as an etch mask. 24b) and the gate insulating pattern 22b are formed.

At this time, the wet etching is performed during the etching process of the oxide semiconductor layer 24a using the second photoresist pattern 100a, and the dry etching is performed during the etching process of the gate insulating film 22a using the second photoresist pattern 100a. Do this.

When the first oxide semiconductor pattern 24b and the gate insulating pattern 22b are formed by etching the second photoresist pattern 100a with an etching mask, the first pattern 20e for the gate pad and the common electrode pattern ( 20c), the pixel electrode pattern 20d is exposed.

As shown in FIG. 3C, the third photoresist pattern is formed by performing an ashing process on the substrate 10 on which the second photoresist pattern 100a, the first oxide semiconductor pattern 24b, and the gate insulation pattern 22b are formed. To form 100b.

Subsequently, the first oxide semiconductor pattern 24b is etched using the third photoresist pattern 100b as an etch mask to form a second oxide semiconductor pattern 24c.

In this case, a wet etching process may be performed during the etching process of the second oxide semiconductor pattern 24c using the third photoresist pattern 100b.

As shown in FIG. 3D, the gate insulating pattern 22b is removed by performing a strip process on the substrate 10 on which the second oxide semiconductor pattern 24c is formed to remove the third photoresist pattern 100b. And forming the second oxide semiconductor pattern 24c.

4A and 4B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to an embodiment of the present invention, and FIGS. 3 are cross-sectional views illustrating the mask process in detail.

As shown in FIGS. 4A and 4B, the source electrode 30a and the drain electrode 30b are formed on the substrate 10 on which the gate insulating pattern 22b and the second oxide semiconductor pattern 24c are formed through a third mask process. ), The storage capacitor upper electrode 30c, the data line 30d, the data pad 30e, the gate pads 20e / 30f, the common electrode 20cf, and the pixel electrode 20df are formed.

Specifically, as shown in FIG. 5A, after the third metal layer 26a and the fourth metal layer 28a are formed on the substrate 10 on which the second oxide semiconductor pattern 24c is formed, the fourth metal layer 28a is formed. ) A fourth photoresist pattern 100c is formed.

In this case, the metal layer for the source and drain electrodes is formed in a structure in which the third metal layer 26a and the fourth metal layer 28a are stacked, and the third metal layer 26a uses MoTi, and the fourth metal layer 28a is Cu. Use

The fourth photoresist pattern 100c is formed by forming a photoresist on the substrate 10 on which the fourth metal layer 28a is formed, and performing a photolithography process using the third mask on the photoresist. In this case, the third mask uses a mask having two different transmittances including a transmission region for transmitting light and a blocking region for blocking light. Therefore, the blocking region may be a region exposing the first pattern for the gate pad, a region D-Pad on which the data pad is formed, a region D-line on which the data line is formed, a region Cst on which the storage capacitor is formed, The thin film transistor is disposed in a region corresponding to the source and drain electrodes of the region TFT in which the thin film transistor is formed, and the transmission region is disposed in all regions except for the region in which the blocking region is disposed.

Subsequently, as shown in FIG. 5B, the source and drain electrode metal layers 26a and 28a are etched using the fourth photoresist pattern 100c formed on the substrate 10 to etch the source electrode 30a, A drain electrode 30b, a storage capacitor upper electrode 30c, a data line 30d, a data pad 30e, and a gate pad 20e / 30f are formed.

At this time, during the etching process of the source and drain electrode metal layers 26a and 28a, the pixel electrode pattern 20c in which the first metal layer 21a and the second metal layer 21b are stacked, and the second metal layer in the common electrode pattern 20d are formed. 21b is removed to form the common electrode 20cf and the pixel electrode 20df.

The second pattern 30f for the gate pad contacts the exposed first pattern 20e for the gate pad to form a gate pad.

Subsequently, the fourth photoresist pattern 100c is removed by performing a strip process on the fourth photoresist pattern 100c.

6A and 6B are cross-sectional views illustrating a contact hole formed without a mask process in a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to an exemplary embodiment of the present invention.

As shown in FIG. 6A, the source electrode 30a, the drain electrode 30b, the storage capacitor upper electrode 30c, the data line 30d, the data pad 30e, the gate pads 20e / 30f, and the common electrode 20cf, a protective film 32 is formed on the substrate 10 on which the pixel electrode 20df is formed.

6B, a dry etching process using plasma is performed on the passivation layer 32 on which the data pad 30e and the gate pads 20e / 30f are formed, thereby performing the gate pads 20e / 30f and the data pad. This process is completed by forming the first and second contact holes 34a and 34b exposing each of the 30e.

A dry etching process using a plasma for removing the gate pads 20e / 30f and the protective layer 22 on the data pads 30e will be described with reference to FIGS. 7A and 7B.

First, the dry etching process using plasma may include, for example, a beam type AP plasma method as shown in FIG. 7A and a bar type AP plasma method as shown in FIG. 7B. have.

The dry processes will be described with reference to the drawings.

As shown in FIG. 7A, the beam type atmospheric pressure plasma method selectively applies a plasma beam emitted from the plasma gun 170 to each of the data pads 30e and the gate pads 20e / 30f. Selective scanning. For this reason, the protective film 32 formed in the data pad 30e and the gate pads 20e / 30f shown in FIG. 6B is removed.

As shown in FIG. 7B, the bar type atmospheric pressure plasma method selectively scans the plasma beam emitted from the bar-shaped long plasma gun 172 to the data pad 30e and the gate pad 20e / 30f, respectively. The protective film 32 formed in the data pad 30e and the gate pads 20e / 30f shown in FIG. 6B is removed.

As a result, a contact hole exposing the gate pad or the data pad can be formed without a mask process.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

Accordingly, the scope of the present invention is not limited thereto, but various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims are also within the scope of the present invention.

1A and 1B are a plan view and a cross-sectional view for explaining a first mask process in a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to an embodiment of the present invention.

2A and 2B are plan views and cross-sectional views illustrating a second mask process in a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to an embodiment of the present invention.

3A to 3D are cross-sectional views for describing the second mask process in detail.

4A and 4B are plan and cross-sectional views illustrating a third mask process in a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to an embodiment of the present invention.

5A through 5B are cross-sectional views for describing the third mask process in detail.

6A and 6B are cross-sectional views illustrating a contact hole formed without a mask process in a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to an embodiment of the present invention.

7A and 7B illustrate a dry etching process using plasma to remove the protective layer on the gate pad and the data pad.

Claims (7)

Forming a gate electrode, a storage capacitor lower pattern, a common electrode pattern, a pixel electrode pattern, and a gate pad first pattern on the substrate using a first mask process; Forming a gate insulating pattern and a second oxide semiconductor pattern on the substrate on which the first mask process is completed using a second mask process; Forming a source electrode, a drain electrode, a storage capacitor upper electrode, a data line, a data pad, a gate pad, a common electrode, and a pixel electrode on the substrate on which the second mask process is completed using a third mask process; Forming a protective film on the substrate on which the third mask process is completed; Fabricating a thin film transistor array substrate comprising performing a dry etching process using plasma on the passivation layer on which the gate pad and the data pad are formed to form first and second contact holes respectively exposing the gate pad and the data pad. Way. The method of claim 1, wherein the gate electrode, the storage capacitor lower pattern, the common electrode pattern, the pixel electrode pattern, the first pattern for the gate pad, the source electrode, the drain electrode, the upper storage capacitor, the data line, the data pad, and the gate pad. The second pattern, the common electrode pattern, and the pixel electrode pattern are A method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer, characterized in that the first metal layer and the second metal layer is laminated structure. The method of claim 1, wherein the forming of the gate insulating pattern and the second oxide semiconductor pattern on the substrate using the second mask process is performed. Sequentially forming a gate insulating film and an oxide semiconductor layer on the substrate; Forming a first photoresist pattern on the oxide semiconductor layer; Etching the oxide semiconductor layer and the gate insulating layer using the first photoresist pattern as an etch mask to form a first oxide semiconductor pattern and the gate insulating pattern; Performing an ashing process on the first photoresist pattern to form a second photoresist pattern; And etching the first oxide semiconductor pattern by using the second photoresist pattern as an etch mask to form the second oxide semiconductor pattern. The method of claim 3, wherein the oxide semiconductor layer A method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer, characterized in that formed of any one of ZnO, CdO, GaO, InO, InO, SnO. The method of claim 3, wherein the second mask is A method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer, characterized by using three different transmittance masks. The method of claim 3, wherein the wet etching is performed during the etching process of the oxide semiconductor layer using the first photoresist pattern and the second photoresist pattern as an etch mask, and the first photoresist pattern is etched as a etch mask. A method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer, characterized in that for performing the dry etching during the etching process. The pixel electrode pattern of claim 2, wherein the common electrode pattern and the pixel electrode pattern stacked with the second metal layer and the first metal layer are formed. And the second metal layer is removed through the third mask process to form the common electrode and the pixel electrode.

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