KR20110045804A - Array substrate for Liquid crystal display device and Method of fabricating the same - Google Patents

Abstract

PURPOSE: An array panel for liquid crystal display device and manufacturing method thereof are provided to increase the quality of a display device by efficiently solving signal delay un-uniform problem about a location relation of a gate line and a gate drive IC. CONSTITUTION: A plurality of gate lines(114) is located in a display area on a first substrate. A plurality of common lines(116) is separated with a plurality of gate lines. A data drive IC(138) is located in a non-display area. A plurality of data lines(130) includes a second data line. A thin film transistor is connected to the data line and the gate line. A plurality of pixel electrodes is connected to the thin film transistor. A plurality of common electrodes is located in a pixel region. A first conductive pattern is electrically connected to the common line.

Description

Array substrate for liquid crystal display device and method for manufacturing the same {Array substrate for Liquid crystal display device and Method of fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a method for manufacturing the same, which can uniformize signal delay between link wirings.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: abbreviated as an active matrix LCD, abbreviated as a liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the best resolution and video performance. It is attracting attention.

The liquid crystal display device includes an upper substrate, a lower substrate, and a liquid crystal layer interposed between the upper and lower substrates. Pixel electrodes are formed in each of the plurality of pixel regions on the lower substrate, and a common electrode is formed on the front surface of the upper substrate, and the liquid crystal layer is driven by an electric field between the pixel electrode and the common electrode. The upper substrate may be referred to as a color filter substrate, and the lower substrate may be referred to as an array substrate.

1 is a plan view schematically illustrating a structure of a general array substrate for a liquid crystal display device.

As illustrated, an array substrate for a liquid crystal display device crosses each other on a substrate 11 on which a display area DR and a non-display area NDR around the display area DR are defined. The gate wiring 13 and the data wiring 15 defining P) are formed. The plurality of pixel areas P is positioned in the display area DR.

Although not illustrated, a thin film transistor connected to the gate line 13 and the data line 15 and a pixel electrode connected to the thin film transistor are formed in the pixel area P. Referring to FIG.

In the non-display area NDR, a gate driver IC (Integrated Circuit) 20 for driving the thin film transistor by applying a signal to the gate line 13 and the data electrode 15 to the pixel electrode. A data driver IC 30 for applying a signal is formed.

Further, a gate link wiring 14 for connecting the gate drive IC 20 and the gate wiring 13 and a data link wiring for connecting the data drive IC 30 and the data wiring 15 ( 16) is formed.

For example, the gate drive IC 20 may include first to third gate drive ICs 20a, 20b, and 20c, and a plurality of gate lines 13 may be included in the first to third gate drive ICs 20a. , 20b, 20c).

In addition, the data drive IC 30 may include first to fourth gate drive ICs 30a, 30b, 30c, and 30d, and a plurality of data wires 15 may include the first to fourth gate drive ICs 30a. , 30b, 30c, 30d).

In this case, the plurality of data wires 13 connected to the first data drive IC 30a may cause resistance variations due to the length of the data link wires 16 depending on their positions. That is, a resistance deviation occurs between the first data wire 13 and the second or third data wire 13, and this resistance deviation occurs as the size of the substrate 11 increases.

This resistance variation problem also occurs in the data link wiring 16 connected to the second to fourth data drive ICs 30b, 30c, and 30d, and also in the gate link wiring 14 connected to the gate drive IC 20. Doing.

This resistance variation causes a delay problem of the data signal, thereby causing a decrease in display quality.

In order to solve this problem, as shown in FIG. 2, a structure in which the gate link wiring and the data link wiring have a zigzag shape has been proposed. For example, the structure of the data link wiring will be described.

FIG. 2 is a diagram showing the form of data link wiring. As shown in the drawing, a data wiring 60 is formed on a substrate 51, and a data drive IC for applying a signal to the data wiring 60 is shown. 70 is formed. In addition, a data link wiring 62 for connecting the data drive IC 70 and the data wiring 60 is formed.

The first data line 60a positioned at a first distance from the data drive IC 70 among the data line 60 and the second data line 60b positioned at a second distance smaller than the first distance. The third data wire 60c is positioned at a third distance smaller than the second distance, and the data link wire 62 connected to each of the first to third data wires 60a, 60b, and 60c is connected to each other. When referred to as the first to third data link wires 62a, 62b, and 62c, the number of zigzag of each of the first to third data link wires 60a, 60b, and 60c is adjusted to control the data link wires 60a and 60b. , 60c) is made uniform in length.

In other words, the resistance of the data link line 62 is made uniform regardless of the distance of the data line 60 from the data drive IC 70 to solve the delay problem.

However, there are still limitations to this structure. In particular, a narrow bezel structure for reducing the size of the liquid crystal display device is required to minimize the area of the non-display area for the data link line 62. In this case, there is a limit in controlling the zigzag number of the data link wiring 62 to make the resistance uniform.

The present invention is to provide an array substrate for a liquid crystal display device with improved display quality by effectively solving the problem of signal delay unevenness caused by the positional relationship between the data drive IC and the data wiring, and the positional relationship between the gate drive IC and the gate wiring.

In addition, it is intended to solve the signal delay nonuniformity problem without increasing the non-display area area.

In order to solve the above problems, the present invention provides a display area and a plurality of gate wires positioned in the display area on a first substrate on which a non-display area around the display area is defined; A plurality of common lines spaced apart in parallel with the plurality of gate lines; A data drive IC positioned in the non-display area; A plurality of data lines including first and second data wires defining a plurality of pixel areas in the display area crossing the plurality of gate wires and varying a distance from the data drive IC; A thin film transistor positioned in the pixel region and connected to the gate line and the data line; A plurality of pixel electrodes positioned in the pixel region and connected to the thin film transistor; A plurality of common electrodes positioned in the pixel area and connected to the common wirings and alternately arranged with the plurality of pixel electrodes; A plurality of data link wires including first and second data link wires extending from the first and second data wires to the non-display area, respectively, and connected to the data drive ICs; Liquid crystals comprising a first conductive pattern overlapping the first and second data link wires to form first and second capacitors, respectively, and electrically connected to common wires positioned at the outermost ones of the plurality of common wires. An array substrate for a display device is provided.

In another aspect, the present invention provides a display device comprising: a plurality of gate wires positioned in the display area on a first substrate on which a display area and a non-display area around the display area are defined; Common wiring positioned in the non-display area; A data drive IC positioned in the non-display area; A plurality of data lines including first and second data wires defining a plurality of pixel areas in the display area crossing the plurality of gate wires and varying a distance from the data drive IC; A thin film transistor positioned in the pixel region and connected to the gate line and the data line; A pixel electrode positioned in the pixel region and connected to the thin film transistor; A plurality of data link wires comprising first and second data link wires extending from said first and second data wires, respectively, and connected to said data drive IC; The present invention provides an array substrate for a liquid crystal display device including a first conductive pattern overlapping the first and second data link wires to form first and second capacitors and electrically connected to the common wires.

The second data line is located closer to the first data line than the data drive IC, and the capacity of the second capacitor is larger than that of the first capacitor.

The first conductive pattern has an inverted triangle or triangular shape.

The first and second data link wirings have a zigzag shape, and the second data link wiring has a zigzag shape number greater than that of the first data link wiring.

And a connection part extending from the first conductive pattern, wherein the connection part contacts the common wire.

A gate drive IC positioned in the non-display area of the first substrate, wherein the gate wiring includes first and second gate wirings having a distance from the gate drive IC, and the first and second gates A plurality of gate link wirings, each of the first and second gate link wirings extending from the wirings, the plurality of gate link wirings connected to the gate drive IC; And a second conductive pattern overlapping the first and second gate link wires to form third and fourth capacitors, respectively.

The second gate wiring is located at a distance closer to the first gate wiring from the gate drive IC, and the capacity of the fourth capacitor is larger than that of the third capacitor.

In still another aspect, the present invention provides a display area including a plurality of pixel areas, a plurality of gate wirings in the display area, and a plurality of gates on a first substrate on which a non-display area around the display area is defined. Forming a plurality of common wires spaced in parallel with the wires, and a plurality of common electrodes extending from one of the plurality of common wires to the pixel areas; A plurality of data lines defining the plurality of pixel areas crossing the plurality of gate lines and including first and second data lines, and extending from the first and second data lines to the non-display area, respectively. Forming a plurality of data link wires including first and second data link wires; Forming a thin film transistor connected to the gate line and the data line in each of the pixel regions; Forming a protective layer covering the plurality of data lines and the plurality of data link lines and the thin film transistor; On the passivation layer, a plurality of pixel electrodes arranged alternately with the plurality of common electrodes in each pixel area and connected to the thin film transistor, and overlapping the first and second data link lines, respectively, Forming a conductive pattern electrically connected to the common wiring positioned at the outermost portion of the wiring; And forming a data drive IC connected to one end of each of the plurality of data link wires in the non-display area, wherein the first and second data wires vary from a distance from the data drive IC. A method of manufacturing an array substrate for a liquid crystal display device is provided.

In another aspect, the present invention provides a display area including a plurality of pixel areas, a plurality of gate wirings in the display area, and a non-display area on a first substrate on which a non-display area around the display area is defined. Forming a common wiring in the region; A plurality of data lines defining the plurality of pixel areas crossing the plurality of gate lines and including first and second data lines, and extending from the first and second data lines to the non-display area, respectively. Forming a plurality of data link wires including first and second data link wires; Forming a thin film transistor connected to the gate line and the data line in each of the pixel regions; Forming a protective layer covering the plurality of data lines and the plurality of data link lines and the thin film transistor; Forming a pixel electrode connected to the thin film transistor in each pixel area, and a conductive pattern on the protective layer, the conductive pattern overlapping the first and second data link wires and electrically connected to the common wire; And forming a data drive IC connected to one end of each of the plurality of data link wires in the non-display area, wherein the first and second data wires vary from a distance from the data drive IC. A method of manufacturing an array substrate for a liquid crystal display device is provided.

The present invention has an advantage of providing an array substrate for a liquid crystal display device having improved display quality by effectively solving the problem of signal delay unevenness caused by the positional relationship between the data drive IC and the data wiring, and the positional relationship between the gate drive IC and the gate wiring.

In addition, it has the advantage of solving the problem of signal delay unevenness without increasing the non-display area area. As a result, the size of the liquid crystal display device can be minimized.

Hereinafter, the present invention will be described in detail with reference to the drawings.

3A is a plan view of an array substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 3B is an enlarged plan view of one pixel area in FIG. 3A.

3A and 3B, in the array substrate 100 for a liquid crystal display device according to the first embodiment of the present invention, a display area DR and a non-display area NDR around the display area are defined. A first substrate 110.

A plurality of gate lines 114 extend in a first direction and a plurality of data lines 130 extend in a second direction on the first substrate 110. The plurality of gate lines 114 and the plurality of data lines 130 cross each other to define a plurality of pixel areas P in the display area DR.

In addition, a plurality of common wires 116 are formed in the first direction adjacent to the gate wire 114. That is, the common wiring 116 is spaced apart from the plurality of gate wirings 114 in parallel to be positioned between adjacent gate wirings 114. The common wire 116 intersects the plurality of data wires 130.

A plurality of data link wires 136 extending from each of the plurality of data wires 130 are formed in the non-display area NDR. Although not shown, one end of the data link wiring 136 is defined as a data pad, and a data pad electrode contacting the data pad is formed on the data pad.

In the non-display area NDR, a data drive IC 138 for applying a signal to the data line 130 is located. The data drive IC 138 is electrically connected to the data link wiring 136. That is, the data drive IC 138 is electrically connected to the data link line 136 by contacting a data pad electrode (not shown).

In the non-display area NDR, a first conductive pattern 152 overlapping the data link line 136 and having an inverted triangle shape is formed. In contrast, the first conductive pattern 152 may have a triangular shape.

 A connection part 154 extending from the first conductive pattern 152 in the second direction is formed, and the connection part 154 is the most of the plurality of common wires 116 through the common wiring contact hole 144. The first conductive pattern 152 and the common wiring 116 are electrically connected to each other by contacting the common wiring 116 located at an outer shell thereof.

A thin film transistor Tr connected to the gate line 114 and the data line 130 is formed in the pixel area P. That is, the thin film transistor Tr may be disposed on the gate electrode 112 connected to the gate line 114, a gate insulating layer (not shown) covering the gate electrode 112, and positioned on the gate insulating layer. A semiconductor layer (not shown) corresponding to the gate electrode 112, a source electrode 132 positioned on the semiconductor layer and connected to the data line 130, and a source electrode 132 positioned on the semiconductor layer. ) And a drain electrode 134 spaced apart from each other. The semiconductor layer includes an active layer made of pure amorphous silicon and an ohmic contact layer made of impurity amorphous silicon.

In addition, a plurality of pixel electrodes 150 contacting the drain electrode 134 and the drain contact hole 142 are formed in the pixel region P, and a plurality of common electrodes connected to the common wiring 116 are formed. 117 is formed. The plurality of pixel electrodes 150 and the plurality of common electrodes 117 are alternately arranged.

Although the pixel electrode 150 and the common electrode 117 are illustrated in a straight line in FIG. 3, the pixel electrode 150 and the common electrode 117 may have a bent shape to form a multi-domain. In addition, although the common electrode 117 is shown extending from the common wiring 116, the common electrode 117 is formed on the same layer as the pixel electrode 150 and connected to the common wiring 116 through a contact hole. Can be.

The data wires 130 and the data link wires 136 are first to fourth data wires 130a, 130b, 130c, and 130d and first to fourth wires based on a distance from the center of the data drive IC 138. Fourth data link wirings 136a, 136b, 136c, and 136d are divided. The first data wire 130a has a first distance from the center of the data drive IC 138, and the second data wire 130b is smaller than the center of the data drive IC 138 and the first distance. Has a second distance. The third data wire 130c has a third distance smaller than the center of the data drive IC 138 and the second distance, and the fourth data wire 130c has a center of the data drive IC 138 and the third distance. And has a fourth distance less than the third distance. The first to fourth data link wires 136a, 136b, 136c, and 136d are connected to the first to fourth data wires 130a, 130b, 130c, and 130d, respectively.

Here, the first to fourth data link wires 136a, 136b, 136c, and 136d have a zigzag shape ('ㄹ' shape or 'S' shape), and the numbers of the first to fourth data link wires 136a, 136b, 136c, and 136d are different so that the overall length of the wires may be different. do. Alternatively, the first to fourth data link wires 136a, 136b, 136c, and 136d may have a straight line shape. In addition, the resistance of the first to fourth data link wires 136a, 136b, 136c, and 136d may be varied by varying their widths. That is, the difference in resistance due to distance can be compensated by making the first data link line 136a the widest and the smallest the width of the fourth data link line 136d.

As described above, a first conductive pattern 152 overlapping the first to fourth data link wires 136a, 136b, 136c, and 136d is formed, and the connection part 154 is connected to the common wire 116. ), The first conductive pattern 152 is electrically connected to the common wiring 116. Therefore, a common voltage is applied to the first conductive pattern 152. The first conductive pattern 152 has an inverted triangle shape. Accordingly, the first conductive pattern 152 overlaps the first data link line 136a by a first area and overlaps the second data link line 136b by a second area larger than the first area. . In addition, the first conductive pattern 152 overlaps the third data link line 136c by a third area larger than the second area and is larger than the fourth data link line 136d and the third area. Overlap by the fourth area.

That is, the overlapping area of the first conductive pattern 152 and the data link line 136 is located at a distance between the data line 130 connected to the data link line 136 and the data drive IC 138. Inversely

According to the above configuration, the first data link wire 136a overlaps the first conductive pattern 152 with a protective layer (not shown), and the first capacitor Cp1 is configured. Similarly, a second capacitor Cp2 is formed by the second data link wiring 136b and the first conductive pattern 152, and the third data link wiring 136c and the first conductive pattern 152 are formed. The third capacitor Cp3 is formed by the fourth capacitor, and the fourth capacitor Cp4 is formed by the fourth data link wire 136d and the first conductive pattern 152.

In this case, the overlapping area of the first conductive pattern 152 and the first data link wiring 136a is the smallest, and the overlapping area of the first conductive pattern 152 and the fourth data link wiring 136d is the smallest. It becomes big. That is, the capacity of the first capacitor Cp1 is smaller than the capacity of the second capacitor Cp2, the capacity of the second capacitor Cp2 is smaller than the capacity of the third capacitor Cp3, and the capacity of the third capacitor Cp3. The capacity is smaller than that of the fourth capacitor Cp4.

The capacitors Cp1, Cp2, Cp3, and Cp4 serve to delay a signal, and thus can uniformize signal delay of the first to fourth data link wires 136a, 136b, 136c, and 136d. In particular, by forming the first conductive pattern 152 without increasing the area of the non-display area NDR, the narrow bezel structure has an advantage.

Although not shown, a gate link line may be formed to extend from the gate line 114 to the non-display area NDR, and a second conductive pattern may be formed to overlap the gate link line. The second conductive pattern can eliminate signal delay unevenness in the gate link wiring on the same principle as that of the first conductive pattern 152.

4 and 5, a cross-sectional structure of an array substrate for a liquid crystal display device according to a first embodiment of the present invention will be described.

4 is a cross-sectional view taken along the line IV-IV of FIG. 3, and FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 3.

3 to 5, the gate line 114 extending along the first direction, the gate electrode 112 extending from the gate line 114, and the first direction on the substrate 110. The common wiring 116 is positioned to be extended and spaced apart from the gate wiring 114. In addition, a plurality of common wires 117 extending from the common wire 116 are positioned in the pixel area P, and gate link wires extending from the gate wire 114 in the non-display area NDR (not shown). ) Is located. One end of the gate link wiring is defined as a gate pad.

The gate wiring 114, the gate electrode 112, the common wiring 116, the common electrode 117, and the gate link wiring are aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and copper. (Cu), and a first metal material such as a copper alloy.

The gate insulating layer 118 made of an inorganic insulating material such as silicon oxide or silicon nitride on the gate wiring 114, the gate electrode 112, the common wiring 116, the common electrode 117, and the gate link wiring. Is located.

The active layer 120a made of pure amorphous silicon and the ohmic contact layer 120b made of impurity amorphous silicon are positioned on the gate insulating layer 118. The active layer 120a and the ohmic contact layer 120b form a semiconductor layer 120.

The source electrode 132 and the drain electrode 134 are spaced apart from each other on the semiconductor layer 120. In addition, a data line 130 connected to the source electrode 132 is positioned on the gate insulating layer 118.

The gate electrode 112, the gate insulating layer 118, the semiconductor layer 120, the source electrode 132, and the drain electrode 134 form a thin film transistor Tr. That is, the thin film transistor Tr is connected to the gate line 114 and the data line 130.

The data link line 136 extending from the data line 130 to the non-display area NDR is positioned on the gate insulating layer 118. Although not shown, one end of the data link wiring 136 is defined as a data pad.

Here, the data wire 130 and the data link wire 136 may be connected to the first to fourth data wires 130a, 130b, 130c, and 130d according to a distance from the center of the data drive IC 138. It is divided into first to fourth data link wirings 136a, 136b, 136c, and 136d.

The first data wire 130a has a first distance from the center of the data drive IC 138, and the second data wire 130b is smaller than the center of the data drive IC 138 and the first distance. Has a second distance. The third data wire 130c has a third distance smaller than the center of the data drive IC 138 and the second distance, and the fourth data wire 130c has a center of the data drive IC 138 and the third distance. And has a fourth distance less than the third distance. The first to fourth data link wires 136a, 136b, 136c, and 136d are connected to the first to fourth data wires 130a, 130b, 130c, and 130d, respectively. The first to fourth data link wires 136a, 136b, 136c, and 136d have a zigzag shape, and the number of the first to fourth data link wires 136a, 136b, 136c, and 136d varies, respectively, to change the length of the entire wire.

The drain contact hole 142 exposing the drain electrode 134 and the plurality of common wires on the source electrode 132, the drain electrode 134, the data wire 130, and the data link wire 136. The protective layer 140 having the common contact hole 144 exposing the common wiring 116 positioned at the outermost portion of the 116 is positioned. The protective layer 140 is made of an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material such as benzocyclobutene (BCB) or photo acryl. In this case, since the common wiring 116 is positioned under the gate insulating layer 118, the common contact hole 144 is formed through the protective layer 140 and the gate insulating layer 118.

Although not shown, a contact hole is formed to expose the gate pad located at one end of the gate link wiring (not shown) and the data pad located at one end of the data link wiring 136.

On the passivation layer 140, a plurality of pixel electrodes arranged alternately with the plurality of common electrodes 117 in the pixel region P and contacting the drain electrode 134 through the drain contact hole 142. 150 is located. The common electrode 117 and the pixel electrode 150 form a transverse electric field.

In the non-display area NDR, a first conductive pattern 152 overlapping the first to fourth data link wires 136a, 136b, 136c, and 136d is positioned. The conductive pattern 152 has an inverted triangle shape so as to have an overlapping area with the first to fourth data link wires 136a, 136b, 136c, and 136d. The first conductive pattern 152 extends therefrom and is electrically connected to the common wire 116 by a connection part 154 contacting the common wire 116 through the common contact hole 144.

The pixel electrode 150 and the first conductive pattern 152 may be formed of any one of indium tin oxide (ITO), indium zinc oxide (IZO), and molybdenum-titanium alloy (MoTi).

As a result, the first data link line 136a, the first conductive pattern 152, and the protective layer 140 constitute a first capacitor Cp1, and the second data link line 136b; The first conductive pattern 152 and the protective layer 140 constitute a second capacitor Cp2. In addition, the third data link line 136c, the first conductive pattern 152, and the protective layer 140 form a third capacitor Cp3, and the fourth data link line 136d and the The first conductive pattern 152 and the protective layer 140 constitute a fourth capacitor Cp4.

Although not shown, the second conductive pattern is positioned in the same structure as the first conductive pattern 152 corresponding to the gate link wiring.

In this case, the overlapping area of the first conductive pattern 152 and the first data link wiring 136a is the smallest, and the overlapping area of the first conductive pattern 152 and the fourth data link wiring 136d is the smallest. It becomes big. That is, the capacity of the first capacitor Cp1 is smaller than the capacity of the second capacitor Cp2, the capacity of the second capacitor Cp2 is smaller than the capacity of the third capacitor Cp3, and the capacity of the third capacitor Cp3. The capacity is smaller than that of the fourth capacitor Cp4. Therefore, the signal delay variation in the first to fourth data link wirings 136a, 136b, 136c, and 136d caused by the distance from the data drive IC 138 is improved.

6A is a plan view of an array substrate for a liquid crystal display according to a second embodiment of the present invention, and FIG. 6B is an enlarged plan view of one pixel area in FIG. 6A.

6A and 6B, in the array substrate 200 for a liquid crystal display device according to the second embodiment of the present invention, a display area DR and a non-display area NDR around the display area are defined. A first substrate 210.

A plurality of gate lines 214 extend in the first direction and a plurality of data lines 230 extend in the second direction on the first substrate 210. The plurality of gate lines 214 and the plurality of data lines 230 cross each other to define a plurality of pixel areas P in the display area DR.

The common line 216 is formed along the first direction in the non-display area NDR. Although not shown, the common wiring 216 applies a common voltage to the plate-shaped common electrode formed on the second substrate facing the first substrate 210.

A plurality of data link lines 236 extending from each of the plurality of data lines 230 are formed in the non-display area NDR. Although not shown, one end of the data link wiring 236 is defined as a data pad, and a data pad electrode contacting the data pad is formed on the data pad.

In the non-display area NDR, a data drive IC 238 for applying a signal to the data line 230 is located. The data drive IC 238 is electrically connected to the data link wiring 236. That is, the data drive IC 238 is electrically connected to the data link wiring 236 by contacting the data pad electrode (not shown).

In the non-display area NDR, a first conductive pattern 252 overlapping the data link line 236 and having an inverted triangle shape is formed. In contrast, the first conductive pattern 252 may have a triangular shape.

 The connection part 254 extending from the first conductive pattern 252 in the second direction is formed, and the connection part 254 contacts the common wire 216 through the common wire contact hole 144. The first conductive pattern 252 and the common wiring 216 are electrically connected to each other.

A thin film transistor Tr connected to the gate line 214 and the data line 230 is formed in the pixel area P. That is, the thin film transistor Tr may be disposed on the gate electrode 212 connected to the gate line 214, a gate insulating layer (not shown) covering the gate electrode 212, and disposed on the gate insulating layer. A semiconductor layer (not shown) corresponding to the gate electrode 212, a source electrode 232 disposed on the semiconductor layer and connected to the data line 230, and a source electrode 232 positioned on the semiconductor layer. ) And a drain electrode 234 spaced apart from each other. The semiconductor layer includes an active layer made of pure amorphous silicon and an ohmic contact layer made of impurity amorphous silicon.

In addition, the pixel electrode 150 is formed in the pixel region P to contact the drain electrode 234 through the drain contact hole 242. The pixel electrode 250 is independently located for each pixel region P and has a plate shape. The pixel electrode 250 is made of a transparent conductive material such as ITO and IZO.

The pixel electrode 150 forms a vertical electric field with a common electrode (not shown) formed on the second substrate (not shown), and the common electrode is formed of, for example, conductive dots (Ag). dot is connected to the common wire 216 of the first substrate 210.

The data wires 230 and the data link wires 236 and the first to fourth data wires 230a, 230b, 230c, and 230d and the first to fourth wires, depending on the distance from the center of the data drive IC 238. The fourth data link wirings 236a, 236b, 236c, and 236d are divided. The first data wire 230a has a first distance from the center of the data drive IC 238, and the second data wire 230b is smaller than the center of the data drive IC 238 and the first distance. Has a second distance. The third data wire 230c has a third distance smaller than the center of the data drive IC 238 and the second distance, and the fourth data wire 230c has a center of the data drive IC 238 and the third distance. And has a fourth distance less than the third distance. The first to fourth data link wires 236a, 236b, 236c, and 236d are connected to the first to fourth data wires 230a, 230b, 230c, and 230d, respectively.

In this case, the first to fourth data link wires 236a, 236b, 236c, and 236d have a zigzag shape, and the number of the first to fourth data link wires 236a, 236b, 236d, and 236d varies, respectively, to change the length of the entire wire. In contrast, the first to fourth data link wires 236a, 236b, 236c, and 236d may have a straight line shape. In addition, the resistance of the first to fourth data link wires 236a, 236b, 236c, and 236d may be adjusted by varying their widths. In other words, the first data link line 236a has the largest width, and the fourth data link line 236d has the smallest width, thereby making it possible to compensate for the distance difference.

As described above, a first conductive pattern 252 is formed to overlap each of the first to fourth data link wires 236a, 236b, 236c, and 236d, and the connection part 254 is connected to the common wire 216. ), The first conductive pattern 252 is electrically connected to the common wiring 216. Therefore, a common voltage is applied to the first conductive pattern 252. The first conductive pattern 252 has an inverted triangle shape. The first conductive pattern 252 is made of the same material on the same layer as the pixel electrode 250.

Therefore, the first conductive pattern 252 overlaps the first data link line 236a by a first area and overlaps the second data link line 236b by a second area larger than the first area. . In addition, the first conductive pattern 252 overlaps the third data link line 236c by a third area larger than the second area and is larger than the fourth data link line 236d and the third area. Overlap by the fourth area.

In other words, an overlapping area of the first conductive pattern 252 and the data link line 236 is determined by a distance between the data line 230 and the data drive IC 238 connected to the data link line 236. Inversely

According to the above configuration, the first data link line 236a overlaps the first conductive pattern 252 and a protective layer (not shown), and the first capacitor Cp1 is configured. Similarly, a second capacitor Cp2 is formed by the second data link wiring 236b and the first conductive pattern 252, and the third data link wiring 236c and the first conductive pattern 252 are formed. The third capacitor Cp3 is formed by the fourth capacitor, and the fourth capacitor Cp4 is formed by the fourth data link wire 236d and the first conductive pattern 252.

In this case, the overlapping area of the first conductive pattern 252 and the first data link wiring 236a is the smallest, and the overlapping area of the first conductive pattern 252 and the fourth data link wiring 236d is the smallest. It becomes big. That is, the capacity of the first capacitor Cp1 is smaller than the capacity of the second capacitor Cp2, the capacity of the second capacitor Cp2 is smaller than the capacity of the third capacitor Cp3, and the capacity of the third capacitor Cp3. The capacity is smaller than that of the fourth capacitor Cp4.

The capacitors Cp1, Cp2, Cp3, and Cp4 serve to delay the signal, and thus can uniformize the signal delay in the first to fourth data link wires 236a, 236b, 236c, and 236d. In particular, by forming the first conductive pattern 252 without increasing the area of the non-display area NDR, the narrow bezel structure has an advantage.

Although not shown, a gate link line may be formed to extend from the gate line 214 to the non-display area NDR, and a second conductive pattern may be formed to overlap the gate link line. The second conductive pattern can eliminate signal delay unevenness in the gate link wiring on the same principle as that of the first conductive pattern 252.

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device according to a first embodiment of the present invention will be described.

7A to 7D are manufacturing process diagrams of the portion cut along the cutting line IV-IV of FIG. 3, and FIGS. 8A to 8D are manufacturing process diagrams of the portion cut along the cutting line V-V of FIG.

As shown in FIGS. 7A and 8A, a first metal layer (not shown) is formed on the substrate 110 and patterned by a mask process to extend the gate wiring 114 extending along the first direction. A gate electrode 112 extending from the gate wiring 114 and a common wiring 116 extending along the first direction and spaced apart from the gate wiring 114 are formed. In addition, a plurality of common wires 117 are formed in the pixel area P and extend from the common wire 116, and gate link wires extending from the gate wire 114 in the non-display area NDR. ) Is formed. One end of the gate link wiring is defined as a gate pad. The first metal layer is made of any one of aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu), and copper alloy.

Next, an inorganic insulating material such as silicon oxide or silicon nitride is deposited on the gate wiring 114, the gate electrode 112, the common wiring 116, the common electrode 117, and the gate link wiring. Thus, the gate insulating film 118 is formed.

Next, as shown in FIGS. 7B and 8B, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are successively deposited on the gate insulating layer 118 and patterned by a mask process. The active layer 120a and the ohmic contact layer 120b are formed to correspond to the gate electrode 112. The active layer 120a and the ohmic contact layer 120b form a semiconductor layer 120.

Next, any one of aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu), and copper alloy is deposited on the semiconductor layer 120 and the gate insulating layer 118 to form a second metal layer ( The source electrode 132 and the drain electrode 134 are spaced apart from each other on the semiconductor layer 120 by forming and patterning the mask by a mask process. The gate electrode 112, the gate insulating layer 118, the semiconductor layer 120, the source electrode 132, and the drain electrode 134 form a thin film transistor Tr.

In addition, the data line 130 connected to the source electrode 132 is formed on the gate insulating layer 118, and the data link line 136 extending from the data line 130 to the non-display area NDR. ) Is formed. Although not shown, one end of the data link wiring 136 is defined as a data pad. The data link wiring 136 may include a first data link wiring (136a of FIG. 3), a second data link wiring (136b of FIG. 3), and third data according to a distance from the data drive IC (138 of FIG. 3). Link wiring 136c and fourth data link wiring 136d.

Next, as illustrated in FIGS. 7C and 8C, silicon oxide or silicon nitride may be formed on the source electrode 132, the drain electrode 134, the data line 130, and the data link line 136. The protective layer 140 is formed by depositing an inorganic insulating material. The protective layer 140 may be made of an organic insulating material such as benzocyclobutene (BCB) or photo acryl. Thereafter, the protective layer 140 is patterned by a mask process to form the drain contact hole 142 exposing the drain electrode 134.

In addition, the common contact hole 144 exposing the common wiring 116 is formed by patterning the passivation layer 140 and the gate insulating layer 118 under the passivation layer 140.

Although not shown, the protective layer 140 is patterned to form a data contact hole for exposing the data pad, which is one end of the data link line 136, and the protective layer 140 and the gate insulating layer 118. The gate contact hole is formed to expose the gate pad that is one end of the gate link wiring (not shown).

Next, as shown in FIGS. 7D and 8D, a transparent conductive material such as ITO and ZIO is deposited on the protective layer 140 to form a transparent conductive material layer (not shown), and then patterned by a mask process. In the pixel region P, a plurality of pixel electrodes 150 are formed. The pixel electrode 150 is connected to the drain electrode 134 through the drain contact hole 142 and alternately arranged with the plurality of common electrodes 117 to form a horizontal electric field.

In the non-display area NDR, a first conductive pattern 152 overlapping the data link line 136 and the connection portion 154 extending from the first conductive pattern 152 are formed. The connection part 154 contacts the common wire 116 through the common contact hole 144, whereby the first conductive pattern 152 is electrically connected to the common wire 116 to provide a common voltage. Is authorized.

The pixel electrode 150 and the first conductive pattern 152 may be made of molybdenum-titanium alloy (MoTi).

The first conductive pattern 152 may have different capacitances from the first to fourth data link wires 136a, 136b, 136c, and 136d, thereby allowing the first to fourth capacitors having different sizes. Cp1, Cp2, CP3, CP4).

Although not shown, a second conductive pattern constituting capacitors having capacitances of different sizes is formed on the protective layer 140 in correspondence with the gate link wiring by the same principle as the first conductive pattern. Gate pad electrodes and data pad electrodes are formed in contact with the gate pad and the data pad.

Subsequently, by connecting the data drive IC 138 and the gate drive IC (not shown) to the data link line 136 and the gate link line, an array substrate for a liquid crystal display device of the present invention can be obtained.

The array substrate for a liquid crystal display device of the present invention is manufactured by the above process, and can uniformize the signal delay of the first to fourth data link wirings 136a, 136b, 136c, and 136d. In particular, by forming the first conductive pattern 152 without increasing the area of the non-display area NDR, the narrow bezel structure has an advantage.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and changes of the present invention without departing from the spirit and scope of the present invention described in the claims below I can understand that you can.

1 is a plan view schematically illustrating a structure of a general array substrate for a liquid crystal display device.

2 is a plan view schematically illustrating a structure of a general array substrate for a liquid crystal display device.

3A is a plan view of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

FIG. 3B is an enlarged plan view of one pixel area in FIG. 3A.

4 is a cross-sectional view taken along the line IV-IV of FIG. 3.

5 is a cross-sectional view taken along the line V-V of FIG. 3.

6A is a plan view of an array substrate for a liquid crystal display according to a second embodiment of the present invention.

FIG. 6B is an enlarged plan view of one pixel area in FIG. 6A.

7A to 7D are manufacturing process diagrams of a portion cut along the cut line IV-IV of FIG. 3.

8A to 8D are manufacturing process diagrams of a portion cut along the cutting line V-V of FIG. 3.

Claims (10)

A plurality of gate wires positioned in the display area on a first substrate having a display area and a non-display area around the display area; A plurality of common lines spaced apart in parallel with the plurality of gate lines; A data drive IC positioned in the non-display area; A plurality of data lines including first and second data wires defining a plurality of pixel areas in the display area crossing the plurality of gate wires and varying a distance from the data drive IC; A thin film transistor positioned in the pixel region and connected to the gate line and the data line; A plurality of pixel electrodes positioned in the pixel region and connected to the thin film transistor; A plurality of common electrodes positioned in the pixel area and connected to the common wires and alternately arranged with the plurality of pixel electrodes; A plurality of data link wires including first and second data link wires extending from the first and second data wires to the non-display area, respectively, and connected to the data drive ICs; A first conductive pattern overlapping the first and second data link wires to form first and second capacitors, and electrically connected to common wires positioned at the outermost ones of the plurality of common wires; Array substrate for a liquid crystal display device comprising a. A plurality of gate wires positioned in the display area on a first substrate having a display area and a non-display area around the display area; Common wiring positioned in the non-display area; A data drive IC positioned in the non-display area; A plurality of data lines including first and second data wires defining a plurality of pixel areas in the display area crossing the plurality of gate wires and varying a distance from the data drive IC; A thin film transistor positioned in the pixel region and connected to the gate line and the data line; A pixel electrode positioned in the pixel region and connected to the thin film transistor; A plurality of data link wires comprising first and second data link wires extending from said first and second data wires, respectively, and connected to said data drive IC; First conductive patterns overlapping the first and second data link wires to form first and second capacitors, respectively, and electrically connected to the common wires. Array substrate for a liquid crystal display device comprising a. The method according to claim 1 or 2, And wherein the second data line is located closer to the first data line than the first data line, and the capacitance of the second capacitor is larger than that of the first capacitor. The method according to claim 1 or 2, And the first conductive pattern has an inverted triangle or a triangular shape. The method according to claim 1 or 2, And the first and second data link wires have a zigzag shape, and wherein the number of zigzag shapes of the second data link wires is larger than that of the first data link wires. The method according to claim 1 or 2, And a connecting portion extending from the first conductive pattern, wherein the connecting portion is in contact with the common wiring. The method according to claim 1 or 2, A gate drive IC positioned in the non-display area of the first substrate, The gate wirings include first and second gate wirings different in distance from the gate drive IC, A plurality of gate link wirings including first and second gate link wirings extending from said first and second gate wirings, respectively, and connected to said gate drive IC; And a second conductive pattern overlapping the first and second gate link wirings to form third and fourth capacitors, respectively. The method according to claim 1 or 2, And the second gate wiring is located at a distance closer to the first gate wiring from the gate drive IC, and the capacitance of the fourth capacitor is larger than that of the third capacitor. On the display substrate including a plurality of pixel regions and a non-display region surrounding the display region, a plurality of gate wirings and a plurality of gate wirings spaced apart in parallel to the plurality of gate wirings on the display substrate. Forming a common wiring and a plurality of common electrodes extending from one of the plurality of common wirings to the pixel areas; A plurality of data lines defining the plurality of pixel areas crossing the plurality of gate lines and including first and second data lines, and extending from the first and second data lines to the non-display area, respectively. Forming a plurality of data link wires including first and second data link wires; Forming a thin film transistor connected to the gate line and the data line in each of the pixel regions; Forming a protective layer covering the plurality of data lines and the plurality of data link lines and the thin film transistor; On the passivation layer, a plurality of pixel electrodes arranged alternately with the plurality of common electrodes in each pixel area and connected to the thin film transistor, and overlapping the first and second data link lines, respectively, Forming a conductive pattern electrically connected to the common wiring positioned at the outermost portion of the wiring; Forming a data drive IC connected to one end of each of the plurality of data link wires in the non-display area, And the first and second data wires differ in distance from the data drive IC. Forming a plurality of gate wires in the display area and a common wire in the non-display area on a display area including a plurality of pixel areas and a non-display area around the display area; ; A plurality of data lines defining the plurality of pixel areas crossing the plurality of gate lines and including first and second data lines, and extending from the first and second data lines to the non-display area, respectively. Forming a plurality of data link wires including first and second data link wires; Forming a thin film transistor connected to the gate line and the data line in each of the pixel regions; Forming a protective layer covering the plurality of data lines and the plurality of data link lines and the thin film transistor; Forming a pixel electrode connected to the thin film transistor in each pixel area, and a conductive pattern on the protective layer, the conductive pattern overlapping the first and second data link wires and electrically connected to the common wire; Forming a data drive IC connected to one end of each of the plurality of data link wires in the non-display area, And the first and second data wires differ in distance from the data drive IC.

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