KR20110044532A - Flexible circuit board and method for fabricating the board and semiconductor package comprising the board and method for fabricating the package - Google Patents

Abstract

PURPOSE: A flexible printed circuit board, manufacturing method thereof and semiconductor package including the same, and manufacturing method thereof are provided to prevent deformity due to the damage of the plating layer by forming the forward plating layer on the test pad domain. CONSTITUTION: A flexible printed circuit board includes a base film(10), a conductive pattern(20), a plating alloy layer, and a protective layer. The base film includes an insulating material having the base film. The conductive pattern includes a wiring area(30) and a test pad area(40). The plating alloy layer is formed on the conductive pattern. The plating alloy layer of the flexible printed circuit board includes tin and copper. The plating alloy layer performs a buffer function between conductive patterns.

Description

Flexible circuit board, method for manufacturing the same, and semiconductor package including the same, and method for manufacturing the same

The present invention relates to a flexible circuit board.

Recently, a flat panel display (FPD) such as a liquid crystal display (LCD), a plasma display panel (PDP), and the like have been in the spotlight.

Such a flat panel display requires a screen display unit for displaying an image and a driving printed circuit board for transmitting an electrical signal to the screen display unit.

On the other hand, the driving printed circuit board and the screen display unit may be connected by a flexible circuit board. The flexible circuit board may include a conductive pattern and a driver IC mounted on the conductive pattern.

In general, tin plating is performed on the conductive pattern to prevent corrosion of the circuit wiring and to improve bonding between the bump and the circuit wiring when the semiconductor chip (driving integrated circuit) is mounted.

On the other hand, in the case of tin plating, a pure tin plating layer is formed on the surface side, and the pure tin plating layer has a weaker strength than the circuit wiring, so that a breakage may occur when a physical influence is given during the manufacturing process or the test process, and in particular, the conductive pattern The test pad region is used to test the substrate after the semiconductor chip is mounted, which may be more easily broken if a pure tin plating layer is formed on the test pad region. In addition, when particles are generated by such breakage, this may cause a failure of the entire product, thereby lowering product reliability.

In addition, if the plating layer is not formed to prevent this, the test pad region of the conductive pattern may be corroded or oxidized, which may also degrade product reliability.

The problem to be solved by the present invention is to provide a flexible circuit board with improved product reliability.

Another object of the present invention is to provide a method of manufacturing a flexible circuit board with improved product reliability.

Another object of the present invention is to provide a semiconductor package with improved product reliability.

Another object of the present invention is to provide a method of manufacturing a semiconductor package with improved product reliability.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In one aspect of the flexible circuit board of the present invention for achieving the above object, a conductive pattern is formed on one surface or both surfaces of a base film, and the conductive pattern is a flexible circuit board on which a plating layer is formed on the conductive pattern. A silver test pad region is included, and the plating layer includes a plating alloy layer in which the conductive pattern component and the plating component are mixed, and a plating layer formed only of the plating component, but the plating layer is not formed on the test pad region.

One aspect of the method for manufacturing a flexible circuit board of the present invention for achieving the above another object is to form a conductive pattern including a test pad region, an outer region, a lead region and an inner lead region on one or both surfaces of the base film; Forming a plating layer including a plating alloy layer and a pure plating layer on the conductive pattern, forming an etching resist in a portion of the conductive pattern, etching the pure plating layer in the remaining region where the etching resist is not formed, and removing the etching resist. It includes.

Another aspect of the method of manufacturing a flexible circuit board of the present invention for achieving the above another object is to form a conductive pattern including a test pad region, an outer region, a lead region and an inner lead region on one or both sides of the base film; Forming a plating alloy layer on the conductive pattern, forming a plating resist in a portion of the conductive pattern, forming a plating layer on the plating alloy layer in the remaining region where the plating resist is not formed, and removing the plating resist. do.

One aspect of a semiconductor package of the present invention for achieving the above another object includes the flexible circuit board, and a semiconductor chip mounted on the flexible circuit board.

One aspect of the manufacturing method of the semiconductor package of this invention for achieving the said another subject includes preparing the flexible circuit board which concerns on the said manufacturing method, and mounting a semiconductor chip in the inner lead area of a flexible circuit board.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

References to elements or layers "on" other elements or layers include all instances where another layer or other element is directly over or in the middle of another element. On the other hand, when a device is referred to as "directly on", it means that it does not intervene with another device or layer in between.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms "comprises" and / or "made of" means that a component, step, operation, and / or element may be embodied in one or more other components, steps, operations, and / And does not exclude the presence or addition thereof.

Although the first, second, etc. are used to describe various components, these components are of course not limited by these terms. These terms are only used to distinguish one component from another. Therefore, of course, the first component mentioned below may be a second component within the technical spirit of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

What is represented herein as "A or B" includes both cases of "A" or "B" or "A and B".

Hereinafter, a flexible circuit board according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a plan view of a flexible circuit board according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1. 1 and 2 illustrate a flexible circuit board for a chip on film (COF), but this is only one example and the present invention is not limited thereto.

1 and 2, a flexible circuit board according to an embodiment of the present invention may include a base film 10, a conductive pattern 20, a plating alloy layer 50, a pure plating layer 60, and a protective layer 70. It includes.

The base film 10 may be made of, for example, an insulating material having a thickness of 20 to 100 μm. The base film 10 may be made of, for example, a polymer resin such as polyimide, polyester, or polyethylene terephthalate (PET).

The conductive pattern 20 may be made of a highly conductive material, for example, a metal such as gold, silver, aluminum, or copper. In particular, the conductive pattern 20 of the flexible circuit board according to an embodiment of the present invention may be a metal layer made of copper (Cu) having a thickness of 5 to 15㎛.

2 illustrates the conductive pattern 20 formed on one surface of the base film 10, the conductive pattern 20 may also be formed on the other surface of the base film 10. That is, the conductive pattern 20 may be formed on both sides of the base film 10.

The conductive pattern 20 may include a wiring region 30 and a test pad region 40. In more detail, the conductive pattern 20 may include an inner lead region 32, an outer region 34, a wiring region 30 including a lead region 36, and a test pad region 40.

The wiring area 30 includes a semiconductor chip (100 in FIG. 9) to be mounted in the inner lead area 32 and a driving printed circuit board (not shown) and a screen display part (not shown) to be mounted in the outer area 34. It can serve to connect. Specifically, a signal input from a printed circuit board (not shown), for example, a driving / control signal is processed by the semiconductor chip 100 (see FIG. 9), and the processed signal is transferred to a screen display unit (not shown). The screen display unit (not shown) may display an image.

The test pad region 40 is positioned at both ends of the conductive pattern 20 to be used to test whether the flexible circuit board is good after manufacturing the flexible circuit board, or the semiconductor chip (100 in FIG. 9) in the inner lead region 32. After mounting, the semiconductor package may be used to test a semiconductor package for good quality.

The plating alloy layer 50 is formed on the conductive pattern 20, and may be a layer in which an alloy including a metal component and another metal component constituting the conductive pattern 20 is formed by a plating process. Specifically, the plating alloy layer 50 of the flexible circuit board according to an embodiment of the present invention is copper and tin formed while performing tin (Sn) plating on a copper (Cu) layer used as a material of the conductive pattern 20. The plating alloy layer 50 may be. In addition, the thickness t1 of the plating alloy layer 50 may be 0.05 to 0.4 μm.

Since the plating alloy layer 50 is relatively stronger than the plating layer 60, the plating alloy layer 50 may perform a buffer function between the conductive pattern 20 and the plating layer 60. That is, the plating alloy pattern may be a pattern that functionally performs a buffer function.

The pure plating layer 60 is formed on the plating alloy layer 50 and may be a layer formed only of a plating component. Specifically, the pure plating layer 60 of the flexible circuit board according to an embodiment of the present invention may be a tin plating layer, but the present invention is not limited thereto and may be other pure plating layers such as nickel and gold. Such a pure plating layer 60 (for example, a tin plating layer) prevents oxidation and corrosion of the conductive pattern 20, and bumps and conductive patterns of the semiconductor chip (100 in FIG. 9) to be mounted in the inner lead region 32. 20) to improve the bonding force. In this case, the thickness t2 of the plating layer 60 may be 0.05 to 0.3 μm.

In particular, the plating layer 60 of the flexible circuit board according to an embodiment of the present invention is a plating alloy formed on the test pad region 40 and the outer region 34 of the conductive pattern 20 as shown in FIG. It can be formed to expose layer 50. Therefore, only the plating alloy layer 50 is formed on the test pad region 40 and the outer region 34 of the conductive pattern 20 to prevent defects due to plating layer damage compared to when the plating layer 60 is further formed. Can be. In addition, even when no plating layer is formed on the test pad region 40 and the outer region 34 of the conductive pattern 20, oxidation and corrosion of the conductive pattern 20 can be prevented and reliability can be improved. Do.

The protective layer 70 may be formed on the lead region 36 of the wiring region 30 of the conductive pattern 20. In detail, the protective layer 70 may be formed on the plating layer 60 formed on the lead region 36 of the wiring region 30 of the conductive pattern 20. The protective layer 70 may serve to protect the conductive pattern 20 from an external impact or a corrosive material and to secure an insulating state of the conductive pattern 20. As the protective layer 70, a solder resist may be exemplified, but the present invention is not limited thereto.

Next, a flexible circuit board according to another exemplary embodiment of the present invention will be described with reference to FIG. 3.

3 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention.

Referring to FIG. 3, a flexible circuit board according to another embodiment of the present invention includes a base film 10, a conductive pattern 20, a plating alloy layer 50, a pure plating layer 60, and a protective layer 70. do.

The plating layer 60 of the flexible circuit board 60 according to another embodiment of the present invention exposes the plating alloy layer 50 formed on the test pad region 40 of the conductive pattern 20 as shown in FIG. 3. Can be formed. That is, unlike the flexible circuit board according to the exemplary embodiment of the present invention, the pure plating layer 60 is formed on the outer region 34 of the conductive pattern 20 of the flexible circuit board according to another exemplary embodiment of the present invention. .

As such, according to another embodiment of the present invention, only the plating alloy layer 50 is formed on the test pad region 40 of the conductive pattern 20. Accordingly, defects due to plating layer damage, which may occur during a product test process, may be prevented as compared with when the pure plating layer 60 is further formed on the test pad region 40 of the conductive pattern 20. In addition, even when no plating layer is formed on the test pad region 40 of the conductive pattern 20, oxidation and corrosion of the conductive pattern 20 can be prevented, thereby improving reliability.

Other descriptions of the plating layer 60 and the descriptions of other components are the same as those of the flexible circuit board according to the exemplary embodiment of the present invention, which will be omitted.

Next, a method of manufacturing a flexible circuit board according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4 to 7.

4 is a flowchart illustrating a method of manufacturing a flexible circuit board according to an embodiment of the present invention. 5 to 7 are intermediate steps for explaining a method of manufacturing a flexible circuit board according to an embodiment of the present invention.

First, referring to FIGS. 4 and 5, a conductive pattern is formed on one surface of the base film (S100), and a plating alloy layer and a pure plating layer are formed on the conductive pattern (S110).

Although FIG. 5 illustrates that the conductive pattern 20 is formed on one surface of the base film 10, the conductive pattern 20 may be formed on the other surface of the base film 10. That is, the present invention may include forming the conductive pattern 20 on both sides of the base film 10.

The plating alloy layer 50 and the plating layer 60 may be formed by plating a pure metal on the conductive pattern 20. Specifically, for example, the plating alloy layer 50 and the pure plating layer 60 are composed of a plating alloy layer 50 composed of copper and tin and tin formed by performing electroless plating tin on the conductive pattern 20 composed of copper. The plating layer 60 may be. More specifically, for example, the plating alloy layer 50 and the pure plating layer 60 are formed by depositing a copper conductive pattern 20 in a tin plating solution to perform electroless plating and spreading the alloy ratio in the plating thickness direction through heat treatment. It may be a plating alloy layer 50 composed of copper and tin and a plating layer 60 composed of tin.

4, 6, and 7, a resist is formed on the plating layer, and the plating layer is etched using the resist (S120).

The resist 80 may be used for etching the formed plating layer 60. Specifically, the resist 80 is used to form the plating layer pattern by etching the formed plating layer 60. For example, an ink that selectively synthesizes synthetic resins such as butyl, epoxy, urethane, vinyl, ester, and phenol ( ink or paste. Such a resist 80 may be formed by a method of curing after screen printing.

Etching the pure plating layer 60 to form a pure plating layer pattern, for example, by forming a pure plating layer pattern by soft etching the acid plating solution containing hydrochloric acid or sulfuric acid. It may be. In this case, according to the manufacturing method of the flexible circuit board according to an embodiment of the present invention, as shown in FIG. 7, on the test pad region 40 and the outer region 34 of the conductive pattern 20. It may be to soft-etch the plating layer 60 so that the plating alloy layer 50 is formed.

After the etching process is performed, the resist 80 is removed (for example, the resist is removed with hot water at a temperature of about 40 ° C. to 70 ° C.) and the protective layer 70 is formed. A circuit board can be manufactured.

In this embodiment, the resist 80 is used as an etching resist, but the resist 80 may be a plating resist. That is, when the resist 80 is a plating resist, the plating alloy layer 50 is formed on the conductive pattern 20, and the resist is formed on the outer region 34 and the test pad region 40 of the conductive pattern 20. After the 80 is formed, the resist 80 is formed on the inner lead region 32 and the lead region 36 of the conductive pattern 20 in which the resist 80 is not formed. It may be to remove.

Next, a method of manufacturing a flexible circuit board according to another exemplary embodiment of the present invention will be described with reference to FIGS. 4 and 8.

8 is an intermediate step diagram for describing a method of manufacturing a flexible circuit board according to another exemplary embodiment of the present invention.

In the manufacturing method of the flexible circuit board according to another embodiment of the present invention to form a conductive pattern on one surface of the base film (S100), to form a plating alloy layer and a pure plating layer on the conductive pattern (S110) The same method as the manufacturing method of the flexible circuit board according to the embodiment.

Next, referring to FIG. 8, in the method of manufacturing a flexible circuit board according to another embodiment of the present invention, a protective layer is first formed on a plating layer, and a resist is formed on an inner lead region of a conductive pattern. Then, the pure plating layer is etched using the formed protective layer and the resist (S120).

That is, in the case of the manufacturing method according to an embodiment of the present invention, the resist 80 is first formed on the plating layer 60, and the protection layer 70 is formed after etching the plating layer 60 using the same. In the manufacturing method according to another embodiment of the present invention, the protective layer 70 is first formed and then the resist 80 is formed, and thereafter, the pure plating layer 60 is etched using the two.

Description of the other parts is the same as the method of manufacturing a flexible circuit board according to an embodiment of the present invention and the duplicated description is omitted.

Meanwhile, as another embodiment of the present invention, after forming a conductive pattern, a protective layer is first formed on the conductive pattern and then plated to form a plating alloy layer and a pure plating layer on the conductive patterns of the inner lead, the outer lead, and the test pad. After forming a pure plating layer pattern may be formed. That is, in another embodiment of the present invention, the plating layer formed under the protective layer may be omitted.

Although the method for manufacturing the flexible circuit board according to the exemplary embodiment of the present invention illustrated in FIG. 2 has been described above, the method of manufacturing the flexible circuit board according to another exemplary embodiment of the present invention illustrated in FIG. 3 is also described above. The method will be fully inferred by those skilled in the art, and a detailed description thereof will be omitted.

Next, a semiconductor package according to an embodiment of the present invention will be described with reference to FIG. 9.

9 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 9, a semiconductor package includes a flexible circuit board and a semiconductor chip 100 according to an embodiment of the present invention.

The semiconductor chip 100 may be mounted on the inner lead region 32 of the conductive pattern 20 on which the plating layer 60 is formed. In FIG. 9, the semiconductor chip 100 is mounted in a flip chip method, but the scope of the present invention is not limited thereto.

The test pad region 40 of the conductive pattern 20 illustrated in FIG. 9 may be cut and removed when the semiconductor chip 100 is mounted and a product test including the semiconductor chip 100 is completed. As described above, a driving printed circuit board (not shown) and a screen display unit (not shown) may be mounted on the outer region 34 of the conductive pattern 20.

As such, when the plating layer 60 is not formed on the test pad region 40 of the conductive pattern 20, defects due to plating layer damage that may occur during a product test process including the semiconductor chip 100 may be prevented.

FIG. 9 illustrates that a semiconductor chip 100 is mounted on a flexible circuit board according to an embodiment of the present invention, but the semiconductor chip 100 may be formed according to another embodiment of the present invention as shown in FIG. 3. It may be mounted on a flexible circuit board. That is, another semiconductor package according to another embodiment of the present invention may include a flexible circuit board and a semiconductor chip 100 according to another embodiment of the present invention.

Next, a method of manufacturing a semiconductor package according to an embodiment of the present invention will be described with reference to FIGS. 7 and 9.

First, as shown in FIG. 7, a flexible circuit board according to embodiments of the present invention is prepared.

After removing the resist 80 formed on the flexible circuit board as shown in FIG. 9, the semiconductor chip 100 is mounted in the inner lead region 32 of the conductive pattern 20.

Although FIG. 7 illustrates a flexible circuit board according to an embodiment of the present invention, the same method of manufacturing a semiconductor package of the present invention may be inferred from all the above-described manufacturing method embodiments of the flexible circuit board. Naturally detailed description will be omitted for those skilled in the art.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 is a plan view of a flexible circuit board according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

3 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention.

4 is a flowchart illustrating a method of manufacturing a flexible circuit board according to an embodiment of the present invention.

5 to 7 are intermediate steps for explaining a method of manufacturing a flexible circuit board according to an embodiment of the present invention.

8 is an intermediate step diagram for describing a method of manufacturing a flexible circuit board according to another exemplary embodiment of the present invention.

9 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: base film 20: conductive pattern

30: wiring area 32: inner lead area

34: outer area 40: test pad area

50: plating alloy layer 60: pure plating layer

70: protective layer 80: resist

100: semiconductor chip 36: lead region

S100-S120: Manufacturing method of flexible circuit board

Claims (12)

In a flexible circuit board in which a conductive pattern is formed on one or both surfaces of the base film, and a plating layer is formed on the conductive pattern. The conductive pattern includes a test pad region, The plating layer includes a plating alloy layer in which the conductive pattern component and the plating component are mixed and a pure plating layer formed only of the plating component, The flexible circuit board on which the purity layer is not formed. The method of claim 1, The thickness of the plating alloy layer is 0.05㎛ ~ 0.4㎛, the thickness of the purity layer is 0.05㎛ 0.3㎛ flexible circuit board. 3. The method of claim 2, The conductive pattern includes copper, and the plating alloy layer includes a plating alloy layer composed of copper (Cu) and tin (Sn), and the purity plating layer comprises a pure plating layer composed of pure tin. The flexible circuit board of any one of claims 1 to 3; And And a semiconductor chip mounted on the flexible circuit board. A conductive pattern including a test pad region, an outer region, a lead region, and an inner lead region is formed on one or both surfaces of the base film, Forming a plating layer including a plating alloy layer and a pure plating layer on the conductive pattern; An etching resist is formed in a portion of the conductive pattern, Etching the purity layer of the remaining region where the etching resist is not formed, Removing the etching resist. The method of claim 5, Etching the pure plating layer comprises the etching by spraying the acid solution containing a hydrochloric acid or sulfuric acid. A conductive pattern including a test pad region, an outer region, a lead region, and an inner lead region is formed on one or both surfaces of the base film, Forming a plating alloy layer on the conductive pattern, A plating resist is formed on a portion of the conductive pattern, Forming a plating layer on the plating alloy layer of the remaining region in which the plating resist is not formed, Removing the plating resist. The method according to claim 5 or 7, The plating alloy layer is formed by spreading the alloy ratio in the plating thickness direction through heat treatment after the plating. The method according to claim 5 or 7, Forming the etching resist or the plating resist forms a solder resist in the lead region before forming the etching resist or the plating resist, And forming the etching resist or the plating resist on the solder resist. The method according to claim 5 or 7, The resist comprises at least one of butyl, epoxy, phenol, vinyl, ester, Forming the etching resist or plating resist comprises forming by a printing method. The method according to claim 5 or 7, Removing the etching resist or the plating resist comprises spraying and removing hot water at 40 ° C. to 100 ° C. to the resist. Preparing a flexible circuit board according to any one of claims 5 to 7, And mounting a semiconductor chip in the inner lead region of the flexible circuit board.

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