KR20110037242A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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KR20110037242A
KR20110037242A KR1020090094599A KR20090094599A KR20110037242A KR 20110037242 A KR20110037242 A KR 20110037242A KR 1020090094599 A KR1020090094599 A KR 1020090094599A KR 20090094599 A KR20090094599 A KR 20090094599A KR 20110037242 A KR20110037242 A KR 20110037242A
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South Korea
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contact hole
forming
insulating film
metal layer
semiconductor device
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KR1020090094599A
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Korean (ko)
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유미현
김재영
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주식회사 하이닉스반도체
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Priority to KR1020090094599A priority Critical patent/KR20110037242A/en
Publication of KR20110037242A publication Critical patent/KR20110037242A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

PURPOSE: A semiconductor device formation method is provided to improve the characteristic of the semiconductor device by fundamentally solving the problem that the bottom of the contact hole is not open. CONSTITUTION: A bottom metal layer(110) is formed on a semiconductor substrate. A sacrificial dielectric film(130) is formed on the upper part of the bottom metal layer. The first contact hole is formed on the sacrificial dielectric film. An insulation spacer(160) is formed on the sidewall of the first contact hole.

Description

반도체 소자의 형성 방법{Method for forming semiconductor device}Method for forming semiconductor device

본 발명은 반도체 소자의 형성 방법에 관한 것으로, 보다 자세하게는 딥 콘택홀 패턴의 형성 방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a deep contact hole pattern.

최근의 대부분의 전자 제품들(electronic appliances)은 반도체 장치(semiconductor devices)를 구비한다. 상기 반도체 장치는 트랜지스터, 저항 및 커패시터 등의 전자 부품(electronic element)들을 구비하며, 이들 전자 부품들은 상기 전자 제품들의 부분적 기능을 수행할 수 있도록 설계된 후, 반도체 기판 상에 집적된다. 예를 들면, 컴퓨터 또는 디지털 카메라 등의 전자 제품들은 정보 저장을 위한 메모리 칩(memory chip), 정보 제어를 위한 처리 칩(processing chip) 등의 반도체 장치들을 구비하고, 상기 메모리 칩 및 처리 칩은 반도체 기판 상에 집적된 상기 전자 부품들을 구비한다. Most modern electronic appliances are equipped with semiconductor devices. The semiconductor device includes electronic elements such as transistors, resistors, and capacitors, which are designed to perform partial functions of the electronic products and then integrated on a semiconductor substrate. For example, electronic products such as a computer or a digital camera include semiconductor devices such as a memory chip for storing information and a processing chip for controlling information, and the memory chip and the processing chip are semiconductors. And the electronic components integrated on a substrate.

한편, 상기 반도체 장치들은 소비자가 요구하는 우수한 성능 및 저렴한 가격을 충족시키기 위해, 점점 더 고집적화될 필요가 있다. 반도체 메모리 소자의 집적도가 높아지면서 디자인 룰(design rule)이 감소하게 되어 반도체 소자의 패턴도 미세화되고 있다. 반도체 소자의 극미세화 및 고집적화가 진행됨에 따라 메모리 용 량의 증가에 비례하여 전체적인 칩(chip) 면적은 증가되고 있지만 실제로 반도체 소자의 패턴이 형성되는 셀(cell) 영역의 면적은 감소되고 있다. 따라서, 원하는 메모리 용량을 확보하기 위해서는 한정된 셀 영역 내에 보다 많은 패턴이 형성되어야만 하므로, 패턴의 선폭(critical dimension)이 감소된 미세 패턴을 형성하여야 한다.On the other hand, the semiconductor devices need to be increasingly integrated in order to meet the excellent performance and low price required by the consumer. As the degree of integration of semiconductor memory devices increases, design rules decrease, and the pattern of semiconductor devices becomes smaller. As the semiconductor devices become extremely fine and highly integrated, the overall chip area increases in proportion to the increase in memory capacity, but the area of the cell area where the pattern of the semiconductor device is formed is decreasing. Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell region, so that a fine pattern with a reduced critical dimension of the pattern must be formed.

미세 패턴을 형성하는 방법에는 노광마스크(photo mask)로서 위상반전마스크(phase shift mask)를 사용하는 방법이나, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; CEL) 방법이나, 두층의 감광막 사이에 에스.오.지(spin on glass; SOG)등의 중간층을 개재시킨 삼층레지스트(Tri layer resister; 이하 TLR이라 칭함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다. A method of forming a fine pattern includes a method of using a phase shift mask as an exposure mask or a method of forming a separate thin film on the wafer to improve image contrast. a contrast enhancement layer (CEL) method, a tri layer resister (hereinafter referred to as a TLR) method having an intermediate layer such as spin on glass (SOG) between two layers of photoresist, or an upper side of the photoresist. Silicate methods for selectively injecting silicon have been developed to lower the resolution limit.

이외에도 피치가 작은 패턴을 구현하기 위하여 장비기술이나 감광제 기술면에서 이를 해결하기 위한 대책을 강구중에 있으며, 공정 측면에서는 가장 가능성이 큰 것으로 이중 노광, 즉 한 패턴을 두 번의 노광으로 형성하는 방안 등이 연구되고 있다.In addition, in order to implement a pattern with a small pitch, measures are being taken to solve this problem in terms of equipment technology and photoresist technology. In terms of process, the most likely method is double exposure, that is, forming one pattern by two exposures. Is being studied.

한편, 35nm의 테크 이하에서의 패턴 특히, 콘택홀은 종횡비의 증가로 인해 노광단계에서의 감광막 패턴 형성의 마진 부족 및 DICD(Develope inspection critical dimension) 감소로 인한 패턴 불량 및 균일도(uniformity) 불량으로 인해 감광막 패턴을 식각마스크로 식각하여 콘택홀을 형성하는 과정에서 콘택홀의 하부 가 오픈되지 않아 반도체 소자의 열화를 유발하는 문제가 있다.On the other hand, the pattern below 35 nm tech, especially the contact hole, is due to poor pattern and uniformity due to lack of margin of photoresist pattern formation and reduced development inspection critical dimension (DICD) due to the increase in aspect ratio. In the process of forming the contact hole by etching the photoresist pattern with the etching mask, the lower portion of the contact hole is not opened, causing deterioration of the semiconductor device.

본 발명은 반도체 소자의 고집적화로 인해 종횡비가 큰 콘택홀을 형성하는 과정에서 콘택홀을 정의하는 감광막 패턴이 정확하게 형성되지 않거나, 콘택홀의 하부가 오픈되지 않아 반도체 소자의 특성을 저하시키는 문제를 해결하고자 한다.The present invention is to solve the problem that the photoresist pattern defining the contact hole is not formed accurately, or the lower portion of the contact hole is not opened in the process of forming a contact hole having a high aspect ratio due to the high integration of the semiconductor device, thereby reducing the characteristics of the semiconductor device. do.

본 발명의 반도체 소자의 형성 방법은 반도체 기판 하부 금속층을 형성하는 단계와 상기 하부 금속층 상부에 희생 절연막을 형성하는 단계와 상기 희생 절연막에 제 1 콘택홀을 형성하는 단계와 상기 제 1 콘택홀의 측벽에 절연막 스페이서를 형성하는 단계 및 상기 절연막 스페이서를 식각마스크로 상기 하부 금속층을 노출시키는 제 2 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다.The method of forming a semiconductor device of the present invention includes forming a lower metal layer of a semiconductor substrate, forming a sacrificial insulating film on the lower metal layer, forming a first contact hole in the sacrificial insulating film, and forming a first contact hole in the sidewall of the first contact hole. Forming an insulating film spacer and forming a second contact hole exposing the lower metal layer with an etch mask using the insulating film spacer.

이때, 상기 하부 금속층을 형성하는 단계 이후 상기 하부 금속층 상에 하부 절연막을 형성하는 단계를 더 포함하는 것을 특징으로 한다.In this case, the method may further include forming a lower insulating film on the lower metal layer after forming the lower metal layer.

여기서, 상기 하부 절연막은 질화막인 것을 특징으로 한다.Here, the lower insulating film is characterized in that the nitride film.

그리고, 상기 제 1 콘택홀을 형성하는 단계는 상기 희생 절연막 상에 상기 제 2 콘택홀의 폭 보다 큰 폭으로 이격된 감광막 패턴을 형성하는 단계 및 상기 감광막 패턴을 식각마스크로 상기 희생절연막 두께의 1/2 이상을 식각하는 단계를 포함하는 것을 특징으로 한다.The forming of the first contact hole may include forming a photoresist pattern spaced apart from the width of the second contact hole by a width larger than the width of the second contact hole, and using the photoresist pattern as an etch mask. It characterized in that it comprises a step of etching two or more.

그리고, 상기 절연막 스페이서를 형성하는 단계는 상기 제 1 콘택홀을 포함하는 전체 상부에 절연막 스페이서 물질을 형성하는 단계 및 상기 절연막 스페이서 물질에 스페이서 식각을 수행하는 단계를 포함하는 것을 특징으로 한다.The forming of the insulating film spacer may include forming an insulating film spacer material over the entire surface including the first contact hole and performing spacer etching on the insulating film spacer material.

이때, 상기 절연막 스페이서 물질은 ULTO(ultra low temperature oxide)인 것을 특징으로 한다.In this case, the insulating film spacer material is characterized in that the ultra low temperature oxide (ULTO).

그리고, 상기 제 2 콘택홀은 15000Å 내지 17000Å의 두께를 갖는 것을 특징으로 한다.And, the second contact hole is characterized in that having a thickness of 15000Å to 17000Å.

본 발명은 반도체 소자의 고집적화로 콘택홀을 정의하는 감광막 패턴이 정확하게 형성되지 않는 문제를 해결하여 종횡비가 큰 콘택홀의 하부가 오픈되지 않는 현상을 근본적으로 방지하여 반도체 소자의 특성을 향상시키는 효과를 제공한다.The present invention solves the problem that the photoresist pattern defining the contact hole is not accurately formed due to the high integration of the semiconductor device, thereby fundamentally preventing the bottom of the contact hole having a large aspect ratio from being opened, thereby providing an effect of improving the characteristics of the semiconductor device. do.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 형성 방법을 나타낸 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

도 1a에 도시된 바와 같이, 반도체 기판(100) 상에 하부 금속층(110)을 형성한다. 이후, 하부 금속층(110) 상부에 하부 절연막(120)을 형성한다. 이어서, 하부 절연막(120) 상부에 희생 절연막(130)을 형성한다. 여기서, 하부 절연막(120)은 질화막인 것이 바람직하고, 희생 절연막(130)은 230Å 이상인 것이 바람직하다. 즉, 본 발명에 따른 반도체 소자의 형성 방법은 희생 절연막(130)의 높이가 230Å 이상인 경우 적용되는 것이 바람직하다. As shown in FIG. 1A, the lower metal layer 110 is formed on the semiconductor substrate 100. Thereafter, a lower insulating layer 120 is formed on the lower metal layer 110. Subsequently, the sacrificial insulating layer 130 is formed on the lower insulating layer 120. Here, the lower insulating film 120 is preferably a nitride film, and the sacrificial insulating film 130 is preferably 230 kPa or more. That is, the method of forming a semiconductor device according to the present invention is preferably applied when the height of the sacrificial insulating film 130 is 230 Å or more.

그 다음, 희생 절연막(130) 상부에 감광막 패턴(140)을 형성한다. 이때, 감광막 패턴(140)이 이격되는 폭(a)은 실제 형성될 콘택홀 패턴의 폭보다 큰 것이 바람직하다. 여기서 감광막 패턴(140)이 실제 형성될 콘택홀 패턴의 폭보다 큰 폭으로 이격시키는 이유는 후속 공정에서 감광막 패턴(140)을 식각마스크로 형성되는 콘택홀의 측벽에 형성될 절연막 스페이서의 영역을 확보하기 위함이다. Next, the photoresist pattern 140 is formed on the sacrificial insulating layer 130. In this case, the width a of the photoresist layer pattern 140 is preferably greater than the width of the contact hole pattern to be formed. The reason why the photoresist pattern 140 is separated by a width larger than the width of the contact hole pattern to be actually formed is to secure the region of the insulating film spacer to be formed on the sidewall of the contact hole formed by the etching mask in a subsequent process. For sake.

도 1b에 도시된 바와 같이, 감광막 패턴(140)을 식각마스크로 희생절연막(130)을 식각하여 제 1 콘택홀(150)을 형성한다. 이때, 제 1 콘택홀(150)의 깊이는 희생절연막(130) 두께의 1/2 이상이 되도록 하는 것이 바람직하다. 이후, 감광막 패턴(140)을 제거하고, 클리닝 공정을 수행하여 표면에 남아있는 파티클을 제거하는 것이 바람직하다. 여기서, 클리닝 공정은 질소 클리닝 공정인 것이 바람직하다.As illustrated in FIG. 1B, the sacrificial insulating layer 130 is etched using the photoresist pattern 140 as an etch mask to form a first contact hole 150. In this case, the depth of the first contact hole 150 may be 1/2 or more of the thickness of the sacrificial insulating layer 130. Thereafter, it is preferable to remove the photoresist pattern 140 and perform a cleaning process to remove particles remaining on the surface. Here, it is preferable that a cleaning process is a nitrogen cleaning process.

이어서, 제 1 콘택홀(150)을 포함하는 희생절연막(130) 상부에 절연막(160)을 형성한다. 이때, 절연막(160)은 ULTO(ultra low temperature oxide)인 것이 바람직하다. 하지만, 반드시 이에 한정되는 것은 아니고, 스택 커버리지(stack coverage)가 좋은 특성을 갖는 물질이라면 변경 가능하다. 여기서, 절연막(160)은 스택 커버리지가 좋은 물질이기 때문에, 제 1 콘택홀(150)의 측벽에 균일하게 형성된다. 따라서, 후속공정에서 수행되는 스페이서 식각 공정에서 형성되는 절연막 스페이서의 폭 또한 균일하게 형성되어 콘택홀 상부 폭의 균일도가 향상된다. Next, an insulating layer 160 is formed on the sacrificial insulating layer 130 including the first contact hole 150. In this case, the insulating layer 160 is preferably ULTO (ultra low temperature oxide). However, the present invention is not limited thereto, and the stack coverage may be changed as long as the material has good properties. Here, since the insulating layer 160 is a material having a good stack coverage, the insulating layer 160 is uniformly formed on the sidewall of the first contact hole 150. Therefore, the width of the insulating film spacer formed in the spacer etching process performed in the subsequent process is also uniformly formed, thereby improving the uniformity of the upper width of the contact hole.

그 다음, 절연막(160)에 스페이서 식각을 수행하여 제 1 콘택홀(150)의 측벽에 절연막 스페이서(160)를 형성한다. 여기서, 절연막 스페이서(160)에 의해 제 1 콘택홀(150)의 하부는 'b'의 폭을 갖도록 노출된다. 즉, 절연막 스페이서(160)에 의해 노출되는 제 1 콘택홀(150)의 하부는 초기에 'a'의 폭으로 형성된 제 1 콘택홀(150)의 폭 보다 좁아진다. 여기서 절연막 스페이서(160)에 의해 노출되는 제 1 콘택홀(150)의 하부 폭(b)은 실제 구현하고자 하는 콘택홀의 폭이 되도록 하는 것이 바람직하다.Next, spacer etching is performed on the insulating layer 160 to form the insulating layer spacer 160 on the sidewall of the first contact hole 150. Here, the lower portion of the first contact hole 150 is exposed by the insulating layer spacer 160 to have a width of 'b'. That is, the lower portion of the first contact hole 150 exposed by the insulating film spacer 160 is narrower than the width of the first contact hole 150 initially formed to have a width of 'a'. In this case, the lower width b of the first contact hole 150 exposed by the insulating layer spacer 160 may be such that the width of the contact hole to be actually implemented.

도 1c에 도시된 바와 같이, 절연막 스페이서(160)를 식각마스크로 하부 금속층(110)이 노출되도록 제 1 콘택홀(150)이 하부의 희생절연막(130)을 식각하여 제 2 콘택홀(170)을 형성한다. 이때, 제 2 콘택홀(170)의 깊이는 5000Å 내지 17000Å의 두께인 것이 바람직하다. 그리고, 제 2 콘택홀(170)의 폭은 'b'인 것이 바람직하다. 즉, 제 2 콘택홀(170)은 종래와 같이 희생절연막(130) 상부에 형성된 감광막 패턴을 식각마스크로 형성되는 것이 아니라, 희생절연막(130) 상부의 제 1 콘택홀의 측벽에 형성된 절연막 스페이서(160)를 식각마스크로 형성됨으로써 종횡비가 높은 희생절연막을 식각하여 콘택홀을 정의하는 경우에도 용이하게 콘택홀의 하부가 오픈되도록 할 수 있다. As illustrated in FIG. 1C, the first contact hole 150 etches the lower sacrificial insulating layer 130 so that the lower metal layer 110 is exposed using the insulating layer spacer 160 as an etch mask, thereby forming the second contact hole 170. To form. At this time, the depth of the second contact hole 170 is preferably a thickness of 5000 kPa to 17000 kPa. In addition, the width of the second contact hole 170 is preferably 'b'. That is, the second contact hole 170 is not formed of the photoresist pattern formed on the sacrificial insulating layer 130 as an etching mask as in the related art, but the insulating layer spacer 160 formed on the sidewall of the first contact hole above the sacrificial insulating layer 130. ) As an etch mask, the lower portion of the contact hole can be easily opened even when the contact hole is defined by etching the sacrificial insulating film having a high aspect ratio.

상술한 바와 같이, 본 발명에 개시된 종횡비가 큰 미세 콘택홀의 형성 방법은 최종 콘택홀의 폭보다 큰 폭으로 이격된 감광막 패턴을 식각마스크로 하여 콘택홀을 형성하고, 그 측벽에 형성된 절연막 스페이서를 식각마스크로 하여 형성하여 종횡비가 큰 미세 콘택홀을 형성함으로써, 종래와 같이 감광막 패턴을 식각마스크로 직접 사용하여 콘택홀 패턴을 형성하지 않기 때문에 미세 콘택홀을 구현하기 위한 감광막 패턴 형성의 어려움으로 인해 콘택홀의 상부 폭의 균일도가 저하되어 콘 택홀의 하부가 정확하게 오픈되지 않는 문제를 근본적으로 해결함으로써 반도체 소자의 특성을 향상시킬 수 있다.As described above, in the method for forming a fine contact hole having a large aspect ratio disclosed in the present invention, the contact hole is formed by using a photoresist pattern pattern spaced larger than the width of the final contact hole as an etch mask, and the insulating layer spacer formed on the sidewall is etch mask. Since the contact hole pattern is not formed by directly using the photoresist pattern as an etch mask as in the related art, since the contact hole pattern is not formed as in the related art, it is difficult to form the photoresist pattern for implementing the micro contact hole. It is possible to improve the characteristics of the semiconductor device by fundamentally solving the problem that the uniformity of the upper width is lowered and the lower part of the contact hole is not opened correctly.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 형성 방법을 나타낸 단면도.1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Claims (7)

반도체 기판 하부 금속층을 형성하는 단계;Forming a metal layer under the semiconductor substrate; 상기 하부 금속층 상부에 희생 절연막을 형성하는 단계;Forming a sacrificial insulating film on the lower metal layer; 상기 희생 절연막에 제 1 콘택홀을 형성하는 단계;Forming a first contact hole in the sacrificial insulating film; 상기 제 1 콘택홀의 측벽에 절연막 스페이서를 형성하는 단계; 및Forming an insulating film spacer on sidewalls of the first contact hole; And 상기 절연막 스페이서를 식각마스크로 상기 하부 금속층을 노출시키는 제 2 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 형성 방법.And forming a second contact hole exposing the lower metal layer by using the insulating film spacer as an etch mask. 청구항 1에 있어서,The method according to claim 1, 상기 하부 금속층을 형성하는 단계 이후After forming the lower metal layer 상기 하부 금속층 상에 하부 절연막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 형성 방법.And forming a lower insulating film on the lower metal layer. 청구항 2에 있어서,The method according to claim 2, 상기 하부 절연막은 질화막인 것을 특징으로 하는 반도체 소자의 형성 방법.And the lower insulating film is a nitride film. 청구항 1에 있어서,The method according to claim 1, 상기 제 1 콘택홀을 형성하는 단계는Forming the first contact hole 상기 희생 절연막 상에 상기 제 2 콘택홀의 폭 보다 큰 폭으로 이격된 감광 막 패턴을 형성하는 단계; 및Forming a photoresist pattern on the sacrificial insulating layer, the photoresist layer having a width greater than a width of the second contact hole; And 상기 감광막 패턴을 식각마스크로 상기 희생절연막 두께의 1/2 이상을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 형성 방법.Etching at least 1/2 of the thickness of the sacrificial insulating layer using the photoresist pattern as an etching mask. 청구항 1에 있어서,The method according to claim 1, 상기 절연막 스페이서를 형성하는 단계는Forming the insulating film spacer 상기 제 1 콘택홀을 포함하는 전체 상부에 절연막 스페이서 물질을 형성하는 단계; 및Forming an insulating film spacer material over the entirety of the first contact hole; And 상기 절연막 스페이서 물질에 스페이서 식각을 수행하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 형성 방법.And spacer etching the insulating film spacer material. 청구항 5에 있어서,The method according to claim 5, 상기 절연막 스페이서 물질은 ULTO(ultra low temperature oxide)인 것을 특징으로 하는 반도체 소자의 형성 방법.And the insulating film spacer material is ultra low temperature oxide (ULTO). 청구항 1에 있어서,The method according to claim 1, 상기 제 2 콘택홀은 The second contact hole 15000Å 내지 17000Å의 두께를 갖는 것을 특징으로 하는 반도체 소자의 형성 방법.It has a thickness of 15000 GPa-17000 GPa, The formation method of the semiconductor element characterized by the above-mentioned.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10700084B2 (en) 2016-07-11 2020-06-30 Samsung Electronics Co., Ltd. Vertical memory devices

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10700084B2 (en) 2016-07-11 2020-06-30 Samsung Electronics Co., Ltd. Vertical memory devices
US10943922B2 (en) 2016-07-11 2021-03-09 Samsung Electronics Co., Ltd. Vertical memory devices

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