KR20110035775A

KR20110035775A - Redundancy circuit of a semiconductor memory apparatus

Info

Publication number: KR20110035775A
Application number: KR1020090093608A
Authority: KR
Inventors: 구기봉
Original assignee: 주식회사 하이닉스반도체
Priority date: 2009-09-30
Filing date: 2009-09-30
Publication date: 2011-04-06

Abstract

The redundancy circuit of the semiconductor memory device according to an exemplary embodiment of the present invention has an address input control unit for outputting an address as a control address when a redundancy enable signal is enabled, an address setting for generating a setting address according to the control address, and whether a fuse is cut. And a redundancy signal generator configured to enable a redundancy signal when the set address and the address are the same when the redundancy enable signal is enabled.

Description

Redundancy Circuit of a Semiconductor Memory Apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to redundancy circuits in semiconductor memory devices.

The semiconductor memory device includes a memory cell and is configured to store data in the memory cell. In this case, the semiconductor memory device includes redundant memory cells to replace defective memory cells, and is designed to internally store data in the redundant memory cells when an address is input to store data in the defective memory cells.

The semiconductor memory device includes a redundancy circuit that designates a storage location of data to an extra memory cell instead of a defective memory cell when an address signal specifying a location of a defective memory cell is input.

As shown in FIG. 1, a general redundancy circuit includes a plurality of address setting units 10 and 20 (only the first and second address setting units are shown as a simple example), and a redundancy signal generating unit 30.

The first address setting unit 10 includes a plurality of fuses (shown in FIG. 2), the first setting address in response to whether the fuses are cut and the first and second addresses add <0: 1>. Create (add_set <0>).

The second address setting unit 20 includes a plurality of fuses, and the second set address add_set <1> in response to whether the fuse is cut and the first and second addresses add <0: 1>. )

When the redundancy enable signal REN is enabled, the redundancy signal generation unit 30 and the first and second set addresses add_set <0: 1> and the first and second addresses add <0: 1 If>) is the same, the redundancy signal SYEB is generated.

Since the first address setting unit 10 and the second address setting unit 20 have the same internal configuration, the second address setting unit 20 will be described by explaining the configuration of the first address setting unit 10. Replaces the description of the configuration.

As illustrated in FIG. 2, the first address setting unit 10 may include first to third transistors P1, N1 and N2, first and second fuses F1 and F2, and first to third electrodes. Inverters IV1 to IV3 are included.

In the first transistor P1, a reset signal RST is input to a gate and an external voltage VDD is applied to a source. A drain of the second transistor P1 is commonly connected to each of the first and second fuses F1 and F2. In the second transistor N1, the first address add <0> is input to a gate thereof, and the other end of the first fuse F1 is connected to a drain thereof. In the third transistor N2, the second address add <1> is input to a gate thereof, and the other end of the second fuse F2 is connected to a drain thereof. The common node to which the sources of the first and second transistors N1 and N2 are connected is connected to the ground terminal VSS. The node connected to the drain of the first transistor P1 is connected to an input terminal of the first inverter IV1. In the second inverter IV2, an output terminal of the first inverter IV1 is connected to an input terminal and an input terminal of the first inverter IV1 is connected to an output terminal. An output terminal of the first inverter IV1 is connected to an input terminal of the third inverter IV3, and the first setting address add_set <0> is output from the output terminal.

The general redundancy circuit configured as described above operates as follows.

Each of the first address setting unit 10 and the second address setting unit 20 sets the first and second setting addresses add_set <0: 1> according to whether a fuse is cut, and the first and second settings. The first and second set addresses add_set <0: 1> are generated in response to the address add <0: 1>.

When the redundancy enable signal REN is enabled, the redundancy signal generation unit 30 may respectively recognize the first and second set addresses add_set <0: 1> and the first and second addresses add <0: 1. >) Is compared to enable the redundancy signal SYEB if it is the same, and to disable the redundancy signal SYEB if it is different. In this case, the redundancy enable signal REN includes information that a redundancy circuit is to be used to replace a defective memory cell. Therefore, when the redundancy enable signal REN is disabled, it has information that the redundancy circuit is not used.

As a result, when the redundancy enable signal REN is disabled, the redundancy signal generator 30 is configured to perform the first and second set addresses add_set <0: 1> and the first and second addresses add <. 0: 1>).

Although the redundancy signal generator 30 does not operate, the first and second address setting units 10 and 20 may respond to the address add <0: 1>. Current is consumed by shifting the voltage level of the set address add_set <0: 1> to a high or low level. Referring to FIG. 1, when the redundancy operation is not performed, the fuses F1 and F2 of the first and second address setting units 10 and 20 are not cut. Accordingly, the second and third transistors N1 and N2 receiving the first and second addresses add <0: 1> to the gate repeat the turn-on / turn-off operation, thereby providing current to the ground terminal VSS. Will flow. As a result, although the redundancy operation is not performed, the first and second address setting units 10 and 20 cause current consumption by flowing a current to the ground terminal VSS.

Since a general redundancy circuit consumes current even when no redundancy operation is performed, the more redundancy circuits, the more the current consumption of the semiconductor memory device increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a redundancy circuit of a semiconductor memory device capable of preventing current consumption when a redundancy operation is not performed.

The redundancy circuit of the semiconductor memory device according to the present invention can prevent current consumption when the redundancy operation is not performed, which is effective in reducing the current of the semiconductor memory device.

As shown in FIG. 3, the redundancy circuit of the semiconductor memory device according to the embodiment of the present invention includes an address input control unit 100, a first address setting unit 10, a second address setting unit 20, and a redundancy signal. The generation unit 30 is included.

When the redundancy enable signal REN is enabled, the address input controller 100 sets the first and second addresses add <0: 1> as the first and second control addresses add_ctrl <0: 1>. Output

The first address setting unit 10 generates a first setting address add_set <0> according to the first and second control addresses add_ctrl <0: 1> and whether a fuse is cut.

The second address setting unit 20 generates a second setting address add_set <1> according to the first and second control addresses add_ctrl <0: 1> and whether a fuse is cut.

When the redundancy enable signal REN is enabled, the redundancy signal generator 30 may enable the first and second set addresses add_set <0: 1> and the first and second addresses add <0 :. 1), the redundancy signal SYEB is enabled.

When the redundancy enable signal REN is enabled, the address input controller 100 may convert the first and second addresses add <0: 1> to the first and second control addresses add_ctrl <0: 1. Output as>). Meanwhile, when the redundancy enable signal REN is disabled, the address input control unit 100 may disable the first and second control addresses add_ctrl regardless of the first and second addresses add <0: 1>. <0: 1>) to a certain level.

As shown in FIG. 4, the address input controller 100 includes first and second NAND gates ND11 and ND12, and first and second inverters IV11 and IV12.

The first NAND gate ND11 receives the first address add <0> and the redundancy enable signal REN. The first inverter IV11 receives the output signal of the first NAND gate ND11 and outputs it as the first control address add_ctrl <0>. The second NAND gate ND12 receives the second address add <1> and the redundancy enable signal REN. The second inverter IV12 receives the output signal of the second NAND gate ND12 and outputs it as the second control address add_ctrl <1>. When the redundancy enable signal REN is disabled at a low level, the address input controller 100 configured as described above may be configured to be independent of the first and second addresses add <0: 1>. Lock the control address add_ctrl <0: 1> to the low level.

Since the first and second address setting units 10 and 20 and the redundancy signal generating unit 30 are configured in the same manner as the prior art illustrated in FIG.

The redundancy circuit of the semiconductor memory device according to the embodiment of the present invention configured as described above operates as follows.

The redundancy enable signal REN is enabled to replace the bad memory cell.

When the redundancy enable signal REN is enabled, the address input control unit 100 sets the first and second addresses add <0: 1> as the first and second control addresses add_ctrl <0: 1>. Output

The first and second address setting units 10 and 20 may configure the first and second setting addresses add_set <0: 1> according to the first and second control addresses add_ctrl <0: 1> and whether the fuse is cut. )

When the redundancy enable signal REN is enabled, the redundancy signal generation unit 30 and the first and second set addresses add_set <0: 1> and the first and second addresses add <0: 1 > And compares the first and second set addresses add_set <0: 1> and the first and second addresses add <0: 1> to enable the redundancy signal SYEB. . On the other hand, the redundancy signal generating unit 30 is the redundancy signal SYEB if the first and second set addresses add_set <0: 1> and the first and second addresses add <0: 1> are different from each other. Disable).

If a redundancy operation is unnecessary because a bad memory cell is not found in the semiconductor memory device, the redundancy enable signal REN is disabled.

When the redundancy enable signal REN is disabled, the address input control unit 100 may disable the first and second control addresses add_ctrl <0 regardless of the first and second addresses add <0: 1>. : 1>) to a certain level.

For example, as illustrated in FIG. 4, the address input control unit 100 may enable the first and second control addresses add_ctrl <0: 1 when the redundancy enable signal REN is disabled at a low level. &Quot;) can be configured to lock to low level.

Since the semiconductor memory device does not perform a redundancy operation, the fuses provided in the first and second address setting units 10 and 20 are not cut. Accordingly, the first and second addresses generating the first and second set addresses add_set <0: 1> according to the first and second control addresses add_ctrl <0: 1> and whether the fuse is cut. The setting unit 10, 20 (see FIG. 2) fixes the first and second setting addresses add_set <0: 1> to a specific level. For example, in the first address setting unit 10 illustrated in FIG. 2, the first and second fuses F1 and F2 are not cut, and are input to the gates of the second and third transistors N1 and N2. Since the first and second control addresses add_ctrl <0: 1> are at the low level, when the reset signal RST is enabled at the low level, the first set address add_set <0> is fixed at the high level. In this case, since the second and third transistors N1 and N2 receive a low level signal to each gate, no current flows to the ground terminal VSS.

When the redundancy enable signal REN is disabled, the redundancy signal generator 30 may disable the first and second set addresses add_set <0: 1> and the first and second addresses add <0: 1. Does not perform an operation of comparing the ") and disables the redundancy signal SYEB.

As described above, in the semiconductor memory device according to the present invention, when the redundancy enable signal REN is disabled, the output of the address setting unit may be fixed to a specific level to prevent current consumption of the address setting unit.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents are included in the scope of the present invention. Should be interpreted.

1 is a block diagram schematically illustrating a redundancy circuit of a general semiconductor memory device;

2 is a configuration diagram of a first address setting unit of FIG. 1;

3 is a block diagram schematically illustrating a redundancy circuit of a semiconductor memory device according to an embodiment of the present invention;

4 is a configuration diagram of an address input control unit of FIG. 3.

10: first address setting unit 20: second address setting unit

30: redundancy signal generation unit 100: address input control unit

Claims

An address input control unit for outputting an address as a control address when the redundancy enable signal is enabled;

An address setting unit which generates a setting address according to the control address and whether a fuse is cut; And

And a redundancy signal generator configured to enable a redundancy signal when the set address and the address are the same when the redundancy enable signal is enabled.

The method of claim 1,

The address input controller

And when the redundancy enable signal is disabled, fixing the control address to a specific level irrespective of the address.

The method of claim 1,

The redundancy signal generator

And when the redundancy enable signal is disabled, disabling the redundancy signal irrespective of the address and the set address.