KR20110031653A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to improve a hot carrier property by performing a writing operation and an erasing operation with an FN tunneling method. CONSTITUTION: A selection gate is formed on a semiconductor substrate. A floating gate(154) is separated from the selection gate and is formed on the semiconductor substrate. An ONO layer(156) is formed on the floating gate. A control gate is formed on the ONO layer. A first ion implantation area(110) is formed on the semiconductor substrate on one side of the selection gate. A second ion implantation area is formed on the semiconductor substrate between the selection gate and the floating gate. The third ion implantation area is formed on the semiconductor substrate on one side of the floating gate.

Description

Semiconductor memory device

Embodiments relate to a semiconductor memory device.

Flash devices, which have advantages of fast random access speed of less than 100ns and program of byte or word, have various applications in memory for code storage, and have a large weight in non-volatile memory (NVM) field.

However, using the Fowler Nordheim (FN) tunneling mechanism, there is an OE (Over Erase) problem that causes a bit line failure due to erase single bits.

FIG. 1 is a diagram schematically illustrating a current flow when a general flash device is programmed or erased.

In order to write / delete / read the flash device, a voltage is applied as shown in Table 1 below. In FIG. 1, arrows indicated by dotted lines indicate current flow during write operations, and arrows indicated by solid lines This shows the current flow during the erase operation.

action Control gate voltage (Vg) Source voltage (Vs) Drain Voltage (Vd) Bulk voltage (Vb) Operation method writing First voltage (Vpp) 0 V Second voltage Vdd 0 V HCI delete 0 V First voltage 0 V 0 V FN tunneling read Second voltage (Vg) 0 V Second voltage 0 V

As shown in Table 1, the voltage applied to the semiconductor substrate (bulk) 10, the source 20, the drain 30, and the control gate 60 is controlled to control the floating gate 40 and the substrate 10. An FN tunneling phenomenon may be induced between channel regions (a delete operation) or a hot carrier injection (HCI) phenomenon may be induced from the source 20 to the drain 30 side (write operation). An oxide-nitride-oxide (ONO) layer 50 is formed between the control gate 60 and the floating gate 40.

When the flash device having such a structure is operated in an HCI method for a write operation, current consumption increases.

The embodiment provides a semiconductor memory device capable of writing / deleting / reading operations and combining various applied voltages in order to solve problems such as transient erasing and high current consumption of HCI.

In an embodiment, a semiconductor memory device may include a selection gate formed on a semiconductor substrate; A floating gate spaced apart from the selection gate and formed on the semiconductor substrate; An ONO layer formed on the floating gate; A control gate formed on the ONO layer; A first ion implantation region formed in the semiconductor substrate on one side of the selection gate; A second ion implantation region formed in the semiconductor substrate between the selection gate and the floating gate; And a third ion implantation region formed in the semiconductor substrate on one side of the floating gate, wherein the first ion implantation region and the third ion implantation region function as source and drain regions, respectively, or vice versa, according to a voltage application method. The second ion implantation region may function as a channel connection region between the first ion implantation region and the third ion implantation region.

According to the embodiment, the following effects are obtained.

First, since both write / erase operations can be implemented by FN tunneling, low power memory devices can be fabricated and hot carrier characteristics can be improved.

Second, the combination of various applied voltages is possible, and the operation of writing / deleting / reading the semiconductor memory device can be processed by various operation methods as necessary, thereby solving the problem of excessive erasing.

Third, when the semiconductor memory device is operated at low power and the problem of over-erasing is solved, the semiconductor memory device can be applied as a memory-embedded device.

Referring to the accompanying drawings, a semiconductor memory device according to an embodiment will be described in detail.

Hereinafter, in describing the embodiments, detailed descriptions of related well-known functions or configurations are deemed to unnecessarily obscure the subject matter of the present invention, and thus only the essential components directly related to the technical spirit of the present invention will be referred to. .

In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure may be "on" or "under" the substrate, each layer (film), region, pad or pattern. "On" and "under" include both "directly" or "indirectly" formed through another layer, as described in do. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

The semiconductor memory device according to the exemplary embodiment may be combined with various applied voltages, and may process write / delete / read operations in various operation methods, for example, HCI or FN tunneling, as necessary.

In addition, the semiconductor memory device according to the embodiment may be a NMOS type nonvolatile memory such as a flash device or an electrically erasable programmable read-only memory (EEPROM).

Hereinafter, six embodiments according to a combination of various applied voltages will be described, but the structure of the semiconductor memory device applied to each embodiment is the same.

That is, the structure of the semiconductor device shown in Figs. 2, 4, 6, 8, 10, 12 is the same, but, first, the voltage application method is different, and second, the operation method at the time of write / erase / read operation Third, the function of the ion implantation region is different, and fourth, the cell array structure is different.

Therefore, in the description of each embodiment, repeated descriptions related to the structure will be omitted.

Hereinafter, the semiconductor memory device according to the first embodiment will be described.

FIG. 2 is a side cross-sectional view schematically illustrating a shape of a semiconductor memory device according to a first embodiment and a current flow during a write / erase operation, and FIG. 3 schematically illustrates a cell array of a semiconductor memory device according to a first embodiment. It is a top view.

The semiconductor memory device according to the first exemplary embodiment illustrated in FIG. 2 illustrates a unit cell of a region indicated by a dotted line in the cell array of FIG. 3.

2, the semiconductor substrate 100, the first ion implantation region 110, the second ion implantation region 130, the third ion implantation region 120, the select gate 140, and the first ion implantation region 110. The first insulating layer 142, the second insulating layer 152, the floating gate 154, the ONO layer 156, and the control gate 157 are included.

In the following embodiments, the first ion implantation region 110 and the third ion implantation region 120 may function as the source region and the drain region, or vice versa, according to a voltage application method.

The first embodiment is operated by the control method of the selection gate 140, the first ion implantation region 110 functions as a source region, and the third ion implantation region 120 functions as a drain region.

The second ion implantation region 130 is formed in an area of the semiconductor substrate 100 between the selection gate 140 and the floating gate 154, and the first ion implantation region 110 and the third ion. It functions as a channel connection region of the injection region 120.

The first insulating layer 142 is formed under the selection gate 140 and functions as a gate insulating layer of the selection gate 140.

In addition, the second insulating layer 152 is formed under the floating gate 154 and functions as a gate insulating layer of the floating gate 154.

A fourth ion implantation region and a fifth ion implantation region for channel formation may be formed on the semiconductor substrate 100 under the first insulation layer 142 and the second insulation layer 152, respectively.

For reference, although not shown in FIG. 2, the semiconductor substrate 100 may include a three-layer well structure.

In addition, a lightly doped drain (LDD) region may be further formed as shown in regions “A” and “B” of FIG. 2.

In order to operate the semiconductor memory device according to the first embodiment by writing / deleting / reading, a voltage is applied as shown in Table 2 below. In FIG. 2, an arrow indicated by a dotted line indicates a current flow during a write operation. Arrows marked with indicate the current flow during the erase operation.

action Control Gate Voltage (Vcg) Select Gate Voltage (Vsg) Drain voltage (Vd) Source voltage (Vs) Bulk Voltage (Vsub) writing

Select cell Positive potential first voltage Third voltage Fourth voltage 0 V 0 V Bit line shared cell (A) 0 V 0 V Fourth voltage 0 V 0 V Word line
Shared cell (B) Positive potential first voltage Third voltage Floating 0 V 0 V delete Negative potential first voltage 0 V Floating Positive potential first voltage Positive potential first voltage read Second voltage Third voltage About 1V 0 V 0 V

Referring to Table 2 as follows.

First, the source voltage is applied to the first ion implantation region 110.

Second, the drain voltage is applied to the third ion implantation region 120.

Third, the bulk voltage is applied to the semiconductor substrate 100.

Fourth, referring to FIG. 3, the cell array according to the first embodiment has a structure that is symmetrical upward and downward with respect to the division region C, and the selection gate 140 (SG-1) is separated from the division region C. The control gate 157 constituting the second word line W / L-2 and the control gate 157 constituting the first word line W / L-1 are repeated.

The vertical region is a bit line B / L-n and refers to an active region in which the ion implantation layers 110, 120, and 130 are formed.

Fifth, the bit line sharing cell refers to a cell sharing a bit line B / L with a unit cell (dotted line area) selected in the first embodiment, for example, an “A” region of FIG. 3. As shown in Table 2, when a voltage is applied to operate a unit cell according to the first embodiment as a write / delete / read operation, disturbance is also generated in other cells sharing a bit line. In addition, voltages may be applied to other cells sharing bit lines other than the selected cell, for example, cells in an “A” region as shown in Table 2.

Sixth, the word line sharing cell refers to a cell sharing the word line (W / L) and the unit cell (dotted area) selected in the first embodiment, for example, the "B" region of FIG. As shown in Table 2, when a voltage is applied to operate a unit cell according to the first embodiment as a write / delete / read operation, a disturbance is generated in other cells sharing a word line. Voltages may be applied to other cells sharing a word line other than the selected cell, for example, a cell in an “B” region, as shown in Table 2.

Seventh, therefore, the semiconductor memory device according to the first embodiment is operated in the HCI method during the write operation, and operated in the FN tunneling method during the erase operation.

Hereinafter, the semiconductor memory device according to the second embodiment will be described.

FIG. 4 is a side cross-sectional view schematically illustrating the shape of the semiconductor memory device according to the first embodiment and a current flow during a write / erase operation, and FIG. 5 schematically illustrates a cell array of the semiconductor memory device according to the second embodiment. It is a top view.

The semiconductor memory device according to the first exemplary embodiment illustrated in FIG. 4 illustrates unit cells of a region indicated by a dotted line in the cell array of FIG. 5.

The second embodiment excludes the selection gate 140, operates the direct control gate of the control gate 157, and the first ion implantation region 110 functions as a drain region. The third ion implantation region 120 functions as a source region.

In order to operate the semiconductor memory device according to the first embodiment by writing / deleting / reading, a voltage is applied as shown in Table 3 below. In FIG. 4, an arrow indicated by a dotted line indicates a current flow during a write operation. Arrows marked with indicate the current flow during the erase operation.

action Control Gate Voltage (Vcg) Select Gate Voltage (Vsg) Drain voltage (Vd) Source voltage (Vs) Bulk Voltage (Vsub) writing

Select cell First voltage Third voltage Fourth voltage 0 V 0 V Word line
Shared cell (A) First voltage Third voltage Floating 0 V 0 V delete Negative potential first voltage 0 V Floating Fourth voltage Fourth voltage read Second voltage Third voltage About 1V 0 V 0 V

Referring to Table 3 as follows.

First, the drain voltage is applied to the first ion implantation region 110.

Second, the source voltage is applied to the third ion implantation region 120.

Third, the bulk voltage is applied to the semiconductor substrate 100.

Fourth, referring to FIG. 5, the cell array according to the second embodiment has a structure that is symmetrical upward and downward based on the division region C, and the word line W / L-1 is separated from the division region C. FIG. The control gate 157, the second select gate 140 (S / G-2), and the first select gate 140 (S / G-1) are repeated.

Fifth, the second embodiment has a structure in which the selection gate 140 is continuously arranged (in the case of the first embodiment, the control gate 157 is continuously arranged), and as in the first embodiment, the bit line sharing cell There is no need to consider the impact on the system.

Sixth, the word line sharing cell refers to a cell sharing the word line (W / L) and the unit cell (dotted line area) selected in the first embodiment, for example, the "A" region of FIG. As shown in Table 3, when a voltage is applied to operate a unit cell according to the second embodiment as a write / delete / read operation, disturbance is generated in other cells sharing a word line. Voltages may be applied to other cells sharing a word line other than the selected cell, for example, cells in an “A” region as shown in Table 3.

Seventh, therefore, the semiconductor memory device according to the second embodiment is operated in the HCI method during the write operation, and operated in the FN tunneling method during the erase operation.

Hereinafter, the semiconductor memory device according to the third embodiment will be described.

FIG. 6 is a side cross-sectional view schematically illustrating a shape of a semiconductor memory device and a current flow during a write / erase operation according to a third embodiment, and FIG. 7 schematically illustrates a cell array of a semiconductor memory device according to a third embodiment. It is a top view.

6 illustrates a unit cell of a region indicated by a dotted line in the cell array of FIG. 7.

The third embodiment is operated by the control method of the selection gate 140, the first ion implantation region 110 functions as a drain region, and the third ion implantation region 120 functions as a source region.

In order to operate the semiconductor memory device according to the third embodiment by writing / deleting / reading, a voltage is applied as shown in Table 4 below. In FIG. Arrows marked with indicate the current flow during the erase operation.

action Control Gate Voltage (Vcg) Select Gate Voltage (Vsg) Drain voltage (Vd) Source voltage (Vs) Bulk Voltage (Vsub) writing

Select cell First voltage Third voltage Negative potential fourth voltage Floating Negative potential fourth voltage Word line
Shared cell (A) First voltage Third voltage Floating Floating Negative potential fourth voltage delete Negative potential first voltage 0 V Floating Fourth voltage Fourth voltage read Second voltage Third voltage About 1V 0 V 0 V

Referring to Table 4 as follows.

First, the drain voltage is applied to the first ion implantation region 110.

Second, the source voltage is applied to the third ion implantation region 120.

Third, the bulk voltage is applied to the semiconductor substrate 100.

Fourth, referring to FIG. 6, the cell array according to the third exemplary embodiment has a structure in which the cell array is symmetrical upward and downward with respect to the division region C, and the word line W / L-1 is separated from the division region C. Referring to FIG. The control gate 157, the second select gate 140 (S / G-2), and the first select gate 140 (S / G-1) are repeated.

Fifth, the selection gate 140 has a structure in which the selection gate 140 is continuously arranged, and thus it is not necessary to consider the influence on the bit line sharing cell as in the first embodiment.

Sixth, the word line sharing cell refers to a cell sharing the word line (W / L) and the unit cell (dotted line area) selected in the first embodiment, for example, the "A" region of FIG. As shown in Table 4, when a voltage is applied to operate a unit cell according to the third embodiment as a write / delete / read operation, disturbance is also generated in other cells sharing a word line. Voltages may be applied to other cells sharing a word line other than the selected cell, for example, cells in an “A” region as shown in Table 4.

Seventh, therefore, the semiconductor memory device according to the third embodiment is operated in the FN tunneling scheme during the write operation, and in the FN tunneling scheme during the erase operation.

Hereinafter, the semiconductor memory device according to the fourth embodiment will be described.

FIG. 8 is a side cross-sectional view schematically illustrating a shape of a semiconductor memory device according to a fourth embodiment and a current flow during a write / erase operation, and FIG. 9 schematically illustrates a cell array of a semiconductor memory device according to a fourth embodiment. It is a top view.

The semiconductor memory device according to the fourth exemplary embodiment illustrated in FIG. 8 illustrates unit cells in regions indicated by dotted lines in the cell array of FIG. 9.

The fourth embodiment excludes the select gate 140, operates the direct control gate of the control gate 157, and the first ion implantation region 110 functions as a source region. The third ion implantation region 120 functions as a drain region.

In order to operate the semiconductor memory device according to the fourth embodiment by writing / deleting / reading, a voltage is applied as shown in Table 5 below. In FIG. Arrows marked with indicate the current flow during the erase operation.

action Control Gate Voltage (Vcg) Select Gate Voltage (Vsg) Drain voltage (Vd) Source voltage (Vs) Bulk Voltage (Vsub) writing

Select cell First voltage 0 V Negative potential first voltage Floating Negative potential first voltage Bit line shared cell (A) 0 V 0 V Negative potential first voltage Floating Negative potential first voltage Word line
Shared cell (B) First voltage 0 V Floating Floating Negative potential first voltage delete Negative potential first voltage 0 V Floating First voltage First voltage read Second voltage Third voltage About 1V 0 V 0 V

Referring to Table 5 as follows.

First, the source voltage is applied to the first ion implantation region 110.

Second, the drain voltage is applied to the third ion implantation region 120.

Third, the bulk voltage is applied to the semiconductor substrate 100.

Fourth, referring to FIG. 9, the cell array according to the fourth embodiment has a structure that is symmetrical upward and downward with respect to the division region C, and the selection gate 140 (SG-1) is formed from the division region C. The control gate 157 constituting the second word line W / L-2 and the control gate 157 constituting the first word line W / L-1 are repeated.

Fifth, the bit line sharing cell refers to a cell sharing a bit line B / L with a unit cell (dotted line area) selected in the fourth embodiment, for example, an “A” region of FIG. 9. As shown in Table 5, when a voltage is applied to operate the unit cell according to the fourth embodiment to write / delete / read, influence is generated on other cells sharing the bit line. Voltages may be applied to other cells sharing a bit line other than the selected cell, for example, cells in an “A” region as shown in Table 5.

Sixth, the word line sharing cell refers to a cell sharing the word line (W / L) and the unit cell (dotted area) selected in the fourth embodiment, for example, the "B" region of FIG. As shown in Table 5, when a voltage is applied to operate a unit cell according to the fourth embodiment as a write / delete / read operation, disturbance is also generated in other cells sharing a word line. Voltages may be applied to other cells sharing a word line other than the selected cell, for example, a cell in an area of “B”.

Seventh, therefore, the semiconductor memory device according to the fourth embodiment is operated in the FN tunneling method during the write operation, and operated in the FN tunneling method during the erase operation.

Hereinafter, the semiconductor memory device according to the fifth embodiment will be described.

FIG. 10 is a side cross-sectional view schematically illustrating a shape of a semiconductor memory device according to a fifth embodiment and a current flow during a write / erase operation, and FIG. 11 schematically illustrates a cell array of a semiconductor memory device according to a fifth embodiment. It is a top view.

The semiconductor memory device according to the fifth exemplary embodiment illustrated in FIG. 10 illustrates a unit cell of a region indicated by a dotted line in the cell array of FIG. 11.

The fifth embodiment is operated by the control method of the selection gate 140, the first ion implantation region 110 functions as a drain region, and the third ion implantation region 120 functions as a source region.

In order to operate the semiconductor memory device according to the fifth embodiment by writing / deleting / reading, a voltage is applied as shown in Table 6 below. In FIG. 10, an arrow indicated by a dotted line indicates a current flow during a write operation. Arrows marked with indicate the current flow during the erase operation.

action Control Gate Voltage (Vcg) Select Gate Voltage (Vsg) Drain voltage (Vd) Source voltage (Vs) Bulk Voltage (Vsub) writing

Select cell Negative potential first voltage First voltage Fourth voltage Floating 0 V Word line
Shared cell (A) Negative potential first voltage First voltage Floating Floating 0 V delete First voltage 0 V Floating Negative potential first voltage Negative potential first voltage read Second voltage Third voltage About 1V 0 V 0 V

Referring to Table 6 as follows.

First, the drain voltage is applied to the first ion implantation region 110.

Second, the source voltage is applied to the third ion implantation region 120.

Third, the bulk voltage is applied to the semiconductor substrate 100.

Fourth, referring to FIG. 11, the cell array according to the fifth embodiment has a structure that is symmetrical upward and downward with respect to the division region C, and the word line W / L-1 is separated from the division region C. Referring to FIG. The control gate 157, the second select gate 140 (S / G-2), and the first select gate 140 (S / G-1) are repeated.

Fifth, the fifth embodiment is a structure in which the selection gate 140 is continuously arranged (in the case of the first embodiment, the control gate 157 is continuously arranged), and as in the first embodiment, the bit line sharing cell There is no need to consider the impact on the system.

Sixth, the word line sharing cell refers to a cell sharing the word line (W / L) and the unit cell (dotted area) selected in the fifth embodiment, for example, the "A" region of FIG. As shown in Table 6, when a voltage is applied to operate a unit cell according to the fifth embodiment as a write / delete / read operation, disturbance is generated in other cells sharing a word line. Voltages may be applied to other cells sharing a word line other than the selected cell, for example, cells in an “A” region as shown in Table 6.

Seventh, therefore, the semiconductor memory device according to the fifth embodiment is operated in the FN tunneling method during the write operation, and operated in the FN tunneling method during the erase operation.

Hereinafter, the semiconductor memory device according to the sixth embodiment will be described.

FIG. 12 is a side cross-sectional view schematically illustrating a shape of a semiconductor memory device and a current flow during a write / erase operation according to a sixth embodiment, and FIG. 13 schematically illustrates a cell array of a semiconductor memory device according to a sixth embodiment. It is a top view.

The semiconductor memory device according to the sixth exemplary embodiment illustrated in FIG. 12 illustrates a unit cell of a region indicated by a dotted line in the cell array of FIG. 13.

The sixth embodiment excludes the select gate 140, operates the direct control gate of the control gate 157, and the first ion implantation region 110 functions as a source region. The third ion implantation region 120 functions as a drain region.

In order to operate the semiconductor memory device according to the sixth embodiment by writing / deleting / reading, a voltage is applied as shown in Table 7 below. In FIG. 12, an arrow indicated by a dotted line indicates a current flow during a write operation. Arrows marked with indicate the current flow during the erase operation.

action Control Gate Voltage (Vcg) Select Gate Voltage (Vsg) Drain voltage (Vd) Source voltage (Vs) Bulk Voltage (Vsub) writing

Select cell Negative potential first voltage 0 V First voltage 0 V 0 V Bit line shared cell (A) 0 V 0 V First voltage 0 V 0 V Word line
Shared cell (B) Negative potential first voltage 0 V Floating 0 V 0 V delete First voltage 0 V Floating Negative potential first voltage Negative potential first voltage read Second voltage Third voltage About 1V 0 V 0 V

Referring to Table 7, it is as follows.

First, the source voltage is applied to the first ion implantation region 110.

Second, the drain voltage is applied to the third ion implantation region 120.

Third, the bulk voltage is applied to the semiconductor substrate 100.

Fourth, referring to FIG. 13, the cell array according to the sixth embodiment has a structure that is symmetrical upward and downward with respect to the division region C. From the division region C, the selection gate 140 (SG-1) is formed. The control gate 157 constituting the second word line W / L-2 and the control gate 157 constituting the first word line W / L-1 are repeated.

Fifth, the bit line sharing cell refers to a cell sharing a bit line B / L with a unit cell (dotted line area) selected in the sixth embodiment, for example, an “A” region of FIG. 13. As shown in Table 7, when a voltage is applied to operate a unit cell according to the sixth embodiment to write / delete / read, a distinction occurs in other cells sharing a bit line. Voltages may be applied to other cells sharing a bit line other than the selected cell, for example, cells in an “A” region as shown in Table 7.

Sixth, the word line sharing cell refers to a cell sharing the word line (W / L) and the unit cell (dotted area) selected in the sixth embodiment, for example, the "B" region of FIG. When a voltage is applied to operate the unit cell according to the sixth embodiment to write / delete / read according to the sixth embodiment, disturbance is also generated in other cells sharing the word line. Voltages may be applied to other cells sharing a word line other than the selected cell, for example, a cell in an “B” region, as shown in Table 7.

Seventh, therefore, the semiconductor memory device according to the sixth embodiment is operated in the FN tunneling method during the write operation, and operated in the FN tunneling method during the erase operation.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications other than those described above are possible. For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. And differences relating to such modifications and applications are included in the appended claims.

1 is a view schematically illustrating a current flow when a general flash device is programmed or erased.

Fig. 2 is a side cross-sectional view schematically illustrating the shape of the semiconductor memory device and the current flow during write / erase operations according to the first embodiment.

3 is a top view schematically showing a cell array of the semiconductor memory device according to the first embodiment;

Fig. 4 is a side sectional view schematically illustrating the shape of the semiconductor memory element according to the first embodiment and the current flow during write / erase operations.

5 is a top view schematically showing a cell array of the semiconductor memory device according to the second embodiment.

Fig. 6 is a side cross-sectional view schematically illustrating the shape of a semiconductor memory element and a current flow during write / erase operations according to the third embodiment.

7 is a top view schematically showing a cell array of a semiconductor memory device according to the third embodiment;

Fig. 8 is a side sectional view schematically illustrating the shape of a semiconductor memory element and a current flow during write / erase operations according to the fourth embodiment.

9 is a top view schematically showing a cell array of the semiconductor memory device according to the fourth embodiment.

Fig. 10 is a side cross-sectional view schematically illustrating the shape of a semiconductor memory device and a current flow during write / erase operations according to the fifth embodiment.

Fig. 11 is a top view schematically showing a cell array of a semiconductor memory device according to the fifth embodiment.

Fig. 12 is a side cross-sectional view schematically illustrating the shape of a semiconductor memory element according to the sixth embodiment and a current flow during write / erase operations.

13 is a top view schematically showing a cell array of a semiconductor memory device according to the sixth embodiment;

Claims (21)

A selection gate formed over the semiconductor substrate; A floating gate spaced apart from the selection gate and formed on the semiconductor substrate; An ONO layer formed on the floating gate; A control gate formed on the ONO layer; A first ion implantation region formed in the semiconductor substrate on one side of the selection gate; A second ion implantation region formed in the semiconductor substrate between the selection gate and the floating gate; And A third ion implantation region formed in the semiconductor substrate on one side of the floating gate, The first ion implantation region and the third ion implantation region function as a source region and a drain region, respectively, or vice versa according to a voltage application method. And the second ion implantation region functions as a channel connection region between the first ion implantation region and the third ion implantation region. The method of claim 1, A first insulating layer formed between the selection gate and the semiconductor substrate; And And a second insulating layer formed between the floating gate and the semiconductor substrate. The method of claim 1, wherein the semiconductor memory device forms a cell array. The cell array has a structure in which the select gate, the control gate forming a second word line, and the control gate forming a first word line are repeated. The active region in which the ion implantation layers are formed constitutes a bit line of the cell array. In each case of a write / erase / read operation, a positive first voltage, a first negative voltage, and a second voltage are applied to the control gate, and a third voltage, 0 V, and a third voltage are applied to the selection gate, and a drain A fourth voltage, a floating state, 0.5V to 1.5V is applied to the third ion implantation region functioning as 0V, a positive potential first voltage, 0V to the first ion implantation region functioning as a source, 0V, a positive potential first voltage, 0V is applied to the semiconductor substrate. The method of claim 3, In the case of another cell sharing a bit line with a cell of the semiconductor memory device selected for a write / delete / read operation, a control gate, a select gate, a third ion implantation region, a first ion implantation region, and a semiconductor substrate of the other cell 0V, 0V, fourth voltage, 0V, 0V are respectively applied to the In the case of another cell sharing a word line with a cell of the semiconductor memory device selected for a write / erase / read operation, a control gate, a select gate, a third ion implantation region, a first ion implantation region, and a semiconductor substrate of the other cell The semiconductor memory device, characterized in that the positive potential first voltage, third voltage, floating state, 0V, 0V are applied to each. The method of claim 3, And a HCI method in a write operation, and an FN tunneling method in an erase operation. The method of claim 1, wherein the semiconductor memory device forms a cell array. The cell array has a structure in which the control gate forming a word line and the two selection gates forming a continuous line are repeated. The active region in which the ion implantation layers are formed constitutes a bit line of the cell array. In each case of a write / erase / read operation, a first voltage, a negative potential first voltage, and a second voltage are applied to the control gate, and a third voltage, 0V, and a third voltage are applied to the control gate, and function as a drain. A fourth voltage, a floating state, and 0.5V to 1.5V are applied to the first ion implantation region, and 0V, a fourth voltage, and 0V are applied to the third ion implantation region serving as a source, and to the semiconductor substrate. 0V, 0V, 0V are applied to the semiconductor memory device. The method of claim 6, In the case of another cell sharing a word line with a cell of the semiconductor memory device selected for a write / erase / read operation, a control gate, a select gate, a third ion implantation region, a first ion implantation region, and a semiconductor substrate of the other cell And a first voltage, a third voltage, a floating state, and 0V and 0V, respectively. The method of claim 6, And excluding the selection gate, operating the direct control method of the control gate, operating the HCI method in a write operation, and operating the FN tunneling method in an erase operation. The method of claim 1, wherein the semiconductor memory device forms a cell array. The cell array has a structure in which the control gate forming a word line and the two selection gates forming a continuous line are repeated. The active region in which the ion implantation layers are formed constitutes a bit line of the cell array. In each case of a write / erase / read operation, a first voltage, a negative potential first voltage, and a second voltage are applied to the control gate, and a third voltage, 0V, and a third voltage are applied to the control gate, and function as a drain. A fourth voltage, a floating state, 0.5V to 1.5V is applied to the first ion implantation region, and a floating state, a fourth voltage, 0V is applied to the third ion implantation region serving as a source, and the semiconductor substrate The negative potential fourth voltage, the fourth voltage, 0V is applied to the semiconductor memory device. 10. The method of claim 9, In the case of another cell sharing a word line with a cell of the semiconductor memory device selected for a write / erase / read operation, a control gate, a select gate, a third ion implantation region, a first ion implantation region, and a semiconductor substrate of the other cell And a first voltage, a third voltage, a floating state, a floating state, and a negative potential fourth voltage, respectively. 10. The method of claim 9, And a FN tunneling method during a write operation, and an FN tunneling method during an erase operation. The method of claim 1, wherein the semiconductor memory device forms a cell array. The cell array has a structure in which the select gate, the control gate forming a second word line, and the control gate forming a first word line are repeated. The active region in which the ion implantation layers are formed constitutes a bit line of the cell array. In each case of a write / erase / read operation, a first voltage, a negative potential first voltage, and a second voltage are applied to the control gate, and 0 V, 0 V, and a third voltage are applied to the selection gate, and the drain gate functions as a drain. A first negative potential voltage, a floating state, 0.5V to 1.5V is applied to the third ion implantation region, and a floating state, a first voltage, 0V is applied to the first ion implantation region serving as a source, and to the semiconductor substrate. A negative potential first voltage, a first voltage, and 0V are applied to the semiconductor memory device. The method of claim 12, In the case of another cell sharing a bit line with a cell of the semiconductor memory device selected for a write / delete / read operation, a control gate, a select gate, a third ion implantation region, a first ion implantation region, and a semiconductor substrate of the other cell 0V, 0V, a negative potential first voltage, a floating state, and a negative potential first voltage, respectively, In the case of another cell sharing a word line with a cell of the semiconductor memory device selected for a write / erase / read operation, a control gate, a select gate, a third ion implantation region, a first ion implantation region, and a semiconductor substrate of the other cell And a first voltage, 0 V, a floating state, a floating state, and a negative potential first voltage, respectively. The method of claim 12, And excluding the selection gate, operating in a direct control method of the control gate, operating in an FN tunneling method in a write operation, and operating in an FN tunneling method in an erase operation. The method of claim 1, wherein the semiconductor memory device forms a cell array. The cell array has a structure in which the control gate forming a word line and the two selection gates forming a continuous line are repeated. The active region in which the ion implantation layers are formed constitutes a bit line of the cell array. In each case of a write / erase / read operation, a negative potential first voltage, a first voltage, and a second voltage are applied to the control gate, and a first voltage, 0V, and a third voltage are applied to the selection gate, and serve as a drain. A fourth voltage, a floating state, 0.5V to 1.5V is applied to the first ion implantation region, and a floating state, a negative potential first voltage, 0V is applied to the third ion implantation region serving as a source, and the semiconductor 0V, a negative potential first voltage, 0V is applied to the substrate. The method of claim 15, In the case of another cell sharing a word line with a cell of the semiconductor memory device selected for a write / erase / read operation, a control gate, a select gate, a third ion implantation region, a first ion implantation region, and a semiconductor substrate of the other cell The semiconductor memory device according to claim 1, wherein a negative potential first voltage, a first voltage, a floating state, a floating state, and 0V are respectively applied to the negative potential. The method of claim 15, And a FN tunneling method during a write operation, and an FN tunneling method during an erase operation. The method of claim 1, wherein the semiconductor memory device forms a cell array. The cell array has a structure in which the select gate, the control gate forming a second word line, and the control gate forming a first word line are repeated. The active region in which the ion implantation layers are formed constitutes a bit line of the cell array. In each case of a write / erase / read operation, a negative potential first voltage, a first voltage, and a second voltage are applied to the control gate, and 0 V, 0 V, and a third voltage are applied to the selection gate, and the drain gate functions as a drain. A first voltage, a floating state, 0.5V to 1.5V is applied to the third ion implantation region, 0V, a negative potential first voltage, 0V is applied to the first ion implantation region serving as a source, and 0V to the semiconductor substrate. And a first negative potential voltage of 0 V is applied. The method of claim 18, In the case of another cell sharing a bit line with a cell of the semiconductor memory device selected for a write / delete / read operation, a control gate, a select gate, a third ion implantation region, a first ion implantation region, and a semiconductor substrate of the other cell 0V, 0V, first voltage, 0V, 0V are applied to the In the case of another cell sharing a word line with a cell of the semiconductor memory device selected for a write / erase / read operation, a control gate, a select gate, a third ion implantation region, a first ion implantation region, and a semiconductor substrate of the other cell And a negative potential first voltage, 0V, a floating state, 0V, and 0V, respectively. The method of claim 18, And excluding the selection gate, operating in the direct control method of the control gate, operating in the FN tunneling method during a write operation, and operating in the FN tunneling method during an erase operation. The method according to any one of claims 3, 6, 9, 12, 15, and 18, And wherein the cell array has a division region, and has a structure that is symmetrical upward and downward with respect to the division region, and wherein the selection gate and the control gate are repeated above and below the division region.

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